diff --git a/Ghidra/Processors/PowerPC/certification.manifest b/Ghidra/Processors/PowerPC/certification.manifest
index d97e6d9b66..6ccaccdc57 100644
--- a/Ghidra/Processors/PowerPC/certification.manifest
+++ b/Ghidra/Processors/PowerPC/certification.manifest
@@ -28,6 +28,10 @@ data/languages/ppc_32_e500_be.cspec||GHIDRA||||END|
data/languages/ppc_32_e500_be.slaspec||GHIDRA||||END|
data/languages/ppc_32_e500_le.cspec||GHIDRA||||END|
data/languages/ppc_32_e500_le.slaspec||GHIDRA||||END|
+data/languages/ppc_32_e500mc_be.cspec||GHIDRA||||END|
+data/languages/ppc_32_e500mc_be.slaspec||GHIDRA||||END|
+data/languages/ppc_32_e500mc_le.cspec||GHIDRA||||END|
+data/languages/ppc_32_e500mc_le.slaspec||GHIDRA||||END|
data/languages/ppc_32_le.cspec||GHIDRA||||END|
data/languages/ppc_32_le.slaspec||GHIDRA||||END|
data/languages/ppc_32_mpc8270.pspec||GHIDRA||||END|
diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc.ldefs b/Ghidra/Processors/PowerPC/data/languages/ppc.ldefs
index 1d3dc8e043..abaf61fa89 100644
--- a/Ghidra/Processors/PowerPC/data/languages/ppc.ldefs
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc.ldefs
@@ -206,6 +206,36 @@
+
+ PowerQUICC-III e500mc 32-bit big-endian family
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+ PowerQUICC-III e500mc 32-bit little-endian family
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diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500mc_be.slaspec b/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500mc_be.slaspec
new file mode 100644
index 0000000000..d95cc07227
--- /dev/null
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500mc_be.slaspec
@@ -0,0 +1,23 @@
+# SLA specification file for IBM PowerPC e500 series core
+
+# NOTE: This language variant includes some registers and instructions not supported
+# by the actual processor (e.g., floating pointer registers and associated instructions).
+# The actual processor only supports a subset of the registers and instructions implemented.
+
+@define ENDIAN "big"
+
+@define REGISTER_SIZE "4"
+
+@define EATRUNC "ea"
+
+# e500mc has 32 bit registers
+#
+@define CTR_OFFSET "32"
+
+@define NoLegacyIntegerMultiplyAccumulate
+
+@include "ppc_common.sinc"
+@include "quicciii.sinc"
+@include "evx.sinc"
+@include "SPEF_SCR.sinc"
+
diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500mc_le.cspec b/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500mc_le.cspec
new file mode 100644
index 0000000000..845fbb9e3f
--- /dev/null
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500mc_le.cspec
@@ -0,0 +1,80 @@
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diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500mc_le.slaspec b/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500mc_le.slaspec
new file mode 100644
index 0000000000..dd9a9c20b7
--- /dev/null
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500mc_le.slaspec
@@ -0,0 +1,21 @@
+# SLA specification file for IBM PowerPC e500 series core
+
+#@define E500
+
+@define ENDIAN "little"
+
+@define REGISTER_SIZE "4"
+
+@define EATRUNC "ea"
+
+# e500mc has 32 bit registers
+#
+@define CTR_OFFSET "32"
+
+@define NoLegacyIntegerMultiplyAccumulate
+
+@include "ppc_common.sinc"
+@include "quicciii.sinc"
+@include "evx.sinc"
+@include "SPEF_SCR.sinc"
+