From 5ff2fa62b117c4022e33c2d0f6df2dd36a3122dd Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Tue, 19 Oct 2021 09:34:12 -0400 Subject: [PATCH] Correctly implemented missing arm thumb AL conditional --- Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc b/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc index b388ae9248..daf7057311 100644 --- a/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc +++ b/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc @@ -331,7 +331,7 @@ it_thfcc: "gt" is fcond=12 { tmp:1 = !ZR && (NG == OV); export tmp; } it_thfcc: "le" is fcond=13 { tmp:1 = !ZR && (NG == OV); export tmp; } it_thfcc: "al" is fcond=14 { tmp:1 = 1; export tmp; } -@define IT_THFCC "it_thfcc & (thc0707=0 | thc0606=0 | thc0505=0)" +@define IT_THFCC "it_thfcc & (thc0707=0 | thc0606=0 | thc0505=0 | thc0404=0)" ByteRotate: "#"^rot is throt [rot = throt << 3; ] { export *[const]:1 rot; }