diff --git a/Ghidra/Processors/68000/data/languages/68000.sinc b/Ghidra/Processors/68000/data/languages/68000.sinc
index 80587caa5b..1bc3202096 100644
--- a/Ghidra/Processors/68000/data/languages/68000.sinc
+++ b/Ghidra/Processors/68000/data/languages/68000.sinc
@@ -1,6 +1,7 @@
 # SLA specification for Motorola 68000 series
 
 define endian=big;
+define alignment=2;
 
 define space ram type=ram_space size=4 default;
 define space register type=register_space size=4;
@@ -11,7 +12,7 @@ define register offset=0 size=1      [ _ _ _ D0b _ _ _ D1b _ _ _ D2b _ _ _ D3b _
 define register offset=0x20 size=4   [ A0 A1 A2 A3 A4 A5 A6 SP ];   # Address registers
 define register offset=0x20 size=2   [ _ A0w _ A1w _ A2w _ A3w _ A4w _ A5w _ A6w _ A7w];
 define register offset=0x20 size=1   [ _ _ _ A0b _ _ _ A1b _ _ _ A2b _ _ _ A3b _ _ _ A4b _ _ _ A5b _ _ _ A6b _ _ _ A7b ];
-define register offset=0x40 size=1   [ XF NF ZF VF CF ];	    # Condition flags
+define register offset=0x40 size=1   [ TF SVF IPL XF NF ZF VF CF ];	    # Condition flags
 define register offset=0x50 size=4   PC;			    # Program counter register
 
 # Floating point registers are 80 bits internally, but are 96 bits to/from memory.
@@ -301,6 +302,7 @@ attach values quick [ 8 1 2 3 4 5 6 7 ];
 define pcodeop kfactor;
 define pcodeop ftrap;
 define pcodeop trap;
+define pcodeop trapv;
 define pcodeop reset;
 define pcodeop saveFPUStateFrame;
 define pcodeop restoreFPUStateFrame;
@@ -667,10 +669,13 @@ macro resbitflags(result, bitnum) {
 }
 
 macro packflags(res) {
-  res = zext((XF<<4)|(NF<<3)|(ZF<<2)|(VF<<1)|CF);
+  res = zext((TF<<15)|(SVF<<13)|(IPL<<8)|(XF<<4)|(NF<<3)|(ZF<<2)|(VF<<1)|CF);
 }
 
 macro unpackflags(in) {
+  TF = (in & 0x8000)!=0;
+  SVF = (in & 0x2000)!=0;
+  IPL = in[8,3];
   XF = (in & 0x10)!=0;
   NF = (in & 8)!=0;
   ZF = (in & 4)!=0;
@@ -1673,11 +1678,11 @@ ptestLevel: "#"^mregn	is mregn  { export *[const]:1 mregn; }
 :tas eab			is (opbig=0x4a & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eab				{ logflags(); resflags(eab); eab = eab | 0x80; }
 @endif # COLDFIRE
 
-:trap "#"^op03			is opbig=0x4e & op67=1 & op45=0 & op03			{ vector:1 = 32 + op03; trap(vector); }
-:trap^cc			is op=5 & cc & op37=31 & op02=4					{ if (!cc) goto inst_next; SP = SP - 4; *:4 SP = PC; vector:1 = 7; trap(vector); }
-:trap^cc^".w" "#"^d16		is op=5 & cc & op37=31 & op02=2; d16		{ if (!cc) goto inst_next; SP = SP - 4; *:4 SP = PC; vector:1 = 7; trap(vector); }
-:trap^cc^".l" "#"^d32		is op=5 & cc & op37=31 & op02=3; d32		{ if (!cc) goto inst_next; SP = SP - 4; *:4 SP = PC; vector:1 = 7; trap(vector); }
-:trapv				is opbig=0x4e & op37=14 & op02=6				{ if (!VF) goto inst_next; vector:1 = 7; trap(vector); }
+:trap "#"^op03			is opbig=0x4e & op67=1 & op45=0 & op03			{ vectoraddr:1 = (32 + op03)*4; trap(vectoraddr); }
+:trap^cc			is op=5 & cc & op37=31 & op02=4					{ if (!cc) goto inst_next; SP = SP - 4; *:4 SP = PC; vectoraddr:1 = (7*4); trapv(vectoraddr); }
+:trap^cc^".w" "#"^d16		is op=5 & cc & op37=31 & op02=2; d16		{ if (!cc) goto inst_next; SP = SP - 4; *:4 SP = PC; vectoraddr:1 = (7*4); trap(vectoraddr); }
+:trap^cc^".l" "#"^d32		is op=5 & cc & op37=31 & op02=3; d32		{ if (!cc) goto inst_next; SP = SP - 4; *:4 SP = PC; vectoraddr:1 = (7*4); trap(vectoraddr); }
+:trapv				is opbig=0x4e & op37=14 & op02=6				{ if (!VF) goto inst_next; vectoraddr:1 = (7*4); trap(vectoraddr); }
 
 :tst.b eab			is (opbig=0x4a & op67=0)... & eab				{ logflags(); resflags(eab); }
 :tst.w eaw			is (opbig=0x4a & op67=1)... & eaw				{ logflags(); resflags(eaw); }