From 8277a6312b77ae1cef2177a80147cd03d2444215 Mon Sep 17 00:00:00 2001 From: William Tan <1284324+Ninja3047@users.noreply.github.com> Date: Tue, 10 Jan 2023 17:10:36 -0500 Subject: [PATCH 1/3] fix: also decode eieio (mbar 0) for VLE --- Ghidra/Processors/PowerPC/data/languages/ppc_embedded.sinc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_embedded.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_embedded.sinc index b87271d9f6..4a07bc7632 100644 --- a/Ghidra/Processors/PowerPC/data/languages/ppc_embedded.sinc +++ b/Ghidra/Processors/PowerPC/data/languages/ppc_embedded.sinc @@ -52,7 +52,7 @@ @ifndef IS_ISA # this is equilent to "mbar 0" #eieio 0x7c 00 06 ac -:eieio is $(NOTVLE) & OP=31 & BITS_21_25=0 & BITS_16_20=0 & BITS_11_15=0 & XOP_1_10=854 & BIT_0=0 +:eieio is OP=31 & BITS_21_25=0 & BITS_16_20=0 & BITS_11_15=0 & XOP_1_10=854 & BIT_0=0 { enforceInOrderExecutionIO(); } From eebdca26684b03cc6ad7f51c51ba0e780eaba723 Mon Sep 17 00:00:00 2001 From: William Tan <1284324+Ninja3047@users.noreply.github.com> Date: Wed, 11 Jan 2023 14:25:45 -0500 Subject: [PATCH 2/3] move mbar from a2 to ppc_embedded, remove duplicate eieio --- .../Processors/PowerPC/data/languages/ppc_a2.sinc | 8 -------- .../PowerPC/data/languages/ppc_embedded.sinc | 13 ++++++------- 2 files changed, 6 insertions(+), 15 deletions(-) diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_a2.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_a2.sinc index 4de9773933..28296d72d2 100644 --- a/Ghidra/Processors/PowerPC/data/languages/ppc_a2.sinc +++ b/Ghidra/Processors/PowerPC/data/languages/ppc_a2.sinc @@ -85,14 +85,6 @@ define pcodeop wclrallOp; define pcodeop wclrOp; # :wclr L,A,B is $(NOTVLE) & OP=31 & XOP_1_10=934 & L & A & B { wclrOp(); } -@ifdef IS_ISA -# binutils: 476.d 474: 7c 00 06 ac mbar -# binutils: 476.d 47c: 7c 20 06 ac mbar 1 -# "mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, PPCNONE, {MO} -define pcodeop mbarOp; -:mbar MO is OP=31 & XOP_1_10=854 & MO { mbarOp(); } -@endif - # binutils: a2.d: 514: 7d 4a 3a 87 mfdcr\. r10,234 :mfdcr. D, DCRN is $(NOTVLE) & OP=31 & D & DCRN & XOP_1_10=323 & BIT_0=1 { diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_embedded.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_embedded.sinc index 4a07bc7632..a7ea6f3cda 100644 --- a/Ghidra/Processors/PowerPC/data/languages/ppc_embedded.sinc +++ b/Ghidra/Processors/PowerPC/data/languages/ppc_embedded.sinc @@ -49,13 +49,12 @@ dataCacheBlockClearToZero(ea); } -@ifndef IS_ISA -# this is equilent to "mbar 0" -#eieio 0x7c 00 06 ac -:eieio is OP=31 & BITS_21_25=0 & BITS_16_20=0 & BITS_11_15=0 & XOP_1_10=854 & BIT_0=0 -{ - enforceInOrderExecutionIO(); -} +@ifdef IS_ISA +# binutils: 476.d 474: 7c 00 06 ac mbar +# binutils: 476.d 47c: 7c 20 06 ac mbar 1 +# "mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, PPCNONE, {MO} +define pcodeop mbarOp; +:mbar MO is OP=31 & XOP_1_10=854 & MO { mbarOp(); } @endif #icbi r0,r0 0x7c 00 07 ac From 9c694ebfd1cf99f02a094dc6568e4544d981719e Mon Sep 17 00:00:00 2001 From: William Tan <1284324+Ninja3047@users.noreply.github.com> Date: Fri, 5 May 2023 11:12:29 -0400 Subject: [PATCH 3/3] move around mbar/eieio --- .../PowerPC/data/languages/ppc_embedded.sinc | 13 ++++++------- .../PowerPC/data/languages/ppc_instructions.sinc | 7 +++++++ .../Processors/PowerPC/data/languages/ppc_isa.sinc | 8 -------- .../Processors/PowerPC/data/languages/quicciii.sinc | 9 --------- 4 files changed, 13 insertions(+), 24 deletions(-) diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_embedded.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_embedded.sinc index a7ea6f3cda..f826beae39 100644 --- a/Ghidra/Processors/PowerPC/data/languages/ppc_embedded.sinc +++ b/Ghidra/Processors/PowerPC/data/languages/ppc_embedded.sinc @@ -49,13 +49,12 @@ dataCacheBlockClearToZero(ea); } -@ifdef IS_ISA -# binutils: 476.d 474: 7c 00 06 ac mbar -# binutils: 476.d 47c: 7c 20 06 ac mbar 1 -# "mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, PPCNONE, {MO} -define pcodeop mbarOp; -:mbar MO is OP=31 & XOP_1_10=854 & MO { mbarOp(); } -@endif +define pcodeop memoryBarrier; +#mbar 0 7c 00 06 ac +:mbar MO is OP=31 & MO & XOP_1_10=854 +{ + memoryBarrier(MO:1); +} #icbi r0,r0 0x7c 00 07 ac :icbi RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=982 & BIT_0=0 & RA_OR_ZERO diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc index b9ca56c0ff..9ed6c843ab 100644 --- a/Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc +++ b/Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc @@ -1087,6 +1087,13 @@ externalControlOut(ea, S); } +#=========================================================== +# EIEIO +#=========================================================== +# binutils-descr: "eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0} +# binutils: mytest.d: 20: 7c 00 06 ac eieio +:eieio is OP=31 & XOP_1_10=854 & BITS_11_25=0 & BIT_0=0 { enforceInOrderExecutionIO(); } + #=========================================================== # EQVx #=========================================================== diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc index 3148135f19..523ec943b2 100644 --- a/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc +++ b/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc @@ -1625,14 +1625,6 @@ define pcodeop lbzcixOp; RT = *:1 A; } -# binutils-descr: "eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0} -define pcodeop eieioOp; -# ISA-cmt: eieio - Enforce In-order Execution of I/O -# ISA-info: eieio - Form "X" Page 698 Category "S" -# binutils: mytest.d: 20: 7c 00 06 ac eieio -:eieio is $(NOTVLE) & OP=31 & XOP_1_10=854 & BITS_11_25=0 & BIT_0=0 { eieioOp(); } - - # binutils-descr: "ldcix", X(31,885), X_MASK, POWER6, PPCNONE, {RT, RA0, RB} # ISA-cmt: ldcix - Load Doubleword Caching Inhibited Indexed # ISA-info: ldcix - Form "X" Page 749 Category "S" diff --git a/Ghidra/Processors/PowerPC/data/languages/quicciii.sinc b/Ghidra/Processors/PowerPC/data/languages/quicciii.sinc index 8b7977bce2..c9958477e9 100644 --- a/Ghidra/Processors/PowerPC/data/languages/quicciii.sinc +++ b/Ghidra/Processors/PowerPC/data/languages/quicciii.sinc @@ -8,7 +8,6 @@ define pcodeop debuggerNotifyHalt; define pcodeop instructionCacheBlockClearLock; define pcodeop queryInstructionCacheBlockLock; define pcodeop prefetchInstructionCacheBlockLockSetX; -define pcodeop memoryBarrier; define pcodeop moveFromAPIDIndirect; define pcodeop moveFromPerformanceMonitorRegister; define pcodeop moveToPerformanceMonitorRegister; @@ -70,14 +69,6 @@ define pcodeop invalidateTLB; # D = (zext(CC_X_OP) * RA_OR_ZERO) + (zext(!CC_X_OP) * B); } -@ifndef IS_ISA -#mbar 0 #FIXME -:mbar MO is OP=31 & MO & XOP_1_10=854 -{ - memoryBarrier(MO:1); -} -@endif - #mfapidi r0,r1 #FIXME :mfapidi D,A is $(NOTVLE) & OP=31 & D & A & XOP_1_10=275 {