From 9f999c2ffcfe4953c2c2279003e5116256e28a31 Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Fri, 16 Sep 2022 15:32:57 +0000 Subject: [PATCH] GP-2536 Corrected ARM addrmode3 bitpatterns --- .../data/languages/ARMTHUMBinstructions.sinc | 4 +-- .../ARM/data/languages/ARMinstructions.sinc | 30 +++++++++---------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc b/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc index f646ab483d..cb4bf10544 100644 --- a/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc +++ b/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc @@ -2276,14 +2276,14 @@ define pcodeop ExclusiveAccess; Rt1215 = zext(val); } -:ldrsb^ItCond".w" Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf99; Rt1215) & RnIndirect12 +:ldrsb^ItCond^".w" Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf99; Rt1215) & RnIndirect12 { build ItCond; tmp:1 = *RnIndirect12; Rt1215 = sext(tmp); } -:ldrsb^ItCond".w" Rt1215,RnIndirectPUW is TMode=1 & ItCond & (op4=0xf91; Rt1215 & thc1111=1) & $(RN_INDIRECT_PUW) +:ldrsb^ItCond^".w" Rt1215,RnIndirectPUW is TMode=1 & ItCond & (op4=0xf91; Rt1215 & thc1111=1) & $(RN_INDIRECT_PUW) { build ItCond; build RnIndirectPUW; diff --git a/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc b/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc index a190525137..99d2e40be1 100644 --- a/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc +++ b/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc @@ -965,80 +965,80 @@ addrmode2: [rn],-addr2shift is I25=1 & P24=0 & U23=0 & W21=1 & rn & addr2shift { # it returns a varnode containing the address ########################### -addrmode3: [reloff] is P24=1 & U23=1 & c2122=2 & c1619=15 & immedH & c0707=1 & c0404=1 & immedL +addrmode3: [reloff] is P24=1 & U23=1 & c2122=2 & c1619=15 & immedH & immedL [ reloff=inst_start+8+((immedH<<4) | immedL);] { export *:4 reloff; } -addrmode3: [reloff] is P24=1 & U23=0 & c2122=2 & c1619=15 & immedH & c0707=1 & c0404=1 & immedL +addrmode3: [reloff] is P24=1 & U23=0 & c2122=2 & c1619=15 & immedH & immedL [ reloff=inst_start+8-((immedH<<4) | immedL);] { export *:4 reloff; } -addrmode3: [rn,"#"^off8] is P24=1 & U23=1 & c2122=2 & rn & immedH & c0707=1 & c0404=1 & immedL +addrmode3: [rn,"#"^off8] is P24=1 & U23=1 & c2122=2 & rn & immedH & immedL [ off8=(immedH<<4)|immedL;] { local tmp = rn + off8; export tmp; } -addrmode3: [rn,"#"^noff8] is P24=1 & U23=0 & c2122=2 & rn & immedH & c0707=1 & c0404=1 & immedL +addrmode3: [rn,"#"^noff8] is P24=1 & U23=0 & c2122=2 & rn & immedH & immedL [ noff8=-((immedH<<4)|immedL);] { local tmp = rn + noff8; export tmp; } -addrmode3: [rn,rm] is P24=1 & U23=1 & c2122=0 & rn & c0811=0 & c0707=1 & c0404=1 & rm +addrmode3: [rn,rm] is P24=1 & U23=1 & c2122=0 & rn & c0811=0 & rm { local tmp = rn + rm; export tmp; } -addrmode3: [rn,-rm] is P24=1 & U23=0 & c2122=0 & rn & c0811=0 & c0707=1 & c0404=1 & rm +addrmode3: [rn,-rm] is P24=1 & U23=0 & c2122=0 & rn & c0811=0 & rm { local tmp = rn - rm; export tmp; } -addrmode3: [rn,"#"^off8]! is P24=1 & U23=1 & c2122=3 & rn & immedH & c0707=1 & c0404=1 & immedL +addrmode3: [rn,"#"^off8]! is P24=1 & U23=1 & c2122=3 & rn & immedH & immedL [ off8=(immedH<<4)|immedL;] { rn=rn + off8; export rn; } -addrmode3: [rn,"#"^noff8]! is P24=1 & U23=0 & c2122=3 & rn & immedH & c0707=1 & c0404=1 & immedL +addrmode3: [rn,"#"^noff8]! is P24=1 & U23=0 & c2122=3 & rn & immedH & immedL [ noff8=-((immedH<<4)|immedL);] { rn=rn + noff8; export rn; } -addrmode3: [rn,rm]! is P24=1 & U23=1 & c2122=1 & rn & c0811=0 & c0707=1 & c0404=1 & rm +addrmode3: [rn,rm]! is P24=1 & U23=1 & c2122=1 & rn & c0811=0 & rm { rn = rn+rm; export rn; } -addrmode3: [rn,-rm]! is P24=1 & U23=0 & c2122=1 & rn & c0811=0 & c0707=1 & c0404=1 & rm +addrmode3: [rn,-rm]! is P24=1 & U23=0 & c2122=1 & rn & c0811=0 & rm { rn = rn - rm; export rn; } -addrmode3: [rn],"#"^off8 is P24=0 & U23=1 & c2122=2 & rn & immedH & c0707=1 & c0404=1 & immedL +addrmode3: [rn],"#"^off8 is P24=0 & U23=1 & c2222=1 & rn & immedH & immedL [ off8=(immedH<<4)|immedL;] { local tmp=rn; rn=rn + off8; export tmp; } -addrmode3: [rn],"#"^noff8 is P24=0 & U23=0 & c2122=2 & rn & immedH & c0707=1 & c0404=1 & immedL +addrmode3: [rn],"#"^noff8 is P24=0 & U23=0 & c2222=1 & rn & immedH & immedL [ noff8=-((immedH<<4)|immedL);] { local tmp=rn; rn=rn + noff8; export tmp; } -addrmode3: [rn],rm is P24=0 & U23=1 & c2122=0 & rn & c0811=0 & c0707=1 & c0404=1 & rm +addrmode3: [rn],rm is P24=0 & U23=1 & c2222=0 & rn & c0811=0 & rm { local tmp=rn; rn=rn+rm; export tmp; } -addrmode3: [rn],-rm is P24=0 & U23=0 & c2122=0 & rn & c0811=0 & c0707=1 & c0404=1 & rm +addrmode3: [rn],-rm is P24=0 & U23=0 & c2222=0 & rn & c0811=0 & rm { local tmp=rn; rn=rn-rm; export tmp; } @@ -5450,7 +5450,7 @@ armEndianNess: "BE" is c0031=0xf1010200 { export 1:1; } *addrmode2 = tmpRd:1; } -:strbt^COND Rd,addrmode2 is $(AMODE) & COND & c2627=1 &P24=0 & B22=1 & W21=1 & L20=0 & Rd & (I25=0 | (I25=1 & c0404=0)) & addrmode2 +:strbt^COND Rd,addrmode2 is $(AMODE) & COND & c2627=1 & P24=0 & B22=1 & W21=1 & L20=0 & Rd & (I25=0 | (I25=1 & c0404=0)) & addrmode2 { build COND; build addrmode2;