From 16c7c29d5438b3a5fc6789f0f5af7d86f73bac06 Mon Sep 17 00:00:00 2001 From: emteere <47253321+emteere@users.noreply.github.com> Date: Thu, 10 Feb 2022 17:35:42 +0000 Subject: [PATCH 1/2] GP-1739 Add up to 16 byte return values for AARCH64 --- Ghidra/Processors/AARCH64/data/languages/AARCH64.cspec | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Ghidra/Processors/AARCH64/data/languages/AARCH64.cspec b/Ghidra/Processors/AARCH64/data/languages/AARCH64.cspec index 06aed80b94..13e4c67c35 100644 --- a/Ghidra/Processors/AARCH64/data/languages/AARCH64.cspec +++ b/Ghidra/Processors/AARCH64/data/languages/AARCH64.cspec @@ -127,6 +127,9 @@ + + + From 0d242f52ad3811b2eea228aeb8578adc73b53683 Mon Sep 17 00:00:00 2001 From: emteere <47253321+emteere@users.noreply.github.com> Date: Tue, 22 Feb 2022 15:56:14 +0000 Subject: [PATCH 2/2] GP-1752_emteere Detecting PIC conditional branch to next instruction as a goto vice a call --- .../Processors/ARM/data/languages/ARMinstructions.sinc | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc b/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc index e46a5be795..b7f459f4c7 100644 --- a/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc +++ b/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc @@ -2257,6 +2257,15 @@ ArmPCRelImmed12: reloff is U23=0 & immed & rotate goto Addr24; } +# bl used as a PIC instruction to get at current PC in lr +:bl^COND Addr24 is $(AMODE) & COND & c2527=5 & L24=1 & immed24=0xffffff & Addr24 +{ + build COND; + build Addr24; + lr = inst_next; + goto Addr24; +} + :bl Addr24 is $(AMODE) & cond=14 & c2527=5 & L24=1 & Addr24 { lr = inst_next;