From fda8cf924e482731a0bb12a5a91b8d6f9314715f Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Thu, 6 Feb 2020 07:40:26 -0500 Subject: [PATCH] GT-3529: Corrected cr16c.sinc abs20 subconstructor address mapping --- Ghidra/Processors/CR16/data/languages/CR16C.sinc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Ghidra/Processors/CR16/data/languages/CR16C.sinc b/Ghidra/Processors/CR16/data/languages/CR16C.sinc index a1e6aa21f9..f70a45749d 100644 --- a/Ghidra/Processors/CR16/data/languages/CR16C.sinc +++ b/Ghidra/Processors/CR16/data/languages/CR16C.sinc @@ -287,12 +287,12 @@ cnt3b: "$"tmp is b0_2 [ tmp = b0_2 + 1; ] { export *[const]:1 tmp; # If (abs20 > 0xEFFFF) the resulting address is logically ORed with 0xF00000 # i.e. addresses from 1M-64k to 1M are re-mapped by the core to 16M-64k to 16M. +abs20: tmp is n5=0xf & dw_w2 [ tmp = 0xff0000 | dw_w2; ] { + export *[const]:3 tmp; +} + abs20: tmp is n5 & dw_w2 [ tmp = (n5 << 16) + dw_w2; ] { - tmp2:3 = tmp; - if (tmp2 <= 0xefffff) goto ; - tmp2 = tmp2 | 0xf00000; - - export *[const]:3 tmp2; + export *[const]:3 tmp; } abs24: "*"tmp is n5 & n7 & b0_15