mirror/ghidra
1
0
Fork 0
mirror of https://github.com/NationalSecurityAgency/ghidra.git synced 2026-10-22 18:22:23 -09:00
Code Issues Packages Projects Releases Wiki Activity
3,258 Commits 3 Branches 60 Tags
ca1047cd970f3ef09c3aec6dc756fe0a830e7607
Commit Graph

66 Commits

Author SHA1 Message Date
ghidra1
39ef49d1d1 Merge remote-tracking branch 'origin/GP-49_external_disassembly_upgrade--SQUASHED' into Ghidra_9.2 2020-09-29 10:23:16 -04:00
ghidra1
356ea446c7 GP-49 external disassembly field can now switch based upon context (implemented for ARM/Thumb) 2020-09-29 10:22:46 -04:00
ghidra1
558844aaa9 Merge remote-tracking branch 'origin/GT-3643_ghidorahrex_arm_ldrt_bitpattern' 2020-09-22 10:26:00 -04:00
emteere
a7d5e983b7 GT_3394_emteere minor fix for Arm v6 with VFPv2 but not VFPv3. Fix 
subconstructor matching for reg d0
 2020-09-21 21:20:00 -04:00
emteere
9e0c6b9372 GT-3394 Fixing UDF instruction flow 2020-09-17 21:28:41 -04:00
ghidorahrex
3778831902 GT-3394: Created ARM v6 pspec 2020-09-17 21:28:40 -04:00
ghidorahrex
ea6cfcd08c Revert "GT-3394: Fixed register definitions in VLDM/VSTM instructions" 
This reverts commit 0858a9140d0f7c9c7e1f2e412d3c19a6087e5d1e.
 2020-09-17 21:28:39 -04:00
ghidorahrex
cfcfff0afc GT-3394: Fixed register definitions in VLDM/VSTM instructions 2020-09-17 21:25:50 -04:00
ghidorahrex
389387c9d3 GT-3394: Fixed ARM instruction issues 
- Added missing THUMB instruction variants
- Corrected VFPv2/VFPv3/SIMD errors
 2020-09-17 21:21:43 -04:00
ghidra1
02e017f507 Merge remote-tracking branch 'origin/GT-2567_ARM_neon_vstm' 2020-09-17 12:00:45 -04:00
emteere
ad96867b74 GT-2567 fixed vldm*/vstm* semantics 2020-09-16 21:30:12 -04:00
ghidra1
f3b4e6de16 GP-164 Added ELF ARM relocation R_ARM_PREL31 and corrected issue with 
R_ARM_ABS32 relocation.
Fixes #2261, Fixes #2276
 2020-09-16 12:48:40 -04:00
ghidra1
da92b68bcd GP-164 Corrected ELF ARM R_ARM_REL32 (type 3) relocation processing 2020-09-15 20:12:41 -04:00
emteere
82f58c22d2 GT-2567 adding missing neon instructions, correcting shift calculation 
of several neon instructions, upping version number due to
sub-constructor split
 2020-09-14 21:35:34 -04:00
emteere
93473d3282 GT-2567 fixed long standing issue with pointer source register 2020-09-14 20:50:39 -04:00
ghidorahrex
169b23b1e0 GT-2567: implemented vstmia/db and vldmia/db ARM neon instructions 2020-09-14 20:50:38 -04:00
ghidra1
04594f770b Merge remote-tracking branch 'origin/GP-68_James_arm_thumb_fixes' 2020-09-11 19:45:35 -04:00
James
5e40f00351 arm fixes 2020-09-01 21:21:29 -04:00
James
31a377b6d0 fixing ARMTHUMBinstructions.sinc 2020-08-25 09:42:47 -04:00
ghidorahrex
16e98bfea6 GT-3643: Corrected ARM ldrt instruction bit-pattern 2020-07-16 10:55:58 -04:00
WorksButNotTested
b3b7bab4ca Added secondary selectors to ARM opinion file for correctly identifying 
ARMBE8 binaries
 2020-07-14 16:12:02 -04:00
ghidorahrex
cde035d8b2 Merge remote-tracking branch 
'origin/GT-3641_ghidorahrex_PR-2005_simeonpilgrim_arm_STREX_fix'

Fixes #2005, fixes #2010
 2020-07-14 14:27:43 -04:00
WorksButNotTested
556710d261 #1494: Fix incorrect handling of relocations for ARM BE8 binaries 2020-07-13 18:35:22 -04:00
ghidorahrex
c5a31bb129 Merge remote-tracking branch 
'origin/GP-23_ghidorahrex_PR-1802_vvasseur_fix_teq_in_arm_thumb'

Fixes #1802
 2020-06-30 15:07:29 -04:00
Simeon Pilgrim
632a768cf3 copy hasExclusiveAccess pattern into ARM STREX instruction to be the same as the THUMB and STREXn instructions 2020-06-19 09:38:04 +12:00
emteere
44037991d2 GT-3393_ghidorahrex_ARM_missing_spaces minor format issue in ARMThumb 
from GT-3393 changes
 2020-05-11 17:08:54 -04:00
Valentin Vasseur
eed394f8a3 ARM: Fix sleigh description of teq in Thumb mode 
teq performs a bitwise EXCLUSIVE or, not an inclusive or. (See section
A8.8.238 of the ARMv7 reference manual.)
 2020-04-26 01:52:01 +02:00
ghidorahrex
0ec0e703b3 Merge remote-tracking branch 'origin/GT-3393_ghidorahrex_ARM_missing_spaces' 2020-02-24 13:58:56 -05:00
ghidorahrex
2d69b43bd1 GT-3393: Fixed formatting for Ldlist in arm thumb 2020-02-12 07:36:18 -05:00
Benjamin Levy
74fae2f644 Merge branch 'master' of 
https://github.com/NationalSecurityAgency/ghidra into spell
 2020-01-29 11:37:23 -05:00
ghidorahrex
498abf1a31 Merge remote-tracking branch 'origin/GT-3420_ghidorahrex_arm_thumb_rsb' 
Fixes #1365
 2020-01-27 07:20:35 -05:00
ghidorahrex
5ff5426ffc Merge remote-tracking branch 'origin/GT-3408_ghidorahrex_arm_thumb_it_al_condition' 2020-01-27 07:17:57 -05:00
Benjamin Levy
a5efecea84 Fix spelling errors 2020-01-26 22:39:18 -05:00
mumbel
dce6e9f6a8 Cleaning up warnings and errors, mostly looking for: 
temporary is written but not read in constructor
 2020-01-22 19:51:45 -06:00
ghidorahrex
f92528923d GT-3408: Corrected IT conditionals 2019-12-20 11:32:48 -05:00
ghidorahrex
7aa51fb572 GT-3420: Corrected RSB width modifier 2019-12-20 08:45:25 -05:00
ghidorahrex
d47317a9f8 GT-3408: Included support of 'al' for IT instructions, generalized 
support for IT instructions and included the 'nv' condition although it
should never occur.
 2019-12-18 14:41:05 -05:00
ghidra1
8fbdec4eca Merge remote-tracking branch 'origin/patch' 2019-12-18 11:02:47 -05:00
emteere
67d774fa42 GT-3374_emteere several bugs and inneficiencies causing analysis to fail 
for programs with debug info
 2019-12-16 16:52:15 -05:00
ghidorahrex
d30ba7c9b1 GT-3393 ARM parameter list spaces 
Corrected ARM subconstructors for spacing around register paramter
lists.
 2019-12-13 09:35:08 -05:00
Ryan Kurtz
30140d88c7 Merge remote-tracking branch 'origin/GT-3368_ghidorahrex_PR-1277_lioncash_mul' 2019-12-04 13:58:08 -05:00
Lioncash
9a5769979c ARM: Handle disassembly of VNMLA for F16/F32/F64 
These Sleigh constructors were acting as constructors for VNMLS, however
the constructors actually describe the bit encoding for VNMLA, which can
result in incorrect disassembly meaning.

This corrects this so that VNMLA instructions are properly disassembled
and also don't show up as generic CDP instructions.
 2019-11-24 05:25:15 -05:00
Lioncash
644f3c3449 ARM: Handle disassembly of conditional VNMLS for F32/F64 
Similarly with VNMUL, VNMLS is also able to execute with a condition
code for single-precision and double-precision floating point variants.

Like with the previous change, we can also amend the Sleigh constructor
so that it decodes properly (the condition code for a predictable
instruction is 0xE, not 0xF).

This fixes VNMLS instructions disassembling as generic CDP instructions,
making disassembly clearer.
 2019-11-24 03:01:22 -05:00
Lioncash
9670b81458 ARM: Handle disassembly of conditional VNMUL for F32/F64 
The single-precision and double-precision variants of VNMUL support
condition codes on them in ARM mode. We can amend the Sleigh
constructors to reflect this.

We can also amend the half-precision variant to reflect that the
condition code should be 0xE in terms of value. The ARMv8 architecture
reference manual states (at F6.1.148) that if a half-precision
instruction is present and does not have a condition code of 1110, then
the behavior is considered CONSTRAINED UNPREDICTABLE.

This fixes VNMUL instructions disassembling as generic CDP instructions,
making the disassembly much clearer.
 2019-11-24 03:00:48 -05:00
Lioncash
520f1c47d9 ARM: Correct Sleigh constructor for VCVT{R}<c>.S32.F32 
Bits 23-27 are defined with a bit encoding of 0b11101, not 0b11011 (See
section F6.1.60 within the ARMv8 reference manual or section A8.8.306
within the ARMv7 reference manual).

This makes conversions from floating-point registers to signed values
disassemble/decompile more properly and not as generic CDP instructions,
making decompilation a little more informative.
 2019-11-24 02:23:06 -05:00
Ryan Kurtz
e3b8a782ba Merge remote-tracking branch 'origin/GT-3239_ryanmkurtz_PR-916_redfast00_privilaged_typo_fix' 2019-10-16 08:28:39 -04:00
ghidra1
349ef0fad2 GT-3149 Corrected bitfield packing for ARM/AARCH64 for Windows PE. 
Imposed default Thumb context setting for PE and MSCoff ARM32 imports
with addition of v8T ARM variant.  Corrected ARM pattern alignment
issues.  Corrected DBViewer long value rendering.
 2019-09-13 14:06:56 -04:00
ghizard
0ba928a33f GT-2880 changes pre-certification 2019-09-05 18:35:33 -04:00
ghizard
525f0057c8 GT-2880 Adding more unaffected/killed 2019-09-05 18:27:18 -04:00
ghizard
651971c493 GT-2880 More changes to ARM processor files 2019-09-05 18:27:17 -04:00