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56 Commits

Author SHA1 Message Date
Ryan Kurtz
9cf60faef0 Merge remote-tracking branch 
'origin/GP-3155_caheckman_PR-2810_Pokechu22_countleadingzeros'
(Closes #2810)
 2023-03-24 14:29:30 -04:00
caheckman
945d91fc93 GP-3155 Regenerating parsers, documentation. LZCOUNT tests. 2023-03-24 13:06:45 -04:00
Ryan Kurtz
82ba4831b6 Merge remote-tracking branch 
'origin/GP-3187_ghidorahrex_PR-5093_rbran_m68k_export_0_fix'
(Closes #5093, Closes #5094)
 2023-03-16 12:11:31 -04:00
Ryan Kurtz
738e662e82 Merge remote-tracking branch 
'origin/GP-2013_ghidorahrex_PR-4217_agatti_68000-shifts' (Closes #4217)
 2023-03-14 09:57:26 -04:00
Rubens Brandão
30fc469235 Sleigh 68000 CPUs exports a length 0 value 
A value with length 0 should be impossible, but also, all constructors from a table should export a value with the same length.
 2023-03-13 10:42:57 -03:00
ghidorahrex
c4cf19ebfc GP-2013 Fixed additional issues with shifts and rotates 2023-03-03 17:14:41 +00:00
Pokechu22
14880b53c4 Create and use LZCOUNT Pcode op 2023-03-02 18:30:04 -08:00
ghidorahrex
1848c1a6f4 GP-2197: Fixed cspec metatype pentry ordering. 2022-12-05 15:29:40 +00:00
ghidorahrex
0e1e607317 GP-2197: Corrected COLDFIRE scalefactor consistency 2022-12-05 15:29:39 +00:00
ghidorahrex
f5b6973ea8 GP-2197 code review fixes 2022-12-05 15:29:38 +00:00
ghidorahrex
362bb9dfa3 GP-2197: Added additional EMACS instructions to coldfire 2022-12-05 15:29:37 +00:00
emteere
947bf43cb5 GP-2197 Adding initial EMAC instructions and .cspec changes for 
D0,A0,D1,A1
 2022-12-05 15:25:31 +00:00
emteere
ca5a6204c3 GP-2391 added evaluation of return address, allow thunking addresses to externals. Added new arem thunk pattern. 2022-10-11 18:25:09 -04:00
Ryan Kurtz
4ed60c8790 Merge remote-tracking branch 'origin/GP-2195_ghidorahrex_PR-4270_agatti_68000-coldfire-bitops' 2022-10-05 09:44:04 -04:00
Ryan Kurtz
79947c37f6 Merge remote-tracking branch 
'origin/GP-2014_ghidorahrex_PR-4223_agatti_68000-pack-unpk'
(Closes #4223)
 2022-09-16 13:31:35 -04:00
ghidorahrex
66c727bb38 GP-2014: review comments 2022-07-22 19:31:09 +00:00
Alessandro Gatti
01c24684a0 Switch back to pcode implementation. 2022-07-05 23:30:18 +02:00
Alessandro Gatti
b44355f367 Use pcodeops for bitrev and byterev. 2022-06-08 20:36:33 +02:00
ghidorahrex
f1be7a7e4e Modified coldfire TPF instructions to jumps 2022-06-07 13:37:26 +00:00
Alessandro Gatti
4ebeee777f Implement ColdFire's BITREV, BYTEREV and FF1. 2022-05-22 06:33:29 +02:00
Alessandro Gatti
43698e4a3a Correct operands order. 
As per discussion on #4189, Tx[bw] and Ty[bw] need to be swapped.
 2022-05-04 07:53:47 +02:00
Alessandro Gatti
63e615e793 Implement 68000 PACK and UNPK opcodes. 2022-05-03 04:19:03 +02:00
Alessandro Gatti
1c6b0140bc Update ASL/ASR/LSL/LSR/ROL/ROR/ROXL/ROXR behavior. 2022-05-02 04:12:49 +02:00
Jeff Muizelaar
f736bdc43f m68k: Fix fopmode for fmod 
See fc7a6fc602/m68kdasm.c (L1772)
and 2e185fb65e/target/m68k/translate.c (L5255)
 2022-04-05 11:28:20 -04:00
ghidra1
a6f7392736 Merge remote-tracking branch 
'origin/GP-1644_ghidorahrex_m68000_addx_fix--SQUASHED' (Closes #3818)
 2022-01-10 21:07:33 -05:00
ghidorahrex
51d84f8bc0 GP-1644: fixed semantics of 68000 addx flags 2022-01-07 12:54:24 -05:00
Alessandro Gatti
b6942c875c Implement CHK, CHK2, and CMP2 for 68k. 2021-11-09 22:25:23 +01:00
Ryan Kurtz
3a0ae8ee39 GP-849: Gradle 7 support 2021-05-12 13:45:16 -04:00
ghidra1
d377d90e14 Merge remote-tracking branch 'origin/patch' 
Conflicts:
	Ghidra/Features/GraphServices/certification.manifest
 2021-03-17 19:38:50 -04:00
ghidra1
162f203395 Updated certification headers 2021-03-17 18:22:50 -04:00
ghidra1
399dd9484f Merge remote-tracking branch 
'origin/GP-758_ghidorahrex_PR-2651_miek_68000_byte_SP' (Closes #1709,
Closes #2651)
 2021-03-10 12:58:12 -05:00
Mike Walters
4904a0e7b5 68000: fix disassembly of fmove with dynamic k-factor 2021-02-13 02:20:52 +00:00
Mike Walters
ad1c5d7819 68000: fix SP postincrement/predecrement with byte operands 
When the address register is the stack pointer and the operand size is
byte, the address is incremented/decremented by two to keep the stack
pointer aligned to a word boundary.
[M68000 Family Programmer’s Reference Manual; 2.2.4 & 2.2.5]

fixes #1709
 2021-01-15 19:24:45 +00:00
ghidra1
5890b88f56 Certification update 2020-12-30 09:44:29 -05:00
ghidra1
1c70e034b3 Merge branch 'GP-556_ghidra1_PR-1610_bstreiff_DWARF_m68k_SVR4' 2020-12-30 09:39:24 -05:00
Brandon Streiff
5d57628b7f 68000: add m68k/SVR4 DWARF register mappings 2020-03-08 11:18:12 -05:00
Christian Zietz
a25e48399e 68000: Rework fix for MOVE USP,x and MOVE x,USP 2020-03-04 16:51:19 +00:00
Christian Zietz
1cb3128623 Fix MOVE USP,x and MOVE x,USP opcodes 2020-03-03 20:11:08 +00:00
Benjamin Levy
74fae2f644 Merge branch 'master' of 
https://github.com/NationalSecurityAgency/ghidra into spell
 2020-01-29 11:37:23 -05:00
ghidorahrex
4c81e6837f Merge remote-tracking branch 'origin/GT-3429_ghidorahrex_m68000_move_overwrite' 2020-01-27 07:17:15 -05:00
Benjamin Levy
a5efecea84 Fix spelling errors 2020-01-26 22:39:18 -05:00
ghidorahrex
c5f2fa286c GT-3429: Corrected issue with m68000 move instruction overwriting 
variables.
 2019-12-30 10:09:03 -05:00
Vladimir Kononovich
876ee2881e Fixed M68000 ROXR and ROXL 2019-12-07 21:12:33 +03:00
ghidorahrex
42abc96b89 GT-3137: 68000 corrected shift CF/XF flags for zero-shift operations. 2019-09-16 10:20:21 -04:00
ghidorahrex
72e0d8d879 GT-3137: corrected updating xf in lsl and lsr instructions. 2019-09-09 13:06:15 -04:00
ghidorahrex
59aa00dfb7 Corrected issue with coldfire mov3q immediate -1 representation 2019-08-13 08:06:16 -04:00
emteere
2221510f90 emteere Minor changes for sleigh editor syntax errors 2019-08-02 12:04:47 -04:00
Philip Pemberton
a8f27f6484 TRAPV/TRAPcc don't use the TRAP7 vector, they use the TRAPV vector 2019-07-18 08:54:54 -04:00
Philip Pemberton
919762c1cc Prefix trap(), make parameter the trap number 
* Add "__m68k_" prefix to `trap()` to indicate that it's a CPU
    intrinsic
  * `__m68k_trap()` now takes the trap number as a parameter, which
    lines up better with established 68k norms (`TRAP #n` is the
    assembly syntax)
 2019-07-18 08:54:28 -04:00
Philip Pemberton
f127c3c0fc M68000: set alignment, full SR decode, TRAPV as address 
* Specify instruction alignment to be 2 bytes
  * Fully decode the status register (add trace and supervisor flags and interrupt priority)
  * Decode TRAPs into the vector addresses to make code easier to follow
 2019-07-18 08:54:09 -04:00