mirror/ghidra
1
0
Fork 0
mirror of https://github.com/NationalSecurityAgency/ghidra.git synced 2026-09-28 17:11:11 -09:00
Code Issues Packages Projects Releases Wiki Activity
Files
master
ghidra/Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.sinc
ghidra1 dbec68725c GP-7267 Minor revision to Hexagon pcode
2026-09-10 19:02:19 -04:00

6890 lines
342 KiB
Plaintext
Raw Permalink Blame History

# Qualcomm Hexagon HVX Instruction Set
# NOTES:
# - HVX implementation has been updated through V81
# - HVX hardware supports either 64-byte or 128-byte vector lengths. See hexagon.slaspec for
# default length of 128-bytes.
# UNDERSTANDING / ASSUMPTIONS:
# - The term "forwarding" indicates that a vector update immediately modifies a tmp shadow
# register which may be read via a subsequent .new access within the same execute packet.
# - The vector .cur update is taken to mean a non-forwarding register update that is
# committed to the register file at the end of the execute packet and not available for
# reading via a .new access.
# - All conditional instructions are treated as non-forwarding.
# - Unless specified as a .cur update, all unconditional vector register updates are treated
# as "forwarding" and commit to register file at the end of the execute packet.
#
# Paired-Vector Operands (e.g., V0V1 )
#
# Vector pair unconditional write (0,4) (new vector store forwarded and committed)
# TODO: When vector swap mode is used (vddM=1) should retained nreg be affected?
# NOTE: vdd4_ has normal order and is not swapped until commit based upon vddM
Vdd5: vdd4 is cond=0 & vdd4 & vdd4_ & vddM=0 & SetVNRegVd5 {
export vdd4_; # must be updated unconditionally
<<COMMIT>>
vdd4 = vdd4_;
}
Vdd5: vdd4R is cond=0 & vdd4R & vdd4h & vdd4l & vdd4_ & vddM=1 & SetVNRegVd5 {
export vdd4_; # must be updated unconditionally
<<COMMIT>>
vdd4l = vdd4_($(HVX_VECTOR_SIZE));
vdd4h = vdd4_:$(HVX_VECTOR_SIZE);
}
# Vector pair temporary write (0,4) (new vector store forwarded, not committed)
Vdd5tmp: vdd4^".tmp" is vdd4 & vdd4_ & vddM=0 & SetVNRegVd5 {
export vdd4_; # must be updated unconditionally
}
Vdd5tmp: vdd4R^".tmp" is vdd4R & vdd4_ & vddM=1 & SetVNRegVd5 {
export vdd4_; # must be updated unconditionally
}
# destination vector pair (0,4) - unconditional write-only use - see Vdd5 (used for lane naming only)
VddW_0004: Vdd5^".w" is Vdd5 { export Vdd5; }
VddH_0004: Vdd5^".h" is Vdd5 { export Vdd5; }
VddB_0004: Vdd5^".b" is Vdd5 { export Vdd5; }
VddUW_0004: Vdd5^".uw" is Vdd5 { export Vdd5; }
VddUH_0004: Vdd5^".uh" is Vdd5 { export Vdd5; }
VddUB_0004: Vdd5^".ub" is Vdd5 { export Vdd5; }
VddQF32_0004: Vdd5^".qf32" is Vdd5 { export Vdd5; }
# source vector pair (0,4) - read-only use
Vss_0004:vss4 is vss4 & vssM=0 {
tmp:$(HVX_VECTOR_PAIR_SIZE) = vss4;
export tmp;
}
Vss_0004:vss4R is vss4 & vss4R & vssM=1 {
local tmp:$(HVX_VECTOR_PAIR_SIZE) = 0;
tmp[0,$(HVX_VECTOR_SIZE_BITS)] = vss4[$(HVX_VECTOR_SIZE_BITS),$(HVX_VECTOR_SIZE_BITS)];
tmp[$(HVX_VECTOR_SIZE_BITS),$(HVX_VECTOR_SIZE_BITS)] = vss4[0,$(HVX_VECTOR_SIZE_BITS)];
export tmp;
}
# read-only use - see Vuu_0812 (used for lane naming only)
VssW_0004:Vss_0004^".w" is Vss_0004 { export Vss_0004; }
# source vector pair (8,12) - read-only use
Vuu_0812:vuu4 is vuu4 & vuuM=0 {
tmp:$(HVX_VECTOR_PAIR_SIZE) = vuu4;
export tmp;
}
Vuu_0812:vuu4R is vuu4 & vuu4R & vuuM=1 {
local tmp:$(HVX_VECTOR_PAIR_SIZE) = 0;
tmp[0,$(HVX_VECTOR_SIZE_BITS)] = vuu4[$(HVX_VECTOR_SIZE_BITS),$(HVX_VECTOR_SIZE_BITS)];
tmp[$(HVX_VECTOR_SIZE_BITS),$(HVX_VECTOR_SIZE_BITS)] = vuu4[0,$(HVX_VECTOR_SIZE_BITS)];
export tmp;
}
# read-only use - see Vuu_0812 (used for lane naming only)
VuuW_0812:Vuu_0812^".w" is Vuu_0812 { export Vuu_0812; }
VuuH_0812:Vuu_0812^".h" is Vuu_0812 { export Vuu_0812; }
VuuB_0812:Vuu_0812^".b" is Vuu_0812 { export Vuu_0812; }
VuuUW_0812:Vuu_0812^".uw" is Vuu_0812 { export Vuu_0812; }
VuuUH_0812:Vuu_0812^".uh" is Vuu_0812 { export Vuu_0812; }
VuuUB_0812:Vuu_0812^".ub" is Vuu_0812 { export Vuu_0812; }
VuuQF32_0812: Vuu_0812^".qf32" is Vuu_0812 { export Vuu_0812; }
# source vector pair (16,20) - read-only use
Vvv_1620:vvv4 is vvv4 & vvvM=0 {
tmp:$(HVX_VECTOR_PAIR_SIZE) = vvv4;
export tmp;
}
Vvv_1620:vvv4R is vvv4 & vvv4R & vvvM=1 {
local tmp:$(HVX_VECTOR_PAIR_SIZE) = 0;
tmp[0,$(HVX_VECTOR_SIZE_BITS)] = vvv4[$(HVX_VECTOR_SIZE_BITS),$(HVX_VECTOR_SIZE_BITS)];
tmp[$(HVX_VECTOR_SIZE_BITS),$(HVX_VECTOR_SIZE_BITS)] = vvv4[0,$(HVX_VECTOR_SIZE_BITS)];
export tmp;
}
# read-only use - see Vvv_1620 (used for lane naming only)
VvvW_1620:Vvv_1620^".w" is Vvv_1620 { export Vvv_1620; }
VvvH_1620:Vvv_1620^".h" is Vvv_1620 { export Vvv_1620; }
VvvB_1620:Vvv_1620^".b" is Vvv_1620 { export Vvv_1620; }
VvvUW_1620:Vvv_1620^".uw" is Vvv_1620 { export Vvv_1620; }
VvvUH_1620:Vvv_1620^".uh" is Vvv_1620 { export Vvv_1620; }
VvvUB_1620:Vvv_1620^".ub" is Vvv_1620 { export Vvv_1620; }
#
# Single Vector Operands (e.g., V0)
#
# Vector unconditional write (new vector store forwarded and committed)
Vd5: vd5 is cond=0 & vd5 & vd5_ & SetVNRegVd5 {
export vd5_; # must be updated unconditionally
<<COMMIT>>
vd5 = vd5_;
}
# Vector .cur unconditional write (not-forwarded, unconditionally committed at end of packet)
Vd5cur: vd5^".cur" is cond=0 & vd5 & vd5_{
export vd5_; # must be updated unconditionally
<<COMMIT>>
vd5 = vd5_;
}
# Vector .cur conditional write (not-forwarded, conditionally committed at end of packet)
Vd5cur: vd5^".cur" is cond=1 & vd5 & vd5_ {
export vd5_;
<<COMMIT_COND>>
if (ConditionReg == 0) goto <nocommit>;
vd5 = vd5_;
<nocommit>
}
# Vector temporary write (new vector store forwarded, not committed)
# .tmp vector is also established for use by vhist... and vwhist... instructions
Vd5tmp: vd5^".tmp" is vd5 & vd5_ & SetVNRegVd5 [ tmpvreg=vd5; ] {
export vd5_;
}
# destination vector - unconditional write-only use - see Vd5 (used for lane naming only)
VdW_0004: Vd5^".w" is Vd5 { export Vd5; }
VdH_0004: Vd5^".h" is Vd5 { export Vd5; }
VdB_0004: Vd5^".b" is Vd5 { export Vd5; }
VdUW_0004: Vd5^".uw" is Vd5 { export Vd5; }
VdUH_0004: Vd5^".uh" is Vd5 { export Vd5; }
VdUB_0004: Vd5^".ub" is Vd5 { export Vd5; }
VdHF_0004: Vd5^".hf" is Vd5 { export Vd5; }
VdSF_0004: Vd5^".sf" is Vd5 { export Vd5; }
VdQF16_0004: Vd5^".qf16" is Vd5 { export Vd5; }
VdQF32_0004: Vd5^".qf32" is Vd5 { export Vd5; }
# source vector (0,4) - read-only use
Vs_0004: vs5 is vs5 {
tmp:$(HVX_VECTOR_SIZE) = vs5;
export tmp;
}
# source vector - read-only use - see Vs_0004 (used for lane naming only)
VsW_0004:Vs_0004^".w" is Vs_0004 { export Vs_0004; }
VsH_0004:Vs_0004^".h" is Vs_0004 { export Vs_0004; }
VsB_0004:Vs_0004^".b" is Vs_0004 { export Vs_0004; }
# source vector (8,12) - read-only use
Vu_0812: vu5 is vu5 {
tmp:$(HVX_VECTOR_SIZE) = vu5;
export tmp;
}
# source vector - read-only use - see Vu_0812 (used for lane naming only)
VuW_0812: Vu_0812^".w" is Vu_0812 { export Vu_0812; }
VuH_0812: Vu_0812^".h" is Vu_0812 { export Vu_0812; }
VuB_0812: Vu_0812^".b" is Vu_0812 { export Vu_0812; }
VuUW_0812: Vu_0812^".uw" is Vu_0812 { export Vu_0812; }
VuUH_0812: Vu_0812^".uh" is Vu_0812 { export Vu_0812; }
VuUB_0812: Vu_0812^".ub" is Vu_0812 { export Vu_0812; }
VuSF_0812: Vu_0812^".sf" is Vu_0812 { export Vu_0812; }
VuHF_0812: Vu_0812^".hf" is Vu_0812 { export Vu_0812; }
VuQF16_0812: Vu_0812^".qf16" is Vu_0812 { export Vu_0812; }
VuQF32_0812: Vu_0812^".qf32" is Vu_0812 { export Vu_0812; }
# source vector (16,20) - read-only use
Vv_1620: vv5 is vv5 {
tmp:$(HVX_VECTOR_SIZE) = vv5;
export tmp;
}
# source vector - read-only use - see Vv_1620 (used for lane naming only)
VvW_1620: Vv_1620^".w" is Vv_1620 { export Vv_1620; }
VvH_1620: Vv_1620^".h" is Vv_1620 { export Vv_1620; }
VvB_1620: Vv_1620^".b" is Vv_1620 { export Vv_1620; }
VvUH_1620: Vv_1620^".uh" is Vv_1620 { export Vv_1620; }
VvUW_1620: Vv_1620^".uw" is Vv_1620 { export Vv_1620; }
VvUB_1620: Vv_1620^".ub" is Vv_1620 { export Vv_1620; }
VvSF_1620: Vv_1620^".sf" is Vv_1620 { export Vv_1620; }
VvHF_1620: Vv_1620^".hf" is Vv_1620 { export Vv_1620; }
VvQF16_1620: Vv_1620^".qf16" is Vv_1620 { export Vv_1620; }
VvQF32_1620: Vv_1620^".qf32" is Vv_1620 { export Vv_1620; }
# source vector (19,23) - read-only use
Vz_1923: vz5 is vz5 {
tmp:$(HVX_VECTOR_SIZE) = vz5;
export tmp;
}
# source vector - read-only use - see Vz_1923 (used for lane naming only)
VzW_1923: Vz_1923^".w" is Vz_1923 { export Vz_1923; }
VzH_1923: Vz_1923^".h" is Vz_1923 { export Vz_1923; }
VzB_1923: Vz_1923^".b" is Vz_1923 { export Vz_1923; }
VzUW_1923: Vz_1923^".uw" is Vz_1923 { export Vz_1923; }
VzUH_1923: Vz_1923^".uh" is Vz_1923 { export Vz_1923; }
# Base address of vector register Vu within the register space - used by vextract
VuBase_0812: vbase is op0812 [ vbase = $(HVX_VECTOR_BASE) + (op0812 * $(HVX_VECTOR_SIZE)); ] {
export *[const]:4 vbase;
}
#
# General register operand w/ lanes
#
# source scalar register pair - read-only use - see rxx5 (used for lane naming only)
RttH_1620: rxx5^".h" is rxx5 { tmp:8 = rxx5; export tmp; }
RttUH_1620: rxx5^".uh" is rxx5 { tmp:8 = rxx5; export tmp; }
# source scalar register - read-only use - see rx5 (used for lane naming only)
RtH_1620: rx5^".h" is rx5 { tmp:4 = rx5; export tmp; }
RtB_1620: rx5^".b" is rx5 { tmp:4 = rx5; export tmp; }
RtUH_1620: rx5^".uh" is rx5 { tmp:4 = rx5; export tmp; }
RtUB_1620: rx5^".ub" is rx5 { tmp:4 = rx5; export tmp; }
#
# Vector Predicate operands
#
# Corresponds to Qd4 in documentation (vector predicate destination Q0..Q3, handles unconditional commit)
Qd2: qv0001 is qv0001 & cond=0 {
tmp:$(HVX_PREDICATE_SIZE) = qv0001;
export tmp;
<<COMMIT>>
qv0001 = tmp;
}
# Vector predicate source qv1112 with invert based on op5
Qv_1112_S05: qv1112 is qv1112 & op5=0 {
tmp:$(HVX_PREDICATE_SIZE) = qv1112;
export tmp;
}
Qv_1112_S05: "!"^qv1112 is qv1112 & op5=1 {
tmp:$(HVX_PREDICATE_SIZE) = ~qv1112;
export tmp;
}
# Vector predicate source qv0809 (inverted)
Qv0809Not: "!"^qv0809 is qv0809 {
tmp:$(HVX_PREDICATE_SIZE) = ~qv0809;
export tmp;
}
# Vector predicate source qv2223 (inverted)
Qv2223Not: "!"^qv2223 is qv2223 {
tmp:$(HVX_PREDICATE_SIZE) = ~qv2223;
export tmp;
}
# Predicate Register Condition (least significant bit only)
# map: Ps_0506 -> PuCond0506_S21
# map: Px_0506 -> pu0506 (read only register use)
VPuCond0506_S21: ".if("pu0506name")" is op21=0 & pu0506 & pu0506name [cond=1;] {
condition:1 = (pu0506 & 1);
<<EXEC_COND>>
ConditionReg = condition;
<<COMMIT_COND>>
ConditionReg = condition;
}
VPuCond0506_S21: ".if(!"pu0506name")" is op21=1 & pu0506 & pu0506name [cond=1;] {
condition:1 = !(pu0506 & 1);
<<EXEC_COND>>
ConditionReg = condition;
<<COMMIT_COND>>
ConditionReg = condition;
}
# Predicate Register Condition (least significant bit only)
# map: Pv_1112 -> PuCond1112_S05
VPuCond1112_S05: ".if("pu1112name")" is op5=0 & pu1112 & pu1112name [cond=1;] {
condition:1 = (pu1112 & 1);
<<EXEC_COND>>
ConditionReg = condition;
<<COMMIT_COND>>
ConditionReg = condition;
}
VPuCond1112_S05: ".if(!"pu1112name")" is op5=1 & pu1112 & pu1112name [cond=1;] {
condition:1 = !(pu1112 & 1);
<<EXEC_COND>>
ConditionReg = condition;
<<COMMIT_COND>>
ConditionReg = condition;
}
# Signed immediate s3
Simm32_0810: "#"^s0810 is s0810 { export *[const]:4 s0810; }
# Signed immediate s4 (split into s13 and i0810)
Simm32_0810_13: "#"^simm is s13 & i0810 [ simm = (s13 << 3) | i0810; ] { export *[const]:4 simm; }
# Vector memory (rx++Mu) load/store vector-sized ram address
# -- 'cond=1' context must be set by conditional instructions!
VAlignMemAddrRxAIMu: "("^rx5^"++"^mu^")" is cond=0 & rx5 & rx5_ & mu {
tmp:4 = rx5 + mu;
ptr:4 = rx5 & ~(0x3F); # align offset
export *[ram]:$(HVX_VECTOR_SIZE) ptr;
<<COMMIT>>
rx5 = tmp;
}
VAlignMemAddrRxAIMu: "("^rx5^"++"^mu^")" is cond=1 & rx5 & rx5_ & mu {
tmp:4 = rx5 + mu;
ptr:4 = rx5 & ~(0x3F); # align offset
export *[ram]:$(HVX_VECTOR_SIZE) ptr;
<<COMMIT_COND>>
if (ConditionReg == 0) goto <nocommit>;
rx5 = tmp;
<nocommit>
}
# Vector memory (rx++Mu) unaligned load/store vector-sized ram address
# -- 'cond=1' context must be set by conditional instructions!
VMemAddrRxAIMu: "("^rx5^"++"^mu^")" is cond=0 & rx5 & rx5_ & mu {
ptr:4 = rx5; # pre-increment address snapshot -- rx5 may be updated before the access is emitted
tmp:4 = rx5 + mu;
export *[ram]:$(HVX_VECTOR_SIZE) ptr;
<<COMMIT>>
rx5 = tmp;
}
VMemAddrRxAIMu: "("^rx5^"++"^mu^")" is cond=1 & rx5 & rx5_ & mu {
ptr:4 = rx5; # pre-increment address snapshot -- rx5 may be updated before the access is emitted
tmp:4 = rx5 + mu;
export *[ram]:$(HVX_VECTOR_SIZE) ptr;
<<COMMIT_COND>>
if (ConditionReg == 0) goto <nocommit>;
rx5 = tmp;
<nocommit>
}
# Vector memory (rx++#s3) load/store vector-sized ram address
# -- 'cond=1' context must be set by conditional instructions!
VAlignMemAddrRxAIS3: "("^rx5^"++"^Simm32_0810^")" is cond=0 & rx5 & rx5_ & Simm32_0810 {
tmp:4 = rx5 + (Simm32_0810 * $(HVX_VECTOR_SIZE) );
ptr:4 = rx5 & ~(0x3F); # align offset
export *[ram]:$(HVX_VECTOR_SIZE) ptr;
<<COMMIT>>
rx5 = tmp;
}
VAlignMemAddrRxAIS3: "("^rx5^"++"^Simm32_0810^")" is cond=1 & rx5 & rx5_ & Simm32_0810 {
tmp:4 = rx5 + (Simm32_0810 * $(HVX_VECTOR_SIZE) );
ptr:4 = rx5 & ~(0x3F); # align offset
export *[ram]:$(HVX_VECTOR_SIZE) ptr;
<<COMMIT_COND>>
if (ConditionReg == 0) goto <nocommit>;
rx5 = tmp;
<nocommit>
}
# Vector memory (rx++#s3) unaligned load/store vector-sized ram address
# -- 'cond=1' context must be set by conditional instructions!
VMemAddrRxAIS3: "("^rx5^"++"^Simm32_0810^")" is cond=0 & rx5 & rx5_ & Simm32_0810 {
ptr:4 = rx5; # pre-increment address snapshot -- rx5 may be updated before the access is emitted
tmp:4 = rx5 + (Simm32_0810 * $(HVX_VECTOR_SIZE) );
export *[ram]:$(HVX_VECTOR_SIZE) ptr;
<<COMMIT>>
rx5 = tmp;
}
VMemAddrRxAIS3: "("^rx5^"++"^Simm32_0810^")" is cond=1 & rx5 & rx5_ & Simm32_0810 {
ptr:4 = rx5; # pre-increment address snapshot -- rx5 may be updated before the access is emitted
tmp:4 = rx5 + (Simm32_0810 * $(HVX_VECTOR_SIZE) );
export *[ram]:$(HVX_VECTOR_SIZE) ptr;
<<COMMIT_COND>>
if (ConditionReg == 0) goto <nocommit>;
rx5 = tmp;
<nocommit>
}
# Vector memory (rx+#s4) load/store vector-sized ram address
VAlignMemAddrRxS4: "("^rx5^"+"^Simm32_0810_13^")" is rx5 & Simm32_0810_13 {
ptr:4 = rx5 + (Simm32_0810_13 * $(HVX_VECTOR_SIZE) );
ptr = ptr & ~(0x3F); # align offset
export *[ram]:$(HVX_VECTOR_SIZE) ptr;
}
VAlignMemAddrRxS4: "("^rx5^")" is rx5 & op0810=0 & op13=0 {
local ptr = rx5 & ~(0x3F); # align offset
export *[ram]:$(HVX_VECTOR_SIZE) ptr;
}
# Vector memory (rx+#s4) unaligned load/store vector-sized ram address
VMemAddrRxS4: "("^rx5^"+"^Simm32_0810_13^")" is rx5 & Simm32_0810_13 {
ptr:4 = rx5 + (Simm32_0810_13 * $(HVX_VECTOR_SIZE) );
export *[ram]:$(HVX_VECTOR_SIZE) ptr;
}
VMemAddrRxS4: "("^rx5^")" is rx5 & op0810=0 & op13=0 {
export *[ram]:$(HVX_VECTOR_SIZE) rx5;
}
# optional nontemporal hint :nt
ntHint22: is op22=0 { }
ntHint22:":nt" is op22=1 { }
#
# HVX Instructions
#
# (v60,1) "vwhist256"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 0 1 0 1 0 0 - - - - -
define pcodeop vwhist256;
:vwhist256 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0911=0x1 & op0508=0x4 & tmpvreg_ & $(END_PACKET) {
build EndPacket;
<<COMMIT>>
vwhist256(tmpvreg_); # TODO: Does not properly convey vector inputs/outputs
}
# (v60,1) vwhist256 -- "vwhist256:sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 0 1 1 1 0 0 - - - - -
define pcodeop vwhist256sat;
:vwhist256^":sat" EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0911=0x1 & op0508=0xc & tmpvreg_ & $(END_PACKET) {
build EndPacket;
<<COMMIT>>
vwhist256sat(tmpvreg_); # TODO: Does not properly convey vector inputs/outputs
}
# (v60,1) "vwhist128"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 1 0 - 1 0 0 - - - - -
define pcodeop vwhist128;
:vwhist128 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0911=0x2 & op0507=0x4 & tmpvreg_ & $(END_PACKET) {
build EndPacket;
<<COMMIT>>
vwhist128(tmpvreg_); # TODO: Does not properly convey vector inputs/outputs
}
# (v60,1) vwhist128 -- "vwhist128(#u1)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 1 1 i 1 0 0 - - - - -
define pcodeop vwhist128u;
:vwhist128 "#"^i8 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0911=0x3 & op0507=0x4 & i8 & tmpvreg_ & $(END_PACKET) {
build EndPacket;
<<COMMIT>>
vwhist128u(tmpvreg_); # TODO: Does not properly convey vector inputs/outputs
}
# (v60,1) vwhist256 -- "vwhist256(Qv4)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 0 1 0 1 0 0 - - - - -
define pcodeop vwhist256q;
:vwhist256 qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0810=0x2 & op0507=0x4 & qv2223 & tmpvreg_ & $(END_PACKET) {
build EndPacket;
<<COMMIT>>
vwhist256q(qv2223, tmpvreg_); # TODO: Does not properly convey vector inputs/outputs
}
# (v60,1) vwhist256 -- "vwhist256(Qv4):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 0 1 1 1 0 0 - - - - -
define pcodeop vwhist256qsat;
:vwhist256^":sat" qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0810=0x3 & op0507=0x4 & qv2223 & tmpvreg_ & $(END_PACKET) {
build EndPacket;
<<COMMIT>>
vwhist256qsat(qv2223, tmpvreg_); # TODO: Does not properly convey vector inputs/outputs
}
# (v60,1) vwhist128 -- "vwhist128(Qv4)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 1 0 - 1 0 0 - - - - -
define pcodeop vwhist128q;
:vwhist128 qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0910=0x2 & op0507=0x4 & qv2223 & tmpvreg_ & $(END_PACKET) {
build EndPacket;
<<COMMIT>>
vwhist128q(qv2223, tmpvreg_); # TODO: Does not properly convey vector inputs/outputs
}
# (v60,1) vwhist128 -- "vwhist128(Qv4,#u1)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 1 1 i 1 0 0 - - - - -
define pcodeop vwhist128qu;
:vwhist128 qv2223,"#"^i8 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0910=0x3 & op0507=0x4 & qv2223 & i8 & tmpvreg_ & $(END_PACKET) {
build EndPacket;
<<COMMIT>>
vwhist128qu(qv2223, tmpvreg_); # TODO: Does not properly convey vector inputs/outputs
}
# (v60,1) vhist -- "vhist"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 0 0 - 1 0 0 - - - - -
define pcodeop vhist;
:vhist EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0911=0x0 & op0507=0x4 & tmpvreg_ & $(END_PACKET) {
build EndPacket;
<<COMMIT>>
vhist(tmpvreg_); # TODO: Does not properly convey vector inputs/outputs
}
# (v60,1) vhist -- "vhist(Qv4)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 0 0 - 1 0 0 - - - - -
define pcodeop vhistq;
:vhist qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0910=0x0 & op0507=0x4 & qv2223 & tmpvreg_ & $(END_PACKET) {
build EndPacket;
<<COMMIT>>
vhistq(qv2223, tmpvreg_); # TODO: Does not properly convey vector inputs/outputs
}
# (v60,1) and -- "Qd4=and(Qs4,Qt4)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 0 0 d d
:and Qd2,qv0809,qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x0 & Qd2 & qv0809 & qv2223 & $(END_PACKET) {
Qd2 = qv0809 & qv2223;
build EndPacket;
}
# (v60,1) and -- "Qd4=and(Qs4,!Qt4)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 0 1 d d
:and Qd2,qv0809,Qv2223Not EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x5 & Qd2 & qv0809 & Qv2223Not & $(END_PACKET) {
Qd2 = qv0809 & Qv2223Not;
build EndPacket;
}
# (v60,1) or -- "Qd4=or(Qs4,Qt4)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 0 1 d d
:or Qd2,qv0809,qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x1 & Qd2 & qv0809 & qv2223 & $(END_PACKET) {
Qd2 = qv0809 | qv2223;
build EndPacket;
}
# (v60,1) or -- "Qd4=or(Qs4,!Qt4)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 0 0 d d
:or Qd2,qv0809,Qv2223Not EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x4 & Qd2 & qv0809 & Qv2223Not & $(END_PACKET) {
Qd2 = qv0809 | Qv2223Not;
build EndPacket;
}
# (v60,1) xor -- "Qd4=xor(Qs4,Qt4)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 1 1 d d
:xor Qd2,qv0809,qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x3 & Qd2 & qv0809 & qv2223 & $(END_PACKET) {
Qd2 = qv0809 ^ qv2223;
build EndPacket;
}
# (v60,1) vshuffe -- "Qd4.b=vshuffe(Qs4.h,Qt4.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 1 0 d d
define pcodeop vshuffe_QhQh;
:vshuffe Qd2^".b",qv0809^".h",qv2223^".h" EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x6 & Qd2 & qv0809 & qv2223 & $(END_PACKET) {
Qd2 = vshuffe_QhQh(qv0809,qv2223);
build EndPacket;
}
# (v60,1) vshuffe -- "Qd4.h=vshuffe(Qs4.w,Qt4.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 1 1 d d
define pcodeop vshuffe_QwQw;
:vshuffe Qd2^".h",qv0809^".w",qv2223^".w" EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x7 & Qd2 & qv0809 & qv2223 & $(END_PACKET) {
Qd2 = vshuffe_QhQh(qv0809,qv2223);
build EndPacket;
}
# (v60,1) vcombine -- "if (!Ps) Vdd=vcombine(Vu,Vv)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 1 0 0 1 0 v v v v v P P - u u u u u - s s d d d d d
#
# (v60,1) vcombine -- "if (Ps) Vdd=vcombine(Vu,Vv)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 1 0 0 1 1 v v v v v P P - u u u u u - s s d d d d d
define pcodeop vcombine;
:vcombine^VPuCond0506_S21 vdd4,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2227=0x29 & vddM=0 & VPuCond0506_S21 & vdd4 & vdd4_ & SetNRegRd5 & Vu_0812 & Vv_1620 & $(END_PACKET) {
build VPuCond0506_S21;
build Vu_0812;
build Vv_1620;
build EndPacket;
<<EXEC_COND>>
build VPuCond0506_S21;
if (ConditionReg == 0) goto <skip>;
vdd4_ = vcombine(Vu_0812,Vv_1620);
<skip>
<<COMMIT_COND>>
build VPuCond0506_S21;
if (ConditionReg == 0) goto <nocommit>;
vdd4 = vdd4_;
<nocommit>
}
# (v67,1) vcombine -- "if ([!]Qv4) Vdd32.swap = vcombine(Vu32,Vv32)"
:vcombine^VPuCond0506_S21 vdd4R,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2227=0x29 & vddM=1 & VPuCond0506_S21 & vdd4 & vdd4R & vdd4l & vdd4h & vdd4_ & SetNRegRd5 & Vu_0812 & Vv_1620 & $(END_PACKET) {
build VPuCond0506_S21;
build Vu_0812;
build Vv_1620;
build EndPacket;
<<EXEC_COND>>
build VPuCond0506_S21;
if (ConditionReg == 0) goto <skip>;
vdd4_ = vcombine(Vu_0812,Vv_1620);
<skip>
<<COMMIT_COND>>
build VPuCond0506_S21;
if (ConditionReg == 0) goto <nocommit>;
vdd4l = vdd4_($(HVX_VECTOR_SIZE));
vdd4h = vdd4_:$(HVX_VECTOR_SIZE);
<nocommit>
}
# (v60,1) vcombine -- "Vdd=vcombine(Vu,Vv)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d
:vcombine Vdd5,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x7 & Vdd5 & Vu_0812 & Vv_1620 & $(END_PACKET) {
Vdd5 = vcombine(Vu_0812,Vv_1620);
build EndPacket;
}
# (v60,1) vshuffoe -- "Vdd.h=vshuffoe(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d
define pcodeop vshuffoe_VhVh;
:vshuffoe VddH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x5 & VddH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VddH_0004 = vshuffoe_VhVh(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vshuffoe -- "Vdd.b=vshuffoe(Vu.b,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d
define pcodeop vshuffoe_VbVb;
:vshuffoe VddB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x6 & VddB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) {
VddB_0004 = vshuffoe_VbVb(VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vswap -- "Vdd=vswap(Qt4,Vu,Vv)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 1 u u u u u - t t d d d d d
define pcodeop vswap_QVwVw;
:vswap Vdd5,qv0506,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x1 & Vdd5 & qv0506 & Vu_0812 & Vv_1620 & $(END_PACKET) {
Vdd5 = vswap_QVwVw(qv0506,Vu_0812,Vv_1620);
build EndPacket;
}
# (v60,1) vzxt -- "Vdd.uh=vzxt(Vu.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 0 1 d d d d d
define pcodeop vzxt_Vub;
:vzxt VddUH_0004,VuUB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x1 & VddUH_0004 & VuUB_0812 & $(END_PACKET) {
VddUH_0004 = vzxt_Vub(VuUB_0812);
build EndPacket;
}
# (v60,1) vzxt -- "Vdd.uw=vzxt(Vu.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 1 0 d d d d d
define pcodeop vzxt_Vuh;
:vzxt VddUW_0004,VuUH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x2 & VddUW_0004 & VuUH_0812 & $(END_PACKET) {
VddUW_0004 = vzxt_Vuh(VuUH_0812);
build EndPacket;
}
# (v60,1) vsxt -- "Vdd.h=vsxt(Vu.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 1 1 d d d d d
define pcodeop vsxt_Vb;
:vsxt VddH_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x3 & VddH_0004 & VuB_0812 & $(END_PACKET) {
VddH_0004 = vsxt_Vb(VuB_0812);
build EndPacket;
}
# (v60,1) vsxt -- "Vdd.w=vsxt(Vu.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 0 0 d d d d d
define pcodeop Ww_vsxt_Vh;
:vsxt VddW_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x4 & VddW_0004 & VuH_0812 & $(END_PACKET) {
VddW_0004 = Ww_vsxt_Vh(VuH_0812);
build EndPacket;
}
# (v60,1) vadd -- "Vdd.b=vadd(Vuu.b,Vvv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d
define pcodeop vadd_WbWb;
:vadd VddB_0004,VuuB_0812,VvvB_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x4 & VddB_0004 & VuuB_0812 & VvvB_1620 & $(END_PACKET) {
VddB_0004 = vadd_WbWb(VuuB_0812,VvvB_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vdd.h=vadd(Vuu.h,Vvv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d
define pcodeop vadd_WhWh;
:vadd VddH_0004,VuuH_0812,VvvH_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x5 & VddH_0004 & VuuH_0812 & VvvH_1620 & $(END_PACKET) {
VddH_0004 = vadd_WhWh(VuuH_0812,VvvH_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vdd.w=vadd(Vuu.w,Vvv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d
define pcodeop Ww_vadd_WwWw;
:vadd VddW_0004,VuuW_0812,VvvW_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x6 & VddW_0004 & VuuW_0812 & VvvW_1620 & $(END_PACKET) {
VddW_0004 = Ww_vadd_WwWw(VuuW_0812,VvvW_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vdd.ub=vadd(Vuu.ub,Vvv.ub):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d
define pcodeop vadd_WubWub_sat;
:vadd^":sat" VddUB_0004,VuuUB_0812,VvvUB_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x7 & VddUB_0004 & VuuUB_0812 & VvvUB_1620 & $(END_PACKET) {
VddUB_0004 = vadd_WubWub_sat(VuuUB_0812,VvvUB_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vdd.uh=vadd(Vuu.uh,Vvv.uh):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d
define pcodeop vadd_WuhWuh_sat;
:vadd^":sat" VddUH_0004,VuuUH_0812,VvvUH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x0 & VddUH_0004 & VuuUH_0812 & VvvUH_1620 & $(END_PACKET) {
VddUH_0004 = vadd_WuhWuh_sat(VuuUH_0812,VvvUH_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vdd.h=vadd(Vuu.h,Vvv.h):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d
define pcodeop vadd_WhWh_sat;
:vadd^":sat" VddH_0004,VuuH_0812,VvvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x1 & VddH_0004 & VuuH_0812 & VvvH_1620 & $(END_PACKET) {
VddH_0004 = vadd_WhWh_sat(VuuH_0812,VvvH_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vdd.w=vadd(Vuu.w,Vvv.w):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d
define pcodeop Ww_vadd_WwWw_sat;
:vadd^":sat" VddW_0004,VuuW_0812,VvvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x2 & VddW_0004 & VuuW_0812 & VvvW_1620 & $(END_PACKET) {
VddW_0004 = Ww_vadd_WwWw_sat(VuuW_0812,VvvW_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vdd.b=vsub(Vuu.b,Vvv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d
define pcodeop vsub_WbWb;
:vsub VddB_0004,VuuB_0812,VvvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x3 & VddB_0004 & VuuB_0812 & VvvB_1620 & $(END_PACKET) {
VddB_0004 = vsub_WbWb(VuuB_0812,VvvB_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vdd.h=vsub(Vuu.h,Vvv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d
define pcodeop vsub_WhWh;
:vsub VddH_0004,VuuH_0812,VvvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x4 & VddH_0004 & VuuH_0812 & VvvH_1620 & $(END_PACKET) {
VddH_0004 = vsub_WhWh(VuuH_0812,VvvH_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vdd.w=vsub(Vuu.w,Vvv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d
define pcodeop Ww_vsub_WwWw;
:vsub VddW_0004,VuuW_0812,VvvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x5 & VddW_0004 & VuuW_0812 & VvvW_1620 & $(END_PACKET) {
VddW_0004 = Ww_vsub_WwWw(VuuW_0812,VvvW_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vdd.ub=vsub(Vuu.ub,Vvv.ub):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d
define pcodeop vsub_WubWub_sat;
:vsub^":sat" VddUB_0004,VuuUB_0812,VvvUB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x6 & VddUB_0004 & VuuUB_0812 & VvvUB_1620 & $(END_PACKET) {
VddUB_0004 = vsub_WubWub_sat(VuuUB_0812,VvvUB_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vdd.uh=vsub(Vuu.uh,Vvv.uh):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d
define pcodeop vsub_WuhWuh_sat;
:vsub^":sat" VddUH_0004,VuuUH_0812,VvvUH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x7 & VddUH_0004 & VuuUH_0812 & VvvUH_1620 & $(END_PACKET) {
VddUH_0004 = vsub_WuhWuh_sat(VuuUH_0812,VvvUH_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vdd.h=vsub(Vuu.h,Vvv.h):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d
define pcodeop vsub_WhWh_sat;
:vsub^":sat" VddH_0004,VuuH_0812,VvvH_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x0 & VddH_0004 & VuuH_0812 & VvvH_1620 & $(END_PACKET) {
VddH_0004 = vsub_WhWh_sat(VuuH_0812,VvvH_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vdd.w=vsub(Vuu.w,Vvv.w):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d
define pcodeop Ww_vsub_WwWw_sat;
:vsub^":sat" VddW_0004,VuuW_0812,VvvW_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x1 & VddW_0004 & VuuW_0812 & VvvW_1620 & $(END_PACKET) {
VddW_0004 = Ww_vsub_WwWw_sat(VuuW_0812,VvvW_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vdd.b=vadd(Vuu.b,Vvv.b):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d
define pcodeop vadd_WbWb_sat;
:vadd^":sat" VddB_0004,VuuB_0812,VvvB_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x0 & VddB_0004 & VuuB_0812 & VvvB_1620 & $(END_PACKET) {
VddB_0004 = vadd_WbWb_sat(VuuB_0812,VvvB_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vdd.b=vsub(Vuu.b,Vvv.b):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d
define pcodeop vsub_WbWb_sat;
:vsub^":sat" VddB_0004,VuuB_0812,VvvB_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x1 & VddB_0004 & VuuB_0812 & VvvB_1620 & $(END_PACKET) {
VddB_0004 = vsub_WbWb_sat(VuuB_0812,VvvB_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vdd.uw=vadd(Vuu.uw,Vvv.uw):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d
define pcodeop vadd_WuwWuw_sat;
:vadd^":sat" VddUW_0004,VuuUW_0812,VvvUW_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x2 & VddUW_0004 & VuuUW_0812 & VvvUW_1620 & $(END_PACKET) {
VddUW_0004 = vadd_WuwWuw_sat(VuuUW_0812,VvvUW_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vdd.uw=vsub(Vuu.uw,Vvv.uw):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d
define pcodeop vsub_WuwWuw_sat;
:vsub^":sat" VddUW_0004,VuuUW_0812,VvvUW_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x3 & VddUW_0004 & VuuUW_0812 & VvvUW_1620 & $(END_PACKET) {
VddUW_0004 = vsub_WuwWuw_sat(VuuUW_0812,VvvUW_1620);
build EndPacket;
}
# (v60,1) not -- "Qd4=not(Qs4)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 1 0 d d
:not Qd2,qv0809 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x2 & Qd2 & qv0809 & $(END_PACKET) {
Qd2 = ~qv0809;
build EndPacket;
}
# (v60,1) vand -- "Vd=vand(Qv4,Vu)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 u u u u u 0 0 0 d d d d d
#
define pcodeop vand_QV;
:vand Vd5,qv2223,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x3 & op13=0x1 & op0507=0x0 & Vd5 & qv2223 & Vu_0812 & $(END_PACKET) {
Vd5 = vand_QV(qv2223,Vu_0812);
build EndPacket;
}
# (v60,1) vand -- "Vd=vand(!Qv4,Vu)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 u u u u u 0 0 1 d d d d d
:vand Vd5,Qv2223Not,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x3 & op13=0x1 & op0507=0x1 & Vd5 & Qv2223Not & Vu_0812 & $(END_PACKET) {
Vd5 = vand_QV(Qv2223Not,Vu_0812);
build EndPacket;
}
# (v60,1) vmin -- "Vd.ub=vmin(Vu.ub,Vv.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d
define pcodeop vmin_VubVub;
:vmin VdUB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x1 & VdUB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) {
VdUB_0004 = vmin_VubVub(VuUB_0812,VvUB_1620);
build EndPacket;
}
# (v60,1) vmin -- "Vd.uh=vmin(Vu.uh,Vv.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d
define pcodeop vmin_VuhVuh;
:vmin VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x2 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) {
VdUH_0004 = vmin_VuhVuh(VuUH_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vmin -- "Vd.h=vmin(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d
define pcodeop vmin_VhVh;
:vmin VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x3 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdH_0004 = vmin_VhVh(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vmin -- "Vd.w=vmin(Vu.w,Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d
define pcodeop vmin_VwVw;
:vmin VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x4 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) {
VdW_0004 = vmin_VwVw(VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vmax -- "Vd.ub=vmax(Vu.ub,Vv.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d
define pcodeop vmax_VubVub;
:vmax VdUB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x5 & VdUB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) {
VdUB_0004 = vmax_VubVub(VuUB_0812,VvUB_1620);
build EndPacket;
}
# (v60,1) vmax -- "Vd.uh=vmax(Vu.uh,Vv.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d
define pcodeop vmax_VuhVuh;
:vmax VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x6 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) {
VdUH_0004 = vmax_VuhVuh(VuUH_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vmax -- "Vd.h=vmax(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d
define pcodeop vmax_VhVh;
:vmax VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x7 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdH_0004 = vmax_VhVh(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vmax -- "Vd.w=vmax(Vu.w,Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d
define pcodeop vmax_VwVw;
:vmax VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x0 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) {
VdW_0004 = vmax_VwVw(VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vmin -- "Vd.b=vmin(Vu.b,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d
define pcodeop vmin_VbVb;
:vmin VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x4 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) {
VdB_0004 = vmin_VbVb(VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vmax -- "Vd.b=vmax(Vu.b,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d
define pcodeop vmax_VbVb;
:vmax VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x5 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) {
VdB_0004 = vmax_VbVb(VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vmax -- "Vd.sf=vmax(Vu.sf,Vv.sf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 0 0 1 d d d d d
define pcodeop vmax_VsfVsf;
:vmax VdSF_0004,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x1 & op0507=0x1 & VdSF_0004 & VuSF_0812 & VvSF_1620 & $(END_PACKET) {
VdSF_0004 = vmax_VsfVsf(VuSF_0812,VvSF_1620);
build EndPacket;
}
# (v60,1) vmin -- "Vd.sf=vmin(Vu.sf,Vv.sf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 0 1 0 d d d d d
define pcodeop vmin_VsfVsf;
:vmin VdSF_0004,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x1 & op0507=0x2 & VdSF_0004 & VuSF_0812 & VvSF_1620 & $(END_PACKET) {
VdSF_0004 = vmin_VsfVsf(VuSF_0812,VvSF_1620);
build EndPacket;
}
# (v60,1) vmax -- "Vd.hf=vmax(Vu.hf,Vv.hf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 0 1 1 d d d d d
define pcodeop vmax_VhfVhf;
:vmax VdHF_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x1 & op0507=0x3 & VdHF_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) {
VdHF_0004 = vmax_VhfVhf(VuHF_0812,VvHF_1620);
build EndPacket;
}
# (v60,1) vmin -- "Vd.hf=vmin(Vu.hf,Vv.hf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 1 0 0 d d d d d
define pcodeop vmin_VhfVhf;
:vmin VdHF_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x1 & op0507=0x4 & VdHF_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) {
VdHF_0004 = vmin_VhfVhf(VuHF_0812,VvHF_1620);
build EndPacket;
}
# (v60,1) vabs -- "Vd.h=vabs(Vu.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 0 0 d d d d d
define pcodeop vabs_Vh;
:vabs VdH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x0 & op13=0x0 & op0507=0x0 & VdH_0004 & VuH_0812 & $(END_PACKET) {
VdH_0004 = vabs_Vh(VuH_0812);
build EndPacket;
}
# (v60,1) vabs -- "Vd.h=vabs(Vu.h):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 0 1 d d d d d
define pcodeop vabs_Vh_sat;
:vabs^":sat" VdH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x0 & op13=0x0 & op0507=0x1 & VdH_0004 & VuH_0812 & $(END_PACKET) {
VdH_0004 = vabs_Vh_sat(VuH_0812);
build EndPacket;
}
# (v60,1) vabs -- "Vd.w=vabs(Vu.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 1 0 d d d d d
define pcodeop vabs_Vw;
:vabs VdW_0004,VuW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x0 & op13=0x0 & op0507=0x2 & VdW_0004 & VuW_0812 & $(END_PACKET) {
VdW_0004 = vabs_Vw(VuW_0812);
build EndPacket;
}
# (v60,1) vabs -- "Vd.w=vabs(Vu.w):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 1 1 d d d d d
define pcodeop vabs_Vw_sat;
:vabs^":sat" VdW_0004,VuW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x0 & op13=0x0 & op0507=0x3 & VdW_0004 & VuW_0812 & $(END_PACKET) {
VdW_0004 = vabs_Vw_sat(VuW_0812);
build EndPacket;
}
# (v60,1) vabs -- "Vd.b=vabs(Vu.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 0 0 d d d d d
define pcodeop vabs_Vb;
:vabs VdB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x4 & VdB_0004 & VuB_0812 & $(END_PACKET) {
VdB_0004 = vabs_Vb(VuB_0812);
build EndPacket;
}
# (v60,1) vabs -- "Vd.b=vabs(Vu.b):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 0 1 d d d d d
define pcodeop vabs_Vb_sat;
:vabs^":sat" VdB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x5 & VdB_0004 & VuB_0812 & $(END_PACKET) {
VdB_0004 = vabs_Vb_sat(VuB_0812);
build EndPacket;
}
# (v60,1) vadd -- "Vd.w=vadd(Vu.w,Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d
define pcodeop vadd_VwVw;
:vadd VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x0 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) {
VdW_0004 = vadd_VwVw(VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vd.ub=vadd(Vu.ub,Vv.ub):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d
define pcodeop vadd_VubVub_sat;
:vadd^":sat" VdUB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x1 & VdUB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) {
VdUB_0004 = vadd_VubVub_sat(VuUB_0812,VvUB_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vd.uh=vadd(Vu.uh,Vv.uh):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d
define pcodeop vadd_VuhVuh_sat;
:vadd^":sat" VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x2 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) {
VdUH_0004 = vadd_VuhVuh_sat(VuUH_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vd.h=vadd(Vu.h,Vv.h):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d
define pcodeop vadd_VhVh_sat;
:vadd^":sat" VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x3 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdH_0004 = vadd_VhVh_sat(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vd.w=vadd(Vu.w,Vv.w):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d
define pcodeop vadd_VwVw_sat;
:vadd^":sat" VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x4 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) {
VdW_0004 = vadd_VwVw_sat(VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vd.b=vsub(Vu.b,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d
define pcodeop vsub_VbVb;
:vsub VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x5 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) {
VdB_0004 = vsub_VbVb(VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vd.h=vsub(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d
define pcodeop vsub_VhVh;
:vsub VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x6 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdH_0004 = vsub_VhVh(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vd.w=vsub(Vu.w,Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d
define pcodeop vsub_VwVw;
:vsub VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x7 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) {
VdW_0004 = vsub_VwVw(VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vd.ub=vsub(Vu.ub,Vv.ub):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d
define pcodeop vsub_VubVub_sat;
:vsub^":sat" VdUB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x0 & VdUB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) {
VdUB_0004 = vsub_VubVub_sat(VuUB_0812,VvUB_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vd.uh=vsub(Vu.uh,Vv.uh):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d
define pcodeop vsub_VuhVuh_sat;
:vsub^":sat" VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x1 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) {
VdUH_0004 = vsub_VuhVuh_sat(VuUH_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vd.h=vsub(Vu.h,Vv.h):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d
define pcodeop vsub_VhVh_sat;
:vsub^":sat" VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x2 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdH_0004 = vsub_VhVh_sat(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vd.w=vsub(Vu.w,Vv.w):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d
define pcodeop vsub_VwVw_sat;
:vsub^":sat" VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x3 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) {
VdW_0004 = vsub_VwVw_sat(VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vd.ub=vadd(Vu.ub,Vv.b):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d
define pcodeop vadd_VubVb_sat;
:vadd^":sat" VdUB_0004,VuUB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x4 & VdUB_0004 & VuUB_0812 & VvB_1620 & $(END_PACKET) {
VdUB_0004 = vadd_VubVb_sat(VuUB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vd.ub=vsub(Vu.ub,Vv.b):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d
define pcodeop vsub_VubVb_sat;
:vsub^":sat" VdUB_0004,VuUB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x5 & VdUB_0004 & VuUB_0812 & VvB_1620 & $(END_PACKET) {
VdUB_0004 = vsub_VubVb_sat(VuUB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vd.b=vadd(Vu.b,Vv.b):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d
define pcodeop vadd_VbVb_sat;
:vadd^":sat" VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x0 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) {
VdB_0004 = vadd_VbVb_sat(VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vd.b=vsub(Vu.b,Vv.b):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d
define pcodeop vsub_VbVb_sat;
:vsub^":sat" VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x2 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) {
VdB_0004 = vsub_VbVb_sat(VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vd.uw=vadd(Vu.uw,Vv.uw):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d
define pcodeop vadd_VuwVuw_sat;
:vadd^":sat" VdUW_0004,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x1 & VdUW_0004 & VuUW_0812 & VvUW_1620 & $(END_PACKET) {
VdUW_0004 = vadd_VuwVuw_sat(VuUW_0812,VvUW_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vd.b=vadd(Vu.b,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d
define pcodeop vadd_VbVb;
:vadd VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x6 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) {
VdB_0004 = vadd_VbVb(VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vd.h=vadd(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d
define pcodeop vadd_VhVh;
:vadd VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x7 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdH_0004 = vadd_VhVh(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vd.uw=vsub(Vu.uw,Vv.uw):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d
define pcodeop vsub_VuwVuw_sat;
:vsub^":sat" VdUW_0004,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x4 & VdUW_0004 & VuUW_0812 & VvUW_1620 & $(END_PACKET) {
VdUW_0004 = vsub_VuwVuw_sat(VuUW_0812,VvUW_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vd.w=vadd(Vu.w,Vv.w,Qx4):carry"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 1 u u u u u 0 x x d d d d d
define pcodeop vsub_VwVwQ_carry;
:vadd^":carry" VdW_0004,VuW_0812,VvW_1620,qv0506 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x1 & op7=0x0 & VdW_0004 & VuW_0812 & VvW_1620 & qv0506 & $(END_PACKET) {
VdW_0004 = vsub_VwVwQ_carry(VuW_0812,VvW_1620,qv0506);
build EndPacket;
}
# (v60,1) vsub -- "Vd.w=vsub(Vu.w,Vv.w,Qx4):carry"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 1 u u u u u 1 x x d d d d d
define pcodeop vsub_VwVwQ_carry_sat;
:vsub^":carry" VdW_0004,VuW_0812,VvW_1620,qv0506 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x1 & op7=0x1 & VdW_0004 & VuW_0812 & VvW_1620 & qv0506 & $(END_PACKET) {
VdW_0004 = vsub_VwVwQ_carry_sat(VuW_0812,VvW_1620,qv0506);
build EndPacket;
}
# (v60,1) vadd -- "Vd.w=vadd(Vu.w,Vv.w,Qs4):carry:sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 1 1 0 0 v v v v v P P 1 u u u u u 0 s s d d d d d
define pcodeop vadd_VwVwQ_carry_sat;
:vadd^":carry:sat" VdW_0004,VuW_0812,VvW_1620,qv0506 EndPacket is iclass=0x1 & op2127=0x6c & op13=0x1 & op7=0x0 & VdW_0004 & VuW_0812 & VvW_1620 & qv0506 & $(END_PACKET) {
VdW_0004 = vadd_VwVwQ_carry_sat(VuW_0812,VvW_1620,qv0506);
build EndPacket;
}
# (v60,1) vadd -- "Vd.w,Qe4=vadd(Vu.w,Vv.w):carry"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 1 1 0 1 v v v v v P P 1 u u u u u 0 e e d d d d d
define pcodeop vadd_VwVw_carryResult;
:vadd^":carry" VdW_0004,qv0506,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x6d & op13=0x1 & op7=0x0 & VdW_0004 & qv0506 & VuW_0812 & VvW_1620 & $(END_PACKET) {
tmpQ:$(HVX_PREDICATE_SIZE) = vadd_VwVw_carryResult(VuW_0812,VvW_1620);
VdW_0004 = vadd_VwVw(VuW_0812,VvW_1620);
build EndPacket;
<<COMMIT>>
qv0506 = tmpQ;
}
# (v60,1) vsub -- "Vd.w,Qe4=vsub(Vu.w,Vv.w):carry"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 1 1 0 1 v v v v v P P 1 u u u u u 1 e e d d d d d
define pcodeop vsub_VwVw_carryResult;
:vsub^":carry" VdW_0004,qv0506,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x6d & op13=0x1 & op7=0x1 & VdW_0004 & qv0506 & VuW_0812 & VvW_1620 & $(END_PACKET) {
tmpQ:$(HVX_PREDICATE_SIZE) = vsub_VwVw_carryResult(VuW_0812,VvW_1620);
VdW_0004 = vsub_VwVw(VuW_0812,VvW_1620);
build EndPacket;
<<COMMIT>>
qv0506 = tmpQ;
}
# (v60,1) vand -- "Vd=vand(Vu,Vv)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d
:vand Vd5,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x0 & op0507=0x5 & Vd5 & Vu_0812 & Vv_1620 & $(END_PACKET) {
Vd5 = Vu_0812 & Vv_1620;
build EndPacket;
}
# (v60,1) vor -- "Vd=vor(Vu,Vv)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d
:vor Vd5,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x0 & op0507=0x6 & Vd5 & Vu_0812 & Vv_1620 & $(END_PACKET) {
Vd5 = Vu_0812 | Vv_1620;
build EndPacket;
}
# (v60,1) vxor -- "Vd=vxor(Vu,Vv)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d
:vxor Vd5,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x0 & op0507=0x7 & Vd5 & Vu_0812 & Vv_1620 & $(END_PACKET) {
Vd5 = Vu_0812 ^ Vv_1620;
build EndPacket;
}
# (v60,1) vnot -- "Vd=vnot(Vu)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 1 0 0 d d d d d
:vnot Vd5,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x0 & op13=0x0 & op0507=0x4 & Vd5 & Vu_0812 & $(END_PACKET) {
Vd5 = ~Vu_0812;
build EndPacket;
}
# (v60,1) "if (Ps) Vd=Vu"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 1 0 0 0 0 - - - - - P P - u u u u u - s s d d d d d
#
# (v60,1) "if (!Ps) Vd=Vu"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 1 0 0 0 1 - - - - - P P - u u u u u - s s d d d d d
:assign^VPuCond0506_S21 vd5,Vu_0812 EndPacket is iclass=0x1 & op2227=0x28 & VPuCond0506_S21 & vd5 & vd5_ & SetVNRegVd5 & Vu_0812 & $(END_PACKET) [ cond=1; ] {
build VPuCond0506_S21;
build Vu_0812;
build EndPacket;
<<EXEC_COND>>
build VPuCond0506_S21;
if (ConditionReg == 0) goto <skip>;
vd5_ = Vu_0812;
<skip>
<<COMMIT_COND>>
build VPuCond0506_S21;
if (ConditionReg == 0) goto <nocommit>;
vd5 = vd5_;
<nocommit>
}
# (v60,1) "Vd=Vu"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - 0 1 1 P P 1 u u u u u 1 1 1 d d d d d
:assign Vd5,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op2123=0x0 & op1620=0x3 & op13=0x1 & op0507=0x7 & Vd5 & Vu_0812 & $(END_PACKET) [ cond=0; ] {
Vd5 = Vu_0812; # Vd5 handles unconditional commit
build EndPacket;
}
# (v60,1) "Vd.tmp=Vu"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 1 0 d d d d d
:assign Vd5tmp,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op2123=0x0 & op1620=0x1 & op13=0x0 & op0507=0x6 & Vd5tmp & Vu_0812 & $(END_PACKET) {
Vd5tmp = Vu_0812;
build EndPacket;
}
# (v60,1) vcombine -- "Vdd.tmp=vcombine(Vu,Vv)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d
:vcombine Vdd5tmp,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x7 & Vdd5tmp & Vu_0812 & Vv_1620 & $(END_PACKET) {
Vdd5tmp = vcombine(Vu_0812,Vv_1620);
build EndPacket;
}
# (v60,1) vavg -- "Vd.ub=vavg(Vu.ub,Vv.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d
define pcodeop vavg_VubVub;
:vavg VdUB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x4 & VdUB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) {
VdUB_0004 = vavg_VubVub(VuUB_0812,VvUB_1620);
build EndPacket;
}
# (v60,1) vavg -- "Vd.uh=vavg(Vu.uh,Vv.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d
define pcodeop vavg_VuhVuh;
:vavg VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x5 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) {
VdUH_0004 = vavg_VuhVuh(VuUH_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vavg -- "Vd.h=vavg(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d
define pcodeop vavg_VhVh;
:vavg VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x6 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdH_0004 = vavg_VhVh(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vavg -- "Vd.w=vavg(Vu.w,Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d
define pcodeop vavg_VwVw;
:vavg VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x7 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) {
VdW_0004 = vavg_VwVw(VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vnavg -- "Vd.b=vnavg(Vu.ub,Vv.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d
define pcodeop vnavg_VubVub;
:vnavg VdB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x0 & VdB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) {
VdB_0004 = vnavg_VubVub(VuUB_0812,VvUB_1620);
build EndPacket;
}
# (v60,1) vnavg -- "Vd.h=vnavg(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d
define pcodeop vnavg_VhVh;
:vnavg VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x1 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdH_0004 = vnavg_VhVh(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vnavg -- "Vd.w=vnavg(Vu.w,Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d
define pcodeop vnavg_VwVw;
:vnavg VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x2 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) {
VdW_0004 = vnavg_VwVw(VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vavg -- "Vd.ub=vavg(Vu.ub,Vv.ub):rnd"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d
define pcodeop vavg_VubVub_rnd;
:vavg^":rnd" VdUB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x3 & VdUB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) {
VdUB_0004 = vavg_VubVub_rnd(VuUB_0812,VvUB_1620);
build EndPacket;
}
# (v60,1) vavg -- "Vd.uh=vavg(Vu.uh,Vv.uh):rnd"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d
define pcodeop vavg_VuhVuh_rnd;
:vavg^":rnd" VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x4 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) {
VdUH_0004 = vavg_VuhVuh_rnd(VuUH_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vavg -- "Vd.h=vavg(Vu.h,Vv.h):rnd"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d
define pcodeop vavg_VhVh_rnd;
:vavg^":rnd" VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x5 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdH_0004 = vavg_VhVh_rnd(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vavg -- "Vd.w=vavg(Vu.w,Vv.w):rnd"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d
define pcodeop vavg_VwVw_rnd;
:vavg^":rnd" VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x6 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) {
VdW_0004 = vavg_VwVw_rnd(VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vavg -- "Vd.uw=vavg(Vu.uw,Vv.uw)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 1 0 d d d d d
define pcodeop vavg_VuwVuw;
:vavg VdUW_0004,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x1 & op0507=0x2 & VdUW_0004 & VuUW_0812 & VvUW_1620 & $(END_PACKET) {
VdUW_0004 = vavg_VuwVuw(VuUW_0812,VvUW_1620);
build EndPacket;
}
# (v60,1) vavg -- "Vd.uw=vavg(Vu.uw,Vv.uw):rnd"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 1 1 d d d d d
define pcodeop vavg_VuwVuw_rnd;
:vavg^":rnd" VdUW_0004,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x1 & op0507=0x3 & VdUW_0004 & VuUW_0812 & VvUW_1620 & $(END_PACKET) {
VdUW_0004 = vavg_VuwVuw_rnd(VuUW_0812,VvUW_1620);
build EndPacket;
}
# (v60,1) vavg -- "Vd.b=vavg(Vu.b,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 1 0 0 d d d d d
define pcodeop vavg_VbVb;
:vavg VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x1 & op0507=0x4 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) {
VdB_0004 = vavg_VbVb(VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vavg -- "Vd.b=vavg(Vu.b,Vv.b):rnd"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 1 0 1 d d d d d
define pcodeop vavg_VbVb_rnd;
:vavg^":rnd" VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x1 & op0507=0x5 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) {
VdB_0004 = vavg_VbVb_rnd(VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vnavg -- "Vd.b=vnavg(Vu.b,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 1 1 0 d d d d d
define pcodeop vnavg_VbVb;
:vnavg VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x1 & op0507=0x6 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) {
VdB_0004 = vnavg_VbVb(VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vcmp.eq -- "Qd4=vcmp.eq(Vu.b,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 0 0 0 d d
define pcodeop vcmp_eq_VbVb;
:vcmp.eq Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x0 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) {
Qd2 = vcmp_eq_VbVb(VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vcmp.eq -- "Qd4=vcmp.eq(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 0 0 1 d d
define pcodeop vcmp_eq_VhVh;
:vcmp.eq Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x1 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) {
Qd2 = vcmp_eq_VhVh(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vcmp.eq -- "Qd4=vcmp.eq(Vu.w,Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 0 1 0 d d
define pcodeop vcmp_eq_VwVw;
:vcmp.eq Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x2 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) {
Qd2 = vcmp_eq_VwVw(VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.b,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 1 0 0 d d
define pcodeop vcmp_gt_VbVb;
:vcmp.gt Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x4 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) {
Qd2 = vcmp_gt_VbVb(VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 1 0 1 d d
define pcodeop vcmp_gt_VhVh;
:vcmp.gt Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x5 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) {
Qd2 = vcmp_gt_VhVh(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.w,Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 1 1 0 d d
define pcodeop vcmp_gt_VwVw;
:vcmp.gt Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x6 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) {
Qd2 = vcmp_gt_VwVw(VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.ub,Vv.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 1 0 0 0 d d
define pcodeop vcmp_gt_VubVub;
:vcmp.gt Qd2,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x8 & Qd2 & VuUB_0812 & VvUB_1620 & $(END_PACKET) {
Qd2 = vcmp_gt_VubVub(VuUB_0812,VvUB_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.uh,Vv.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 1 0 0 1 d d
define pcodeop vcmp_gt_VuhVuh;
:vcmp.gt Qd2,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x9 & Qd2 & VuUH_0812 & VvUH_1620 & $(END_PACKET) {
Qd2 = vcmp_gt_VuhVuh(VuUH_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.uw,Vv.uw)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 1 0 1 0 d d
define pcodeop vcmp_gt_VuwVuw;
:vcmp.gt Qd2,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0xa & Qd2 & VuUW_0812 & VvUW_1620 & $(END_PACKET) {
Qd2 = vcmp_gt_VuwVuw(VuUW_0812,VvUW_1620);
build EndPacket;
}
# (v60,1) vcmp.eq -- "Qx4&=vcmp.eq(Vu.b,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 0 0 0 x x
define pcodeop vcmp_eqand_QVbVb;
:vcmp.eq&= Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x0 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) {
Qd2 = vcmp_eqand_QVbVb(Qd2,VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vcmp.eq -- "Qx4&=vcmp.eq(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 0 0 1 x x
define pcodeop vcmp_eqand_QVhVh;
:vcmp.eq&= Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x1 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) {
Qd2 = vcmp_eqand_QVhVh(Qd2,VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vcmp.eq -- "Qx4&=vcmp.eq(Vu.w,Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 0 1 0 x x
define pcodeop vcmp_eqand_QVwVw;
:vcmp.eq&= Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x2 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) {
Qd2 = vcmp_eqand_QVwVw(Qd2,VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.b,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 1 0 0 x x
define pcodeop vcmp_gtand_QVbVb;
:vcmp.gt&= Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x4 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) {
Qd2 = vcmp_gtand_QVbVb(Qd2,VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 1 0 1 x x
define pcodeop vcmp_gtand_QVhVh;
:vcmp.gt&= Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x5 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) {
Qd2 = vcmp_gtand_QVhVh(Qd2,VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.w,Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 1 1 0 x x
define pcodeop vcmp_gtand_QVwVw;
:vcmp.gt&= Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x6 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) {
Qd2 = vcmp_gtand_QVwVw(Qd2,VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.ub,Vv.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 0 0 0 x x
define pcodeop vcmp_gtand_QVubVub;
:vcmp.gt&= Qd2,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x8 & Qd2 & VuUB_0812 & VvUB_1620 & $(END_PACKET) {
Qd2 = vcmp_gtand_QVubVub(Qd2,VuUB_0812,VvUB_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.uh,Vv.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 0 0 1 x x
define pcodeop vcmp_gtand_QVuhVuh;
:vcmp.gt&= Qd2,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x9 & Qd2 & VuUH_0812 & VvUH_1620 & $(END_PACKET) {
Qd2 = vcmp_gtand_QVuhVuh(Qd2,VuUH_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.uw,Vv.uw)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 0 1 0 x x
define pcodeop vcmp_gtand_QVuwVuw;
:vcmp.gt&= Qd2,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0xa & Qd2 & VuUW_0812 & VvUW_1620 & $(END_PACKET) {
Qd2 = vcmp_gtand_QVuwVuw(Qd2,VuUW_0812,VvUW_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.sf,Vv.sf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 1 0 0 x x
define pcodeop vcmp_gtor_QVsfVsf;
:vcmp.gt|= Qd2,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0xc & Qd2 & VuSF_0812 & VvSF_1620 & $(END_PACKET) {
Qd2 = vcmp_gtor_QVsfVsf(Qd2,VuSF_0812,VvSF_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.hf,Vv.hf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 1 0 1 x x
define pcodeop vcmp_gtor_QVhfVhf;
:vcmp.gt|= Qd2,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0xd & Qd2 & VuHF_0812 & VvHF_1620 & $(END_PACKET) {
Qd2 = vcmp_gtor_QVhfVhf(Qd2,VuHF_0812,VvHF_1620);
build EndPacket;
}
# (v60,1) vcmp.eq -- "Qx4|=vcmp.eq(Vu.b,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 0 0 0 x x
define pcodeop vcmp_eqor_QVbVb;
:vcmp.eq|= Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x10 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) {
Qd2 = vcmp_eqor_QVbVb(Qd2,VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vcmp.eq -- "Qx4|=vcmp.eq(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 0 0 1 x x
define pcodeop vcmp_eqor_QVhVh;
:vcmp.eq|= Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x11 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) {
Qd2 = vcmp_eqor_QVhVh(Qd2,VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vcmp.eq -- "Qx4|=vcmp.eq(Vu.w,Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 0 1 0 x x
define pcodeop vcmp_eqor_QVwVw;
:vcmp.eq|= Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x12 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) {
Qd2 = vcmp_eqor_QVwVw(Qd2,VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.b,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 1 0 0 x x
define pcodeop vcmp_gtor_QVbVb;
:vcmp.gt|= Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x14 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) {
Qd2 = vcmp_gtor_QVbVb(Qd2,VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 1 0 1 x x
define pcodeop vcmp_gtor_QVhVh;
:vcmp.gt|= Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x15 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) {
Qd2 = vcmp_gtor_QVhVh(Qd2,VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.w,Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 1 1 0 x x
define pcodeop vcmp_gtor_QVwVw;
:vcmp.gt|= Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x16 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) {
Qd2 = vcmp_gtor_QVwVw(Qd2,VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.ub,Vv.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 0 0 0 x x
define pcodeop vcmp_gtor_QVubVub;
:vcmp.gt|= Qd2,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x18 & Qd2 & VuUB_0812 & VvUB_1620 & $(END_PACKET) {
Qd2 = vcmp_gtor_QVubVub(Qd2,VuUB_0812,VvUB_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.uh,Vv.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 0 0 1 x x
define pcodeop vcmp_gtor_QVuhVuh;
:vcmp.gt|= Qd2,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x19 & Qd2 & VuUH_0812 & VvUH_1620 & $(END_PACKET) {
Qd2 = vcmp_gtor_QVuhVuh(Qd2,VuUH_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.uw,Vv.uw)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 0 1 0 x x
define pcodeop vcmp_gtor_QVuwVuw;
:vcmp.gt|= Qd2,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x1a & Qd2 & VuUW_0812 & VvUW_1620 & $(END_PACKET) {
Qd2 = vcmp_gtor_QVuwVuw(Qd2,VuUW_0812,VvUW_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.sf,Vv.sf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 1 0 0 d d
define pcodeop vcmp_gt_VsfVsf;
:vcmp.gt Qd2,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x1c & Qd2 & VuSF_0812 & VvSF_1620 & $(END_PACKET) {
Qd2 = vcmp_gt_VsfVsf(VuSF_0812,VvSF_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.hf,Vv.hf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 1 0 1 d d
define pcodeop vcmp_gt_VhfVhf;
:vcmp.gt Qd2,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x1d & Qd2 & VuHF_0812 & VvHF_1620 & $(END_PACKET) {
Qd2 = vcmp_gt_VhfVhf(VuHF_0812,VvHF_1620);
build EndPacket;
}
# (v60,1) vcmp.eq -- "Qx4^=vcmp.eq(Vu.b,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 0 0 0 x x
define pcodeop vcmp_eqxacc_QVbVb;
:vcmp.eq^"^=" Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x20 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) {
Qd2 = vcmp_eqxacc_QVbVb(Qd2,VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vcmp.eq -- "Qx4^=vcmp.eq(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 0 0 1 x x
define pcodeop vcmp_eqxacc_QVhVh;
:vcmp.eq^"^=" Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x21 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) {
Qd2 = vcmp_eqxacc_QVhVh(Qd2,VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vcmp.eq -- "Qx4^=vcmp.eq(Vu.w,Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 0 1 0 x x
define pcodeop vcmp_eqxacc_QVwVw;
:vcmp.eq^"^=" Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x22 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) {
Qd2 = vcmp_eqxacc_QVwVw(Qd2,VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.b,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 1 0 0 x x
define pcodeop vcmp_gtxacc_QVbVb;
:vcmp.gt^"^=" Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x24 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) {
Qd2 = vcmp_gtxacc_QVbVb(Qd2,VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 1 0 1 x x
define pcodeop vcmp_gtxacc_QVhVh;
:vcmp.gt^"^=" Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x25 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) {
Qd2 = vcmp_gtxacc_QVhVh(Qd2,VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.w,Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 1 1 0 x x
define pcodeop vcmp_gtxacc_QVwVw;
:vcmp.gt^"^=" Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x26 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) {
Qd2 = vcmp_gtxacc_QVwVw(Qd2,VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.ub,Vv.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 1 0 0 0 x x
define pcodeop vcmp_gtxacc_QVubVub;
:vcmp.gt^"^=" Qd2,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x28 & Qd2 & VuUB_0812 & VvUB_1620 & $(END_PACKET) {
Qd2 = vcmp_gtxacc_QVubVub(Qd2,VuUB_0812,VvUB_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.uh,Vv.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 1 0 0 1 x x
define pcodeop vcmp_gtxacc_QVuhVuh;
:vcmp.gt^"^=" Qd2,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x29 & Qd2 & VuUH_0812 & VvUH_1620 & $(END_PACKET) {
Qd2 = vcmp_gtxacc_QVuhVuh(Qd2,VuUH_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.uw,Vv.uw)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 1 0 1 0 x x
define pcodeop vcmp_gtxacc_QVuwVuw;
:vcmp.gt^"^=" Qd2,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x2a & Qd2 & VuUW_0812 & VvUW_1620 & $(END_PACKET) {
Qd2 = vcmp_gtxacc_QVuwVuw(Qd2,VuUW_0812,VvUW_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.sf,Vv.sf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 0 0 1 0 x x
define pcodeop vcmp_gtand_QVsfVsf;
:vcmp.gt^"&=" Qd2,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x32 & Qd2 & VuSF_0812 & VvSF_1620 & $(END_PACKET) {
Qd2 = vcmp_gtand_QVsfVsf(Qd2,VuSF_0812,VvSF_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.hf,Vv.hf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 0 0 1 1 x x
define pcodeop vcmp_gtand_QVhfVhf;
:vcmp.gt^"&=" Qd2,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x33 & Qd2 & VuHF_0812 & VvHF_1620 & $(END_PACKET) {
Qd2 = vcmp_gtand_QVhfVhf(Qd2,VuHF_0812,VvHF_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.sf,Vv.sf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 1 0 1 0 x x
define pcodeop vcmp_gtxacc_QVsfVsf;
:vcmp.gt^"^=" Qd2,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x3a & Qd2 & VuSF_0812 & VvSF_1620 & $(END_PACKET) {
Qd2 = vcmp_gtxacc_QVsfVsf(Qd2,VuSF_0812,VvSF_1620);
build EndPacket;
}
# (v60,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.hf,Vv.hf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 1 0 1 1 x x
define pcodeop vcmp_gtxacc_QVhfVhf;
:vcmp.gt^"^=" Qd2,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x3b & Qd2 & VuHF_0812 & VvHF_1620 & $(END_PACKET) {
Qd2 = vcmp_gtxacc_QVhfVhf(Qd2,VuHF_0812,VvHF_1620);
build EndPacket;
}
# (v60,1) "if (Qv4) Vx.b+=Vu.b"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 0 0 x x x x x
define pcodeop condnac_QnVbVb;
# TODO: Verify that Ghidra renders properly (other cases like this exist)
:accum^".if("^qv2223^")+=" VsB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x0 & qv2223 & Vd5 & VsB_0004 & VuB_0812 & $(END_PACKET) {
Vd5 = condnac_QnVbVb(qv2223,VsB_0004,VuB_0812);
build EndPacket;
}
# (v60,1) "if (!Qv4) Vx.b+=Vu.b"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 1 1 x x x x x
# TODO: Verify that Ghidra renders properly (other cases like this exist)
:accum^".if(!"^qv2223^")+=" VsB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x3 & qv2223 & Vd5 & VsB_0004 & VuB_0812 & $(END_PACKET) {
Vd5 = condnac_QnVbVb(~qv2223,VsB_0004,VuB_0812);
build EndPacket;
}
# (v60,1) "if (Qv4) Vx.h+=Vu.h"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 0 1 x x x x x
define pcodeop condnac_QnVhVh;
:accum^".if("^qv2223^")+=" VsH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x1 & qv2223 & Vd5 & VsH_0004 & VuH_0812 & $(END_PACKET) {
Vd5 = condnac_QnVhVh(qv2223,VsH_0004,VuH_0812);
build EndPacket;
}
# (v60,1) "if (!Qv4) Vx.h+=Vu.h"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 0 0 x x x x x
:accum^".if(!"^qv2223^")+=" VsH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x4 & qv2223 & Vd5 & VsH_0004 & VuH_0812 & $(END_PACKET) {
Vd5 = condnac_QnVhVh(~qv2223,VsH_0004,VuH_0812);
build EndPacket;
}
# (v60,1) "if (Qv4) Vx.w+=Vu.w"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 1 0 x x x x x
define pcodeop condnac_QnVwVw;
:accum^".if("^qv2223^")+=" VsW_0004,VuW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x2 & qv2223 & Vd5 & VsW_0004 & VuW_0812 & $(END_PACKET) {
Vd5 = condnac_QnVwVw(qv2223,VsW_0004,VuW_0812);
build EndPacket;
}
# (v60,1) "if (!Qv4) Vx.w+=Vu.w"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 0 1 x x x x x
:accum^".if(!"^qv2223^")+=" VsW_0004,VuW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x5 & qv2223 & Vd5 & VsW_0004 & VuW_0812 & $(END_PACKET) {
Vd5 = condnac_QnVwVw(~qv2223,VsW_0004,VuW_0812);
build EndPacket;
}
# (v60,1) "if (Qv4) Vx.b-=Vu.b"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 1 0 x x x x x
define pcodeop condnac_QVbVb;
:accum^".if("^qv2223^")-=" VsB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x6 & qv2223 & Vd5 & VsB_0004 & VuB_0812 & $(END_PACKET) {
Vd5 = condnac_QVbVb(qv2223,VsB_0004,VuB_0812);
build EndPacket;
}
# (v60,1) "if (!Qv4) Vx.b-=Vu.b"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 0 1 x x x x x
:accum^".if(!"^qv2223^")-=" VsB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0507=0x1 & qv2223 & Vd5 & VsB_0004 & VuB_0812 & $(END_PACKET) {
Vd5 = condnac_QVbVb(~qv2223,VsB_0004,VuB_0812);
build EndPacket;
}
# (v60,1) "if (Qv4) Vx.h-=Vu.h"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 1 1 x x x x x
define pcodeop condnac_QVhVh;
:accum^".if("^qv2223^")-=" VsH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x7 & qv2223 & Vd5 & VsH_0004 & VuH_0812 & $(END_PACKET) {
Vd5 = condnac_QVhVh(qv2223,VsH_0004,VuH_0812);
build EndPacket;
}
# (v60,1) "if (!Qv4) Vx.h-=Vu.h"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 1 0 x x x x x
:accum^".if(!"^qv2223^")-=" VsH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0507=0x2 & qv2223 & Vd5 & VsH_0004 & VuH_0812 & $(END_PACKET) {
Vd5 = condnac_QVhVh(~qv2223,VsH_0004,VuH_0812);
build EndPacket;
}
# (v60,1) "if (Qv4) Vx.w-=Vu.w"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 0 0 x x x x x
define pcodeop condnac_QVwVw;
:accum^".if("^qv2223^")-=" VsW_0004,VuW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0507=0x0 & qv2223 & Vd5 & VsW_0004 & VuW_0812 & $(END_PACKET) {
Vd5 = condnac_QVwVw(qv2223,VsW_0004,VuW_0812);
build EndPacket;
}
# (v60,1) "if (!Qv4) Vx.w-=Vu.w"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 1 1 x x x x x
:accum^".if(!"^qv2223^")-=" VsW_0004,VuW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0507=0x3 & qv2223 & Vd5 & VsW_0004 & VuW_0812 & $(END_PACKET) {
Vd5 = condnac_QVwVw(~qv2223,VsW_0004,VuW_0812);
build EndPacket;
}
# (v60,1) vmux -- "Vd=vmux(Qt4,Vu,Vv)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 1 1 1 v v v v v P P 1 u u u u u - t t d d d d d
define pcodeop vmux_QVV;
:vmux Vd5,qv0506,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x77 & op13=0x1 & Vd5 & qv0506 & Vu_0812 & Vv_1620 & $(END_PACKET) {
Vd5 = vmux_QVV(qv0506,Vu_0812,Vv_1620);
build EndPacket;
}
# (v60,1) vsatdw -- "Vd.w=vsatdw(Vu.w,Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 1 1 0 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d
define pcodeop vsatdw_VwVw;
:vsatdw VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x6c & op13=0x1 & op0507=0x7 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) {
VdW_0004 = vsatdw_VwVw(VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vsat -- "Vd.uh=vsat(Vu.uw,Vv.uw)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d
define pcodeop Vuh_vsat_VuwVuw;
:vsat VdUH_0004,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x6 & VdUH_0004 & VuUW_0812 & VvUW_1620 & $(END_PACKET) {
VdUH_0004 = Vuh_vsat_VuwVuw(VuUW_0812,VvUW_1620);
build EndPacket;
}
# (v60,1) vsat -- "Vd.ub=vsat(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d
define pcodeop Vub_vsat_VhVh;
:vsat VdUB_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x2 & VdUB_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdUB_0004 = Vub_vsat_VhVh(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vsat -- "Vd.h=vsat(Vu.w,Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d
define pcodeop Vh_vsat_VwVw;
:vsat VdH_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x3 & VdH_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) {
VdH_0004 = Vh_vsat_VwVw(VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vshuffe -- "Vd.b=vshuffe(Vu.b,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d
define pcodeop vshuffe_VbVb;
:vshuffe VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x1 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) {
VdB_0004 = vshuffe_VbVb(VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vshuffo -- "Vd.b=vshuffo(Vu.b,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d
define pcodeop vshuffo_VbVb;
:vshuffo VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x2 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) {
VdB_0004 = vshuffo_VbVb(VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vshuffe -- "Vd.h=vshuffe(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d
define pcodeop vshuffe_VhVh;
:vshuffe VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x3 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdH_0004 = vshuffe_VhVh(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vshuffo -- "Vd.h=vshuffo(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d
define pcodeop vshuffo_VhVh;
:vshuffo VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x4 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdH_0004 = vshuffo_VhVh(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,9) vextract -- "Rd=vextract(Vu,Rs)"
# Solo instruction in packet
# Behavior: Rd = Vu.uw[ (Rs & (VWIDTH-1)) >> 2 ]
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 u u u u u 0 0 1 d d d d d
:vextract Rd5,vu5,rs5 EndPacket is iclass=0x9 & op2127=0x10 & op13=0x0 & op0507=0x1 & Rd5 & vu5 & VuBase_0812 & rs5 & $(END_PACKET) {
wordOff:4 = rs5 & $(HVX_VECTOR_WORD_MASK); # (Rs & (VWIDTH-1)) >> 2, kept as a byte offset
vptr:4 = VuBase_0812 + wordOff;
Rd5 = *[register]:4 vptr;
build EndPacket;
}
# (v60,2) vgather -- "vtmp.h=vgather(Rt,Mu,Vvv.w).h"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 0 1 0 - - - v v v v v
define pcodeop vgather_RMWw;
:vgather.h rx5,mu,VssW_0004 EndPacket is iclass=0x2 & op2127=0x78 & op0810=0x2 & rx5 & mu & VssW_0004 & Vd5tmp & $(END_PACKET) {
Vd5tmp = vgather_RMWw(rx5,mu,VssW_0004);
build EndPacket;
}
# (v60,2) vgather -- "if (Qs4) vtmp.h=vgather(Rt,Mu,Vvv.w).h"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 1 1 0 - s s v v v v v
define pcodeop vgather_QRMWw;
:vgather.h^".if("^qv0506^")" rx5,mu,VssW_0004 EndPacket is iclass=0x2 & op2127=0x78 & op0810=0x6 & qv0506 & rx5 & mu & VssW_0004 & Vd5tmp & $(END_PACKET) {
Vd5tmp = vgather_QRMWw(qv0506,rx5,mu,VssW_0004); # conditional handled within vgatherIf function
build EndPacket;
}
# (v60,2) vgather -- "vtmp.w=vgather(Rt,Mu,Vv.w).w"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 0 0 0 - - - v v v v v
define pcodeop vgather_RMVw;
:vgather.w rx5,mu,VsW_0004 EndPacket is iclass=0x2 & op2127=0x78 & op0810=0x0 & rx5 & mu & VsW_0004 & Vd5tmp & $(END_PACKET) {
Vd5tmp = vgather_RMVw(rx5,mu,VsW_0004);
build EndPacket;
}
# (v60,2) vgather -- "vtmp.h=vgather(Rt,Mu,Vv.h).h"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 0 0 1 - - - v v v v v
define pcodeop vgather_RMVh;
:vgather.h rx5,mu,VsH_0004 EndPacket is iclass=0x2 & op2127=0x78 & op0810=0x1 & rx5 & mu & VsH_0004 & Vd5tmp & $(END_PACKET) {
Vd5tmp = vgather_RMVh(rx5,mu,VsH_0004);
build EndPacket;
}
# (v60,2) vgather -- "if (Qs4) vtmp.w=vgather(Rt,Mu,Vv.w).w"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 1 0 0 - s s v v v v v
# NOTES:
# - Rt identifies a memory source area to be gathered into temp vector
# - Mu identifies length-1 of memory region in bytes
# - Vv.w or Vv.h identifies bytes offsets into the memory region
# - vgather must be paired with vmem Vtmp.new store
define pcodeop vgather_QRMVw;
:vgather.w^".if("^qv0506^")" rx5,mu,VsW_0004 EndPacket is iclass=0x2 & op2127=0x78 & op0810=0x4 & qv0506 & rx5 & mu & VsW_0004 & Vd5tmp & $(END_PACKET) {
Vd5tmp = vgather_QRMVw(qv0506,rx5,mu,VsW_0004); # conditional handled within vgatherIf function
build EndPacket;
}
# (v60,2) vgather -- "if (Qs4) vtmp.h=vgather(Rt,Mu,Vv.h).h"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 1 0 1 - s s v v v v v
define pcodeop vgather_QRMVh;
:vgather.h^".if("^qv0506^")" rx5,mu,VsH_0004 EndPacket is iclass=0x2 & op2127=0x78 & op0810=0x5 & qv0506 & rx5 & mu & VsH_0004 & Vd5tmp & $(END_PACKET) {
Vd5tmp = vgather_QRMVh(qv0506,rx5,mu,VsH_0004); # conditional handled within vgatherIf function
build EndPacket;
}
# (v60,2) vmem -- "Vd=vmem(Rt+#s4)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 0 0 0 d d d d d
#
# (v60,2) vmem -- "Vd=vmem(Rt+#s4):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 0 1 0 t t t t t P P i 0 0 i i i 0 0 0 d d d d d
:vmem^ntHint22 Vd5,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op2327=0x10 & op21=0 & op1112=0x0 & op0507=0x0 & ntHint22 & Vd5 & VAlignMemAddrRxS4 & $(END_PACKET) [ cond=0; ] {
Vd5 = VAlignMemAddrRxS4; # Vd5 handles forwarding commit
build EndPacket;
}
# (v60,2) vmem -- "if (Pv) Vd=vmem(Rt+#s4)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 1 0 d d d d d
#
# (v60,2) vmem -- "if (!Pv) Vd=vmem(Rt+#s4)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 1 1 d d d d d
#
# (v60,2) vmem -- "if (Pv) Vd=vmem(Rt+#s4):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 1 0 d d d d d
#
# (v60,2) vmem -- "if (!Pv) Vd=vmem(Rt+#s4):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 1 1 d d d d d
:vmem^VPuCond1112_S05^ntHint22 vd5,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op2327=0x11 & op21=0 & op0607=0x1 & VPuCond1112_S05 & ntHint22 & vd5 & vd5_ & SetVNRegVd5 & VAlignMemAddrRxS4 & $(END_PACKET) {
build VPuCond1112_S05;
build VAlignMemAddrRxS4;
build EndPacket;
<<EXEC_COND>>
build VPuCond1112_S05;
if (ConditionReg == 0) goto <skip>;
vd5_ = VAlignMemAddrRxS4;
<skip>
<<COMMIT_COND>>
build VPuCond1112_S05;
if (ConditionReg == 0) goto <nocommit>;
vd5 = vd5_;
<nocommit>
}
# (v60,2) vmem -- "Vd=vmem(Rx++#s3)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 0 0 0 d d d d d
#
# (v60,2) vmem -- "Vd=vmem(Rx++#s3):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 0 1 0 x x x x x P P - 0 0 i i i 0 0 0 d d d d d
:vmem^ntHint22 Vd5,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op2327=0x12 & op21=0 & op1112=0x0 & op0507=0x0 & ntHint22 & Vd5 & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=0; ] {
Vd5 = VAlignMemAddrRxAIS3; # Vd5 handles forwarding commit
build EndPacket;
}
# (v60,2) vmem -- "if (Pv) Vd=vmem(Rx++#s3)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 1 0 d d d d d
#
# (v60,2) vmem -- "if (!Pv) Vd=vmem(Rx++#s3)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 1 1 d d d d d
#
# (v60,2) vmem -- "if (Pv) Vd=vmem(Rx++#s3):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 1 0 d d d d d
#
# (v60,2) vmem -- "if (!Pv) Vd=vmem(Rx++#s3):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 1 1 d d d d d
:vmem^VPuCond1112_S05^ntHint22 vd5,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op2327=0x13 & op21=0 & op0607=0x1 & VPuCond1112_S05 & ntHint22 & vd5 & vd5_ & SetVNRegVd5 & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=1; ] {
build VPuCond1112_S05;
build VAlignMemAddrRxAIS3;
build EndPacket;
<<EXEC_COND>>
build VPuCond1112_S05;
build VAlignMemAddrRxAIS3;
if (ConditionReg == 0) goto <skip>;
vd5_ = VAlignMemAddrRxAIS3;
<skip>
<<COMMIT_COND>>
build VPuCond1112_S05; # set ConditionReg before any conditional commit below
build VAlignMemAddrRxAIS3; # conditional Rx post-increment
if (ConditionReg == 0) goto <nocommit>;
vd5 = vd5_;
<nocommit>
}
# (v60,2) vmem -- "Vd=vmem(Rx++Mu)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 0 0 0 d d d d d
#
# (v60,2) vmem -- "Vd=vmem(Rx++Mu):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 0 1 0 x x x x x P P u 0 0 - - - 0 0 0 d d d d d
:vmem^ntHint22 Vd5,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op2327=0x16 & op21=0 & op1112=0x0 & op0507=0x0 & ntHint22 & Vd5 & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=0; ] {
Vd5 = VAlignMemAddrRxAIMu; # Vd5 handles forwarding commit
build EndPacket;
}
# (v60,2) vmem -- "if (Pv) Vd=vmem(Rx++Mu)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 1 0 d d d d d
#
# (v60,2) vmem -- "if (!Pv) Vd=vmem(Rx++Mu)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 1 1 d d d d d
#
# (v60,2) vmem -- "if (Pv) Vd=vmem(Rx++Mu):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 1 0 d d d d d
#
# (v60,2) vmem -- "if (!Pv) Vd=vmem(Rx++Mu):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 1 1 d d d d d
:vmem^VPuCond1112_S05^ntHint22 vd5,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op2327=0x17 & op21=0 & op0607=0x1 & VPuCond1112_S05 & ntHint22 & vd5 & vd5_ & SetVNRegVd5 & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=1; ] {
build VPuCond1112_S05;
build VAlignMemAddrRxAIMu;
build EndPacket;
<<EXEC_COND>>
build VPuCond1112_S05;
build VAlignMemAddrRxAIMu;
if (ConditionReg == 0) goto <skip>;
vd5_ = VAlignMemAddrRxAIMu;
<skip>
<<COMMIT_COND>>
build VPuCond1112_S05;
build VAlignMemAddrRxAIMu; # conditionally commit Rx post-increment update
if (ConditionReg == 0) goto <nocommit>;
vd5 = vd5_;
<nocommit>
}
# (v60,2) vmem -- "Vd.cur=vmem(Rt+#s4)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 0 0 1 d d d d d
#
# (v60,2) vmem -- "Vd.cur=vmem(Rt+#s4):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 0 1 0 t t t t t P P i 0 0 i i i 0 0 1 d d d d d
:vmem^ntHint22 Vd5cur,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op2327=0x10 & op21=0 & op1112=0x0 & op0507=0x1 & ntHint22 & Vd5cur & VAlignMemAddrRxS4 & $(END_PACKET) [ cond = 0; ] {
Vd5cur = VAlignMemAddrRxS4;
build EndPacket;
}
# (v60,2) vmem -- "if (Pv) Vd.cur=vmem(Rt+#s4)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 0 0 d d d d d
#
# (v60,2) vmem -- "if (!Pv) Vd.cur=vmem(Rt+#s4)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 0 1 d d d d d
#
# (v60,2) vmem -- "if (Pv) Vd.cur=vmem(Rt+#s4):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 0 0 d d d d d
#
# (v60,2) vmem -- "if (!Pv) Vd.cur=vmem(Rt+#s4):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 0 1 d d d d d
:vmem^VPuCond1112_S05^ntHint22 Vd5cur,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op2327=0x11 & op21=0 & op0607=0x2 & VPuCond1112_S05 & ntHint22 & Vd5cur & VAlignMemAddrRxS4 & $(END_PACKET) [ cond=1; ] {
build VPuCond1112_S05;
build VAlignMemAddrRxS4;
build EndPacket;
<<EXEC_COND>>
build VPuCond1112_S05;
if (ConditionReg == 0) goto <skip>;
Vd5cur = VAlignMemAddrRxS4;
<skip>
}
# (v60,2) vmem -- "Vd.cur=vmem(Rx++#s3)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 0 0 1 d d d d d
#
# (v60,2) vmem -- "Vd.cur=vmem(Rx++#s3):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 0 1 0 x x x x x P P - 0 0 i i i 0 0 1 d d d d d
#
:vmem^ntHint22 Vd5cur,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op2327=0x12 & op21=0 & op1112=0x0 & op0507=0x1 & ntHint22 & Vd5cur & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=0; ] {
Vd5cur = VAlignMemAddrRxAIS3;
build EndPacket;
}
# (v60,2) vmem -- "if (Pv) Vd.cur=vmem(Rx++#s3)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 0 0 d d d d d
#
# (v60,2) vmem -- "if (!Pv) Vd.cur=vmem(Rx++#s3)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 0 1 d d d d d
#
# (v60,2) vmem -- "if (Pv) Vd.cur=vmem(Rx++#s3):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 0 0 d d d d d
#
# (v60,2) vmem -- "if (!Pv) Vd.cur=vmem(Rx++#s3):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 0 1 d d d d d
:vmem^VPuCond1112_S05^ntHint22 Vd5cur,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op2327=0x13 & op21=0 & op0607=0x2 & VPuCond1112_S05 & ntHint22 & Vd5cur & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=1; ] {
build VPuCond1112_S05;
build VAlignMemAddrRxAIS3;
build EndPacket;
<<EXEC_COND>>
build VPuCond1112_S05;
build VAlignMemAddrRxAIS3;
if (ConditionReg == 0) goto <skip>;
Vd5cur = VAlignMemAddrRxAIS3;
<skip>
<<COMMIT_COND>>
build VPuCond1112_S05;
build Vd5cur; # conditionally commit Vd
build VAlignMemAddrRxAIS3; # conditionally commit Rx post-increment update
}
# (v60,2) vmem -- "Vd.cur=vmem(Rx++Mu)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 0 0 1 d d d d d
#
# (v60,2) vmem -- "Vd.cur=vmem(Rx++Mu):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 0 1 0 x x x x x P P u 0 0 - - - 0 0 1 d d d d d
:vmem^ntHint22 Vd5cur,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op2327=0x16 & op21=0 & op1112=0x0 & op0507=0x1 & ntHint22 & Vd5cur & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=0;] {
Vd5cur = VAlignMemAddrRxAIMu;
build EndPacket;
}
# (v60,2) vmem -- "if (Pv) Vd.cur=vmem(Rx++Mu)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 0 0 d d d d d
#
# (v60,2) vmem -- "if (!Pv) Vd.cur=vmem(Rx++Mu)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 0 1 d d d d d
#
# (v60,2) vmem -- "if (Pv) Vd.cur=vmem(Rx++Mu):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 0 0 d d d d d
#
# (v60,2) vmem -- "if (!Pv) Vd.cur=vmem(Rx++Mu):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 0 1 d d d d d
:vmem^VPuCond1112_S05^ntHint22 Vd5cur,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op2327=0x17 & op21=0 & op0607=0x2 & VPuCond1112_S05 & ntHint22 & Vd5cur & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=1; ] {
build VPuCond1112_S05;
build VAlignMemAddrRxAIMu;
build EndPacket;
<<EXEC_COND>>
build VPuCond1112_S05;
build VAlignMemAddrRxAIMu;
if (ConditionReg == 0) goto <skip>;
Vd5cur = VAlignMemAddrRxAIMu;
<skip>
<<COMMIT_COND>>
build VPuCond1112_S05;
build Vd5cur; # conditionally commit Vd
build VAlignMemAddrRxAIMu; # conditionally commit Rx post-increment update
}
# (v60,2) vmem -- "Vd.tmp=vmem(Rt+#s4)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 0 1 0 d d d d d
#
# (v60,2) vmem -- "Vd.tmp=vmem(Rt+#s4):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 0 1 0 t t t t t P P i 0 0 i i i 0 1 0 d d d d d
:vmem^ntHint22 Vd5tmp,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op2327=0x10 & op21=0 & op1112=0x0 & op0507=0x2 & ntHint22 & Vd5tmp & VAlignMemAddrRxS4 & $(END_PACKET) {
Vd5tmp = VAlignMemAddrRxS4;
build EndPacket;
}
# (v60,2) vmem -- "if (Pv) Vd.tmp=vmem(Rt+#s4)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 1 0 d d d d d
#
# (v60,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rt+#s4)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 1 1 d d d d d
#
# (v60,2) vmem -- "if (Pv) Vd.tmp=vmem(Rt+#s4):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 1 0 d d d d d
# (v60,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rt+#s4):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 1 1 d d d d d
:vmem^VPuCond1112_S05^ntHint22 Vd5tmp,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op2327=0x11 & op21=0 & op0607=0x3 & VPuCond1112_S05 & ntHint22 & Vd5tmp & VAlignMemAddrRxS4 & $(END_PACKET) {
build VPuCond1112_S05;
build VAlignMemAddrRxS4;
build EndPacket;
<<EXEC_COND>>
build VPuCond1112_S05;
if (ConditionReg == 0) goto <skip>;
Vd5tmp = VAlignMemAddrRxS4;
<skip>
}
# (v60,2) vmem -- "Vd.tmp=vmem(Rx++#s3)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 0 1 0 d d d d d
#
# (v60,2) vmem -- "Vd.tmp=vmem(Rx++#s3):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 0 1 0 x x x x x P P - 0 0 i i i 0 1 0 d d d d d
:vmem^ntHint22 Vd5tmp,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op2327=0x12 & op21=0 & op1112=0x0 & op0507=0x2 & ntHint22 & Vd5tmp & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=0; ] {
Vd5tmp = VAlignMemAddrRxAIS3;
build EndPacket;
}
# (v60,2) vmem -- "if (Pv) Vd.tmp=vmem(Rx++#s3)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 1 0 d d d d d
#
# (v60,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rx++#s3)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 1 1 d d d d d
#
# (v60,2) vmem -- "if (Pv) Vd.tmp=vmem(Rx++#s3):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 1 0 d d d d d
#
# (v60,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rx++#s3):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 1 1 d d d d d
:vmem^VPuCond1112_S05^ntHint22 Vd5tmp,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op2327=0x13 & op21=0 & op0607=0x3 & VPuCond1112_S05 & ntHint22 & Vd5tmp & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=1; ] {
build VPuCond1112_S05;
build VAlignMemAddrRxAIS3;
build EndPacket;
<<EXEC_COND>>
build VPuCond1112_S05;
build VAlignMemAddrRxAIS3;
if (ConditionReg == 0) goto <skip>;
Vd5tmp = VAlignMemAddrRxAIS3;
<skip>
<<COMMIT_COND>>
build VPuCond1112_S05;
build VAlignMemAddrRxAIS3; # conditionally commit Rx post-increment update
}
# (v60,2) vmem -- "Vd.tmp=vmem(Rx++Mu)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 0 1 0 d d d d d
#
# (v60,2) vmem -- "Vd.tmp=vmem(Rx++Mu):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 0 1 0 x x x x x P P u 0 0 - - - 0 1 0 d d d d d
:vmem^ntHint22 Vd5tmp,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op2327=0x16 & op21=0 & op1112=0x0 & op0507=0x2 & ntHint22 & Vd5tmp & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=0; ] {
Vd5tmp = VAlignMemAddrRxAIMu;
build EndPacket;
}
# (v60,2) vmem -- "if (Pv) Vd.tmp=vmem(Rx++Mu)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 1 0 d d d d d
#
# (v60,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rx++Mu)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 1 1 d d d d d
#
# (v60,2) vmem -- "if (Pv) Vd.tmp=vmem(Rx++Mu):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 1 0 d d d d d
#
# (v60,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rx++Mu):nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 1 1 d d d d d
:vmem^VPuCond1112_S05^ntHint22 Vd5tmp,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op2327=0x17 & op21=0 & op0607=0x3 & VPuCond1112_S05 & ntHint22 & Vd5tmp & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=1; ] {
build VPuCond1112_S05;
build VAlignMemAddrRxAIMu;
build EndPacket;
<<EXEC_COND>>
build VPuCond1112_S05;
build VAlignMemAddrRxAIMu;
if (ConditionReg == 0) goto <skip>;
Vd5tmp = VAlignMemAddrRxAIMu;
<skip>
<<COMMIT_COND>>
build VPuCond1112_S05;
build VAlignMemAddrRxAIMu; # conditionally commit Rx post-increment update
}
# (v60,2) vmemu -- "Vd=vmemu(Rt+#s4)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 1 1 1 d d d d d
:vmemu Vd5,VMemAddrRxS4 EndPacket is iclass=0x2 & op2127=0x40 & op1112=0x0 & op0507=0x7 & Vd5 & VMemAddrRxS4 & $(END_PACKET) {
Vd5 = VMemAddrRxS4; # Vd5 handles forwarding commit
build EndPacket;
}
# (v60,2) vmemu -- "Vd=vmemu(Rx++#s3)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 1 1 1 d d d d d
:vmemu Vd5,VMemAddrRxAIS3 EndPacket is iclass=0x2 & op2127=0x48 & op1112=0x0 & op0507=0x7 & Vd5 & VMemAddrRxAIS3 & $(END_PACKET) [ cond=0; ] {
Vd5 = VMemAddrRxAIS3; # Vd5 handles forwarding commit
build EndPacket;
}
# (v60,2) vmemu -- "Vd=vmemu(Rx++Mu)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 1 1 1 d d d d d
:vmemu Vd5,VMemAddrRxAIMu EndPacket is iclass=0x2 & op2127=0x58 & op1112=0x0 & op0507=0x7 & Vd5 & VMemAddrRxAIMu & $(END_PACKET) [ cond=0; ] {
Vd5 = VMemAddrRxAIMu; # Vd5 handles forwarding commit
build EndPacket;
}
# (v60,1) v6mpy -- "Vxx.w+=v6mpy(Vuu.ub,Vvv.b,#u2):v"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 1 u u u u u 0 i i x x x x x
define pcodeop Ww_v6mpyacc_WwWubWbI_v;
:v6mpy+=^":v" VddW_0004,VuuUB_0812,VvvB_1620,Uimm2_0506 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x1 & op7=0x0 & Vss_0004 & VddW_0004 & VuuUB_0812 & VvvB_1620 & Uimm2_0506 & $(END_PACKET) {
VddW_0004 = Ww_v6mpyacc_WwWubWbI_v(Vss_0004,VuuUB_0812,VvvB_1620,Uimm2_0506);
build EndPacket;
}
# (v60,1) v6mpy -- "Vxx.w+=v6mpy(Vuu.ub,Vvv.b,#u2):h"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 1 u u u u u 1 i i x x x x x
define pcodeop Ww_v6mpyacc_WwWubWbI_h;
:v6mpy+=^":h" VddW_0004,VuuUB_0812,VvvB_1620,Uimm2_0506 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x1 & op7=0x1 & Vss_0004 & VddW_0004 & VuuUB_0812 & VvvB_1620 & Uimm2_0506 & $(END_PACKET) {
VddW_0004 = Ww_v6mpyacc_WwWubWbI_h(Vss_0004,VuuUB_0812,VvvB_1620,Uimm2_0506);
build EndPacket;
}
# (v60,1) v6mpy -- "Vdd.w=v6mpy(Vuu.ub,Vvv.b,#u2):v"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 1 u u u u u 0 i i d d d d d
define pcodeop Ww_v6mpy_WubWbI_v;
:v6mpy^":v" VddW_0004,VuuUB_0812,VvvB_1620,Uimm2_0506 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x1 & op7=0x0 & VddW_0004 & VuuUB_0812 & VvvB_1620 & Uimm2_0506 & $(END_PACKET) {
VddW_0004 = Ww_v6mpy_WubWbI_v(VuuUB_0812,VvvB_1620,Uimm2_0506);
build EndPacket;
}
# (v60,1) v6mpy -- "Vdd.w=v6mpy(Vuu.ub,Vvv.b,#u2):h"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 1 u u u u u 1 i i d d d d d
define pcodeop Ww_v6mpy_WubWbI_h;
:v6mpy^":h" VddW_0004,VuuUB_0812,VvvB_1620,Uimm2_0506 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x1 & op7=0x1 & VddW_0004 & VuuUB_0812 & VvvB_1620 & Uimm2_0506 & $(END_PACKET) {
VddW_0004 = Ww_v6mpy_WubWbI_h(VuuUB_0812,VvvB_1620,Uimm2_0506);
build EndPacket;
}
# (v60,1) vadd -- "Vxx.w+=vadd(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 0 1 0 x x x x x
define pcodeop Ww_vaddacc_WwVhVh;
:vadd+= VddW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x2 & Vss_0004 & VddW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VddW_0004 = Ww_vaddacc_WwVhVh(Vss_0004,VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vxx.w+=vadd(Vu.uh,Vv.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 1 0 0 x x x x x
define pcodeop Ww_vaddacc_WwVuhVuh;
:vadd+= VddW_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x1 & op0507=0x4 & Vss_0004 & VddW_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) {
VddW_0004 = Ww_vaddacc_WwVuhVuh(Vss_0004,VuUH_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vxx.h+=vadd(Vu.ub,Vv.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 1 0 1 x x x x x
define pcodeop Wh_vaddacc_WhVubVub;
:vadd+= VddH_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x1 & op0507=0x5 & Vss_0004 & VddH_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) {
VddH_0004 = Wh_vaddacc_WhVubVub(Vss_0004,VuUB_0812,VvUB_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vdd.h=vadd(Vu.ub,Vv.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d
define pcodeop Wh_vadd_VubVub;
:vadd VddH_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x2 & VddH_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) {
VddH_0004 = Wh_vadd_VubVub(VuUB_0812,VvUB_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vdd.w=vadd(Vu.uh,Vv.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d
define pcodeop Ww_vadd_VuhVuh;
:vadd VddW_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x3 & VddW_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) {
VddW_0004 = Ww_vadd_VuhVuh(VuUH_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vdd.w=vadd(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d
define pcodeop Ww_vadd_VhVh;
:vadd VddW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x4 & VddW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VddW_0004 = Ww_vadd_VhVh(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vdd.h=vsub(Vu.ub,Vv.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d
define pcodeop Wh_vsub_VubVub;
:vsub VddH_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x5 & VddH_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) {
VddH_0004 = Wh_vsub_VubVub(VuUB_0812,VvUB_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vdd.w=vsub(Vu.uh,Vv.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d
define pcodeop Ww_vsub_VuhVuh;
:vsub VddW_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x6 & VddW_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) {
VddW_0004 = Ww_vsub_VuhVuh(VuUH_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vdd.w=vsub(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d
define pcodeop Ww_vsub_VhVh;
:vsub VddW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x7 & VddW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VddW_0004 = Ww_vsub_VhVh(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vdmpy -- "Vdd.h=vdmpy(Vuu.ub,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 1 1 d d d d d
define pcodeop Ww_vdmpy_WubRb;
:vdmpy VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x7 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) {
VddH_0004 = Ww_vdmpy_WubRb(VuuUB_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vdmpy -- "Vxx.h+=vdmpy(Vuu.ub,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 1 1 x x x x x
define pcodeop vdmpyacc_WhWubRb;
:vdmpy+= VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x7 & Vss_0004 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) {
VddH_0004 = vdmpyacc_WhWubRb(Vss_0004,VuuUB_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vdmpy -- "Vd.w=vdmpy(Vuu.h,Rt.uh,#1):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 0 1 d d d d d
define pcodeop Vw_vdmpy_WhRuh_sat;
:vdmpy^":sat" VdW_0004,VuuH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x1 & VdW_0004 & VuuH_0812 & RtUH_1620 & $(END_PACKET) {
VdW_0004 = Vw_vdmpy_WhRuh_sat(VuuH_0812,RtUH_1620);
build EndPacket;
}
# (v60,1) vdmpy -- "Vd.w=vdmpy(Vuu.h,Rt.h):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 1 1 d d d d d
define pcodeop Vw_vdmpy_WhRh_sat;
:vdmpy^":sat" VdW_0004,VuuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x3 & VdW_0004 & VuuH_0812 & RtH_1620 & $(END_PACKET) {
VdW_0004 = Vw_vdmpy_WhRh_sat(VuuH_0812,RtH_1620);
build EndPacket;
}
# (v60,1) vdmpy -- "Vdd.w=vdmpy(Vuu.h,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 0 0 d d d d d
define pcodeop Ww_vdmpy_WhRb;
:vdmpy VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x4 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) {
VddW_0004 = Ww_vdmpy_WhRb(VuuH_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vdmpy -- "Vx.w+=vdmpy(Vuu.h,Rt.uh,#1):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 0 1 x x x x x
define pcodeop vdmpyacc_VwWhRuh_sat;
:vdmpy+=^":sat" VdW_0004,VuuH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x1 & vs5 & VdW_0004 & VuuH_0812 & RtUH_1620 & $(END_PACKET) {
VdW_0004 = vdmpyacc_VwWhRuh_sat(vs5,VuuH_0812,RtUH_1620);
build EndPacket;
}
# (v60,1) vdmpy -- "Vx.w+=vdmpy(Vuu.h,Rt.h):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 1 0 x x x x x
define pcodeop vdmpyacc_VwWhRh_sat;
:vdmpy+=^":sat" VdW_0004,VuuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x2 & vs5 & VdW_0004 & VuuH_0812 & RtH_1620 & $(END_PACKET) {
VdW_0004 = vdmpyacc_VwWhRh_sat(vs5,VuuH_0812,RtH_1620);
build EndPacket;
}
# (v60,1) vdmpy -- "Vxx.w+=vdmpy(Vuu.h,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 0 0 x x x x x
define pcodeop vdmpyacc_WwWhRb;
:vdmpy+= VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x4 & Vss_0004 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) {
VddW_0004 = vdmpyacc_WwWhRb(Vss_0004,VuuH_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vdmpy -- "Vx.w+=vdmpy(Vu.h,Vv.h):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 1 1 x x x x x
define pcodeop vdmpyacc_VwVhVh_sat;
:vdmpy+=^":sat" VdW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x3 & vs5 & VdW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdW_0004 = vdmpyacc_VwVhVh_sat(vs5,VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vlut4 -- "Vd.h=vlut4(Vu.uh,Rtt.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 0 0 d d d d d
define pcodeop vlut4_VuhPh;
:vlut4 VdH_0004,VuUH_0812,RttH_1620 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x4 & VdH_0004 & VuUH_0812 & RttH_1620 & $(END_PACKET) {
VdH_0004 = vlut4_VuhPh(VuUH_0812,RttH_1620);
build EndPacket;
}
# (v60,1) vmpa -- "Vx.h=vmpa(Vx.h,Vu.h,Rtt.h):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 0 0 x x x x x
define pcodeop vmpa_VhVhVhPh_sat;
:vmpa^":sat" VdH_0004,VsH_0004,VuH_0812,RttH_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x4 & VdH_0004 & VsH_0004 & VuH_0812 & RttH_1620 & $(END_PACKET) {
VdH_0004 = vmpa_VhVhVhPh_sat(VsH_0004,VuH_0812,RttH_1620);
build EndPacket;
}
# (v60,1) vmpa -- "Vx.h=vmpa(Vx.h,Vu.uh,Rtt.uh):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 0 1 x x x x x
define pcodeop vmpa_VhVhVuhPuh_sat;
:vmpa^":sat" VdH_0004,VsH_0004,VuUH_0812,RttUH_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x5 & VdH_0004 & VsH_0004 & VuUH_0812 & RttUH_1620 & $(END_PACKET) {
VdH_0004 = vmpa_VhVhVuhPuh_sat(VsH_0004,VuUH_0812,RttUH_1620);
build EndPacket;
}
# (v60,1) vmps -- "Vx.h=vmps(Vx.h,Vu.uh,Rtt.uh):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 1 0 x x x x x
define pcodeop vmps_VhVhVuhPuh_sat;
:vmps^":sat" VdH_0004,VsH_0004,VuUH_0812,RttUH_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x6 & VdH_0004 & VsH_0004 & VuUH_0812 & RttUH_1620 & $(END_PACKET) {
VdH_0004 = vmps_VhVhVuhPuh_sat(VsH_0004,VuUH_0812,RttUH_1620);
build EndPacket;
}
# (v60,1) vmpa -- "Vdd.h=vmpa(Vuu.ub,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 1 0 d d d d d
define pcodeop vmpa_WubRb;
:vmpa VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x6 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) {
VddH_0004 = vmpa_WubRb(VuuUB_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vmpa -- "Vdd.w=vmpa(Vuu.h,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 1 1 d d d d d
define pcodeop vmpa_WhRb;
:vmpa VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x7 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) {
VddW_0004 = vmpa_WhRb(VuuH_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vmpa -- "Vxx.h+=vmpa(Vuu.ub,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 1 0 x x x x x
define pcodeop vmpaacc_WhWubRb;
:vmpa+= VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x6 & Vss_0004 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) {
VddH_0004 = vmpaacc_WhWubRb(Vss_0004,VuuUB_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vmpa -- "Vxx.w+=vmpa(Vuu.h,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 1 1 x x x x x
define pcodeop vmpaacc_WwWhRb;
:vmpa+= VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x7 & Vss_0004 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) {
VddW_0004 = vmpaacc_WwWhRb(Vss_0004,VuuH_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vmpa -- "Vdd.h=vmpa(Vuu.ub,Rt.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 1 1 d d d d d
define pcodeop vmpa_WubRub;
:vmpa VddH_0004,VuuUB_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x3 & VddH_0004 & VuuUB_0812 & RtUB_1620 & $(END_PACKET) {
VddH_0004 = vmpa_WubRub(VuuUB_0812,RtUB_1620);
build EndPacket;
}
# (v60,1) vmpa -- "Vdd.w=vmpa(Vuu.uh,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 1 0 1 d d d d d
define pcodeop vmpa_WuhRb;
:vmpa VddW_0004,VuuUH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x0 & op0507=0x5 & VddW_0004 & VuuUH_0812 & RtB_1620 & $(END_PACKET) {
VddW_0004 = vmpa_WuhRb(VuuUH_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vmpa -- "Vxx.w+=vmpa(Vuu.uh,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 1 0 x x x x x
define pcodeop vmpaacc_WwWuhRb;
:vmpa+= VddW_0004,VuuUH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x2 & Vss_0004 & VddW_0004 & VuuUH_0812 & RtB_1620 & $(END_PACKET) {
VddW_0004 = vmpaacc_WwWuhRb(Vss_0004,VuuUH_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vmpa -- "Vxx.h+=vmpa(Vuu.ub,Rt.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 u u u u u 1 0 0 x x x x x
define pcodeop vmpaacc_WhWubRub;
:vmpa+= VddH_0004,VuuUB_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x1 & op0507=0x4 & Vss_0004 & VddH_0004 & VuuUB_0812 & RtUB_1620 & $(END_PACKET) {
VddH_0004 = vmpaacc_WhWubRub(Vss_0004,VuuUB_0812,RtUB_1620);
build EndPacket;
}
# (v60,1) vmpa -- "Vdd.h=vmpa(Vuu.ub,Vvv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d
define pcodeop vmpa_WubWb;
:vmpa VddH_0004,VuuUB_0812,VvvB_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x0 & op0507=0x3 & VddH_0004 & VuuUB_0812 & VvvB_1620 & $(END_PACKET) {
VddH_0004 = vmpa_WubWb(VuuUB_0812,VvvB_1620);
build EndPacket;
}
# (v60,1) vmpa -- "Vdd.h=vmpa(Vuu.ub,Vvv.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d
define pcodeop vmpa_WubWub;
:vmpa VddH_0004,VuuUB_0812,VvvUB_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x7 & VddH_0004 & VuuUB_0812 & VvvUB_1620 & $(END_PACKET) {
VddH_0004 = vmpa_WubWub(VuuUB_0812,VvvUB_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vdd.h=vmpy(Vu.ub,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 0 1 d d d d d
define pcodeop vmpy_VubRb;
:vmpy VddH_0004,VuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x5 & VddH_0004 & VuUB_0812 & RtB_1620 & $(END_PACKET) {
VddH_0004 = vmpy_VubRb(VuUB_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vxx.h+=vmpy(Vu.ub,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 0 1 x x x x x
define pcodeop vmpyacc_WhVubRb;
:vmpy+= VddH_0004,VuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x5 & Vss_0004 & VddH_0004 & VuUB_0812 & RtB_1620 & $(END_PACKET) {
VddH_0004 = vmpyacc_WhVubRb(Vss_0004,VuUB_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vdd.w=vmpy(Vu.h,Rt.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d
define pcodeop vmpy_VhRh;
:vmpy VddW_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x0 & op0507=0x0 & VddW_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) {
VddW_0004 = vmpy_VhRh(VuH_0812,RtH_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vdd.uw=vmpy(Vu.uh,Rt.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 1 1 d d d d d
define pcodeop vmpy_VuhRuh;
:vmpy VddUW_0004,VuUH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x0 & op0507=0x3 & VddUW_0004 & VuUH_0812 & RtUH_1620 & $(END_PACKET) {
VddUW_0004 = vmpy_VuhRuh(VuUH_0812,RtUH_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vxx.w+=vmpy(Vu.h,Rt.h):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 0 0 x x x x x
define pcodeop vmpyacc_WwVhRh_sat;
:vmpy+=^":sat" VddW_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0507=0x0 & Vss_0004 & VddW_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) {
VddW_0004 = vmpyacc_WwVhRh_sat(Vss_0004,VuH_0812,RtH_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vxx.uw+=vmpy(Vu.uh,Rt.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 0 1 x x x x x
define pcodeop vmpyacc_WuwVuhRuh;
:vmpy+= VddUW_0004,VuUH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0507=0x1 & Vss_0004 & VddUW_0004 & VuUH_0812 & RtUH_1620 & $(END_PACKET) {
VddUW_0004 = vmpyacc_WuwVuhRuh(Vss_0004,VuUH_0812,RtUH_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vxx.uh+=vmpy(Vu.ub,Rt.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 0 0 x x x x x
define pcodeop vmpyacc_WuhVubRub;
:vmpy+= VddUH_0004,VuUB_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x0 & Vss_0004 & VddUH_0004 & VuUB_0812 & RtUB_1620 & $(END_PACKET) {
VddUH_0004 = vmpyacc_WuhVubRub(Vss_0004,VuUB_0812,RtUB_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vxx.w+=vmpy(Vu.h,Rt.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 u u u u u 1 1 0 x x x x x
define pcodeop vmpyacc_WwVhRh;
:vmpy+= VddW_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x1 & op0507=0x6 & Vss_0004 & VddW_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) {
VddW_0004 = vmpyacc_WwVhRh(Vss_0004,VuH_0812,RtH_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vdd.uh=vmpy(Vu.ub,Rt.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d
define pcodeop vmpy_VubRub;
:vmpy VddUH_0004,VuUB_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x4e & op13=0x0 & op0507=0x0 & VddUH_0004 & VuUB_0812 & RtUB_1620 & $(END_PACKET) {
VddUH_0004 = vmpy_VubRub(VuUB_0812,RtUB_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vdd.h=vmpy(Vu.b,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d
define pcodeop vmpy_VbVb;
:vmpy VddH_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x0 & op0507=0x4 & VddH_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) {
VddH_0004 = vmpy_VbVb(VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vdd.uh=vmpy(Vu.ub,Vv.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d
define pcodeop vmpy_VubVub;
:vmpy VddUH_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x0 & op0507=0x5 & VddUH_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) {
VddUH_0004 = vmpy_VubVub(VuUB_0812,VvUB_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vdd.h=vmpy(Vu.ub,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d
define pcodeop vmpy_VubVb;
:vmpy VddH_0004,VuUB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x0 & op0507=0x6 & VddH_0004 & VuUB_0812 & VvB_1620 & $(END_PACKET) {
VddH_0004 = vmpy_VubVb(VuUB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vxx.h+=vmpy(Vu.b,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 1 0 0 x x x x x
define pcodeop vmpyacc_WhVbVb;
:vmpy+= VddH_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x4 & Vss_0004 & VddH_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) {
VddH_0004 = vmpyacc_WhVbVb(Vss_0004,VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vxx.uh+=vmpy(Vu.ub,Vv.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 1 0 1 x x x x x
define pcodeop vmpyacc_WuhVubVub;
:vmpy+= VddUH_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x5 & Vss_0004 & VddUH_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) {
VddUH_0004 = vmpyacc_WuhVubVub(Vss_0004,VuUB_0812,VvUB_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vxx.h+=vmpy(Vu.ub,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 1 1 0 x x x x x
define pcodeop vmpyacc_WhVubVb;
:vmpy+= VddH_0004,VuUB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x6 & Vss_0004 & VddH_0004 & VuUB_0812 & VvB_1620 & $(END_PACKET) {
VddH_0004 = vmpyacc_WhVubVb(Vss_0004,VuUB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vdd.w=vmpy(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d
define pcodeop vmpy_VhVh;
:vmpy VddW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x0 & op0507=0x7 & VddW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VddW_0004 = vmpy_VhVh(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vxx.w+=vmpy(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 1 1 1 x x x x x
define pcodeop vmpyacc_WwVhVh;
:vmpy+= VddW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x7 & Vss_0004 & VddW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VddW_0004 = vmpyacc_WwVhVh(Vss_0004,VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vdd.w=vmpy(Vu.h,Vv.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d
define pcodeop vmpy_VhVuh;
:vmpy VddW_0004,VuH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x0 & op0507=0x2 & VddW_0004 & VuH_0812 & VvUH_1620 & $(END_PACKET) {
VddW_0004 = vmpy_VhVuh(VuH_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vxx.w+=vmpy(Vu.h,Vv.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 0 0 1 x x x x x
define pcodeop vmpyacc_WwVhVuh;
:vmpy+= VddW_0004,VuH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x1 & Vss_0004 & VddW_0004 & VuH_0812 & VvUH_1620 & $(END_PACKET) {
VddW_0004 = vmpyacc_WwVhVuh(Vss_0004,VuH_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vd.h=vmpy(Vu.h,Vv.h):<<1:rnd:sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d
define pcodeop vmpy_VhVh_rndsat;
:vmpy^":<<1:rnd:sat" VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x0 & op0507=0x1 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdH_0004 = vmpy_VhVh_rndsat(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vdd.uw=vmpy(Vu.uh,Vv.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d
define pcodeop vmpy_VuhVuh;
:vmpy VddUW_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x0 & op0507=0x0 & VddUW_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) {
VddUW_0004 = vmpy_VuhVuh(VuUH_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vxx.uw+=vmpy(Vu.uh,Vv.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 0 0 0 x x x x x
define pcodeop vmpyacc_WuwVuhVuh;
:vmpy+= VddUW_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x0 & Vss_0004 & VddUW_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) {
VddUW_0004 = vmpyacc_WuwVuhVuh(Vss_0004,VuUH_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vdd.qf32=vmpy(Vu.qf16,Vv.hf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 1 u u u u u 0 0 0 d d d d d
define pcodeop Wqf32_vmpy_Vqf16Vhf;
:vmpy VddQF32_0004,VuQF16_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x1 & op0507=0x0 & VddQF32_0004 & VuQF16_0812 & VvHF_1620 & $(END_PACKET) {
VddQF32_0004 = Wqf32_vmpy_Vqf16Vhf(VuQF16_0812,VvHF_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vd.qf16=vmpy(Vu.qf16,Vv.qf16)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 0 1 1 d d d d d
define pcodeop vmpy_Vqf16Vqf16;
:vmpy VdQF16_0004,VuQF16_0812,VvQF16_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x1 & op0507=0x3 & VdQF16_0004 & VuQF16_0812 & VvQF16_1620 & $(END_PACKET) {
VdQF16_0004 = vmpy_Vqf16Vqf16(VuQF16_0812,VvQF16_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vd.qf16=vmpy(Vu.hf,Vv.hf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 0 0 d d d d d
define pcodeop vmpy_VhfVhf;
:vmpy VdQF16_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x1 & op0507=0x4 & VdQF16_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) {
VdQF16_0004 = vmpy_VhfVhf(VuHF_0812,VvHF_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vd.qf16=vmpy(Vu.qf16,Vv.hf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 0 1 d d d d d
define pcodeop vmpy_Vqf16Vhf;
:vmpy VdQF16_0004,VuQF16_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x1 & op0507=0x5 & VdQF16_0004 & VuQF16_0812 & VvHF_1620 & $(END_PACKET) {
VdQF16_0004 = vmpy_Vqf16Vhf(VuQF16_0812,VvHF_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vdd.qf32=vmpy(Vu.qf16,Vv.qf16)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 1 0 d d d d d
define pcodeop Wqf32_vmpy_Vqf16Vqf16;
:vmpy VddQF32_0004,VuQF16_0812,VvQF16_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x1 & op0507=0x6 & VddQF32_0004 & VuQF16_0812 & VvQF16_1620 & $(END_PACKET) {
VddQF32_0004 = Wqf32_vmpy_Vqf16Vqf16(VuQF16_0812,VvQF16_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vdd.qf32=vmpy(Vu.hf,Vv.hf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 1 1 d d d d d
define pcodeop Wqf32_vmpy_VhfVhf;
:vmpy VddQF32_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x1 & op0507=0x7 & VddQF32_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) {
VddQF32_0004 = Wqf32_vmpy_VhfVhf(VuHF_0812,VvHF_1620);
build EndPacket;
}
# (v60,1) vmpyi -- "Vd.h=vmpyi(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d
define pcodeop vmpyi_VhVh;
:vmpyi VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x0 & op0507=0x4 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdH_0004 = vmpyi_VhVh(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vmpyi -- "Vx.h+=vmpyi(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 0 0 x x x x x
define pcodeop vmpyiacc_VhVhVh;
:vmpyi+= VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x4 & vs5 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdH_0004 = vmpyiacc_VhVhVh(vs5,VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vmpyie -- "Vx.w+=vmpyie(Vu.w,Vv.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 0 1 x x x x x
define pcodeop vmpyieacc_VwVwVuh;
:vmpyie+= VdW_0004,VuW_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x5 & vs5 & VdW_0004 & VuW_0812 & VvUH_1620 & $(END_PACKET) {
VdW_0004 = vmpyieacc_VwVwVuh(vs5,VuW_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vmpyie -- "Vx.w+=vmpyie(Vu.w,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 0 0 0 x x x x x
define pcodeop vmpyieacc_VwVwVh;
:vmpyie+= VdW_0004,VuW_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x1 & op0507=0x0 & vs5 & VdW_0004 & VuW_0812 & VvH_1620 & $(END_PACKET) {
VdW_0004 = vmpyieacc_VwVwVh(vs5,VuW_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vmpyie -- "Vd.w=vmpyie(Vu.w,Vv.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d
define pcodeop vmpyie_VwVuh;
:vmpyie VdW_0004,VuW_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x0 & VdW_0004 & VuW_0812 & VvUH_1620 & $(END_PACKET) {
VdW_0004 = vmpyie_VwVuh(VuW_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vmpyio -- "Vd.w=vmpyio(Vu.w,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d
define pcodeop vmpyio_VwVh;
:vmpyio VdW_0004,VuW_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x1 & VdW_0004 & VuW_0812 & VvH_1620 & $(END_PACKET) {
VdW_0004 = vmpyio_VwVh(VuW_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vmpyi -- "Vx.w+=vmpyi(Vu.w,Rt.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 1 1 x x x x x
define pcodeop vmpyiacc_VwVwRh;
:vmpyi+= VdW_0004,VuW_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0507=0x3 & vs5 & VdW_0004 & VuW_0812 & RtH_1620 & $(END_PACKET) {
VdW_0004 = vmpyiacc_VwVwRh(vs5,VuW_0812,RtH_1620);
build EndPacket;
}
# (v60,1) vmpyi -- "Vd.w=vmpyi(Vu.w,Rt.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 1 1 1 d d d d d
define pcodeop vmpyi_VwRh;
:vmpyi VdW_0004,VuW_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x0 & op0507=0x7 & VdW_0004 & VuW_0812 & RtH_1620 & $(END_PACKET) {
VdW_0004 = vmpyi_VwRh(VuW_0812,RtH_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vd.qf32=vmpy(Vu.qf32,Vv.qf32)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 0 0 0 d d d d d
define pcodeop vmpy_Vqf32Vqf32;
:vmpy VdQF32_0004,VuQF32_0812,VvQF32_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x1 & op0507=0x0 & VdQF32_0004 & VuQF32_0812 & VvQF32_1620 & $(END_PACKET) {
VdQF32_0004 = vmpy_Vqf32Vqf32(VuQF32_0812,VvQF32_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vd.qf32=vmpy(Vu.sf,Vv.sf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 0 0 1 d d d d d
define pcodeop vmpy_VsfVsf;
:vmpy VdQF32_0004,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x1 & op0507=0x1 & VdQF32_0004 & VuSF_0812 & VvSF_1620 & $(END_PACKET) {
VdQF32_0004 = vmpy_VsfVsf(VuSF_0812,VvSF_1620);
build EndPacket;
}
# (v60,1) vmpyo -- "Vxx+=vmpyo(Vu.w,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 0 1 1 x x x x x
define pcodeop vmpyoacc_WVwVh;
:vmpyo+= Vdd5,VuW_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x3 & Vss_0004 & Vdd5 & VuW_0812 & VvH_1620 & $(END_PACKET) {
Vdd5 = vmpyoacc_WVwVh(Vss_0004,VuW_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vmpyo -- "Vx.w+=vmpyo(Vu.w,Vv.h):<<1:sat:shift"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 1 0 x x x x x
define pcodeop vmpyoacc_VwVwVh_s1_sat_shift;
:vmpyo+=^":<<1:sat:shift" VdW_0004,VuW_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x6 & vs5 & VdW_0004 & VuW_0812 & VvH_1620 & $(END_PACKET) {
VdW_0004 = vmpyoacc_VwVwVh_s1_sat_shift(vs5,VuW_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vmpyo -- "Vx.w+=vmpyo(Vu.w,Vv.h):<<1:rnd:sat:shift"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 1 1 x x x x x
define pcodeop vmpyoacc_VwVwVh_s1_rnd_sat_shift;
:vmpyo+=^":<<1:rnd:sat:shift" VdW_0004,VuW_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x7 & vs5 & VdW_0004 & VuW_0812 & VvH_1620 & $(END_PACKET) {
VdW_0004 = vmpyoacc_VwVwVh_s1_rnd_sat_shift(vs5,VuW_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vmpye -- "Vdd=vmpye(Vu.w,Vv.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d
define pcodeop W_vmpye_VwVuh;
:vmpye Vdd5,VuW_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x6 & Vdd5 & VuW_0812 & VvUH_1620 & $(END_PACKET) {
Vdd5 = W_vmpye_VwVuh(VuW_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vmpyo -- "Vd.w=vmpyo(Vu.w,Vv.h):<<1:rnd:sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d
define pcodeop vmpyo_VwVh_s1_rnd_sat;
:vmpyo^":<<1:rnd:sat" VdW_0004,VuW_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x0 & VdW_0004 & VuW_0812 & VvH_1620 & $(END_PACKET) {
VdW_0004 = vmpyo_VwVh_s1_rnd_sat(VuW_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vmpye -- "Vd.w=vmpye(Vu.w,Vv.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d
define pcodeop vmpye_VwVuh;
:vmpye VdW_0004,VuW_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x0 & op0507=0x5 & VdW_0004 & VuW_0812 & VvUH_1620 & $(END_PACKET) {
VdW_0004 = vmpye_VwVuh(VuW_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vmpyo -- "Vd.w=vmpyo(Vu.w,Vv.h):<<1:sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d
define pcodeop vmpyo_VwVh_s1_sat;
:vmpyo^":<<1:sat" VdW_0004,VuW_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x0 & op0507=0x7 & VdW_0004 & VuW_0812 & VvH_1620 & $(END_PACKET) {
VdW_0004 = vmpyo_VwVh_s1_sat(VuW_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vrmpy -- "Vdd.w=vrmpy(Vuu.ub,Rt.b,#u1)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 1 0 i d d d d d
define pcodeop vrmpy_WubRbI;
:vrmpy VddW_0004,VuuUB_0812,RtB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x0 & op0607=0x2 & VddW_0004 & VuuUB_0812 & RtB_1620 & Uimm1_05 & $(END_PACKET) {
VddW_0004 = vrmpy_WubRbI(VuuUB_0812,RtB_1620,Uimm1_05);
build EndPacket;
}
# (v60,1) vrmpy -- "Vxx.w+=vrmpy(Vuu.ub,Rt.b,#u1)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 1 0 i x x x x x
define pcodeop vrmpyacc_WwWubRbI;
:vrmpy+= VddW_0004,VuuUB_0812,RtB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0607=0x2 & Vss_0004 & VddW_0004 & VuuUB_0812 & RtB_1620 & Uimm1_05 & $(END_PACKET) {
VddW_0004 = vrmpyacc_WwWubRbI(Vss_0004,VuuUB_0812,RtB_1620,Uimm1_05);
build EndPacket;
}
# (v60,1) vrmpy -- "Vxx.uw+=vrmpy(Vuu.ub,Rt.ub,#u1)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 1 1 i x x x x x
define pcodeop vrmpyacc_WuwWubRubI;
:vrmpy+= VddUW_0004,VuuUB_0812,RtUB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op0607=0x3 & Vss_0004 & VddUW_0004 & VuuUB_0812 & RtUB_1620 & Uimm1_05 & $(END_PACKET) {
VddUW_0004 = vrmpyacc_WuwWubRubI(Vss_0004,VuuUB_0812,RtUB_1620,Uimm1_05);
build EndPacket;
}
# (v60,1) vrmpy -- "Vdd.uw=vrmpy(Vuu.ub,Rt.ub,#u1)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 1 1 i d d d d d
define pcodeop vrmpy_WubRubI;
:vrmpy VddUW_0004,VuuUB_0812,RtUB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op0607=0x3 & VddUW_0004 & VuuUB_0812 & RtUB_1620 & Uimm1_05 & $(END_PACKET) {
VddUW_0004 = vrmpy_WubRubI(VuuUB_0812,RtUB_1620,Uimm1_05);
build EndPacket;
}
# (v60,1) vrmpy -- "Vx.uw+=vrmpy(Vu.ub,Vv.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 0 0 x x x x x
define pcodeop vrmpyacc_VuwVubVub;
:vrmpy+= VdUW_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x0 & vs5 & VdUW_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) {
VdUW_0004 = vrmpyacc_VuwVubVub(vs5,VuUB_0812,VvUB_1620);
build EndPacket;
}
# (v60,1) vrmpy -- "Vx.w+=vrmpy(Vu.b,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 0 1 x x x x x
define pcodeop vrmpyacc_VwVbVb;
:vrmpy+= VdW_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x1 & vs5 & VdW_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) {
VdW_0004 = vrmpyacc_VwVbVb(vs5,VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vrmpy -- "Vx.w+=vrmpy(Vu.ub,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 1 0 x x x x x
define pcodeop vrmpyacc_VwVubVb;
:vrmpy+= VdW_0004,VuUB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x2 & vs5 & VdW_0004 & VuUB_0812 & VvB_1620 & $(END_PACKET) {
VdW_0004 = vrmpyacc_VwVubVb(vs5,VuUB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vtmpy -- "Vdd.h=vtmpy(Vuu.b,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d
define pcodeop vtmpy_WbRb;
:vtmpy VddH_0004,VuuB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x0 & VddH_0004 & VuuB_0812 & RtB_1620 & $(END_PACKET) {
VddH_0004 = vtmpy_WbRb(VuuB_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vtmpy -- "Vdd.h=vtmpy(Vuu.ub,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 0 1 d d d d d
define pcodeop vtmpy_WubRb;
:vtmpy VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x1 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) {
VddH_0004 = vtmpy_WubRb(VuuUB_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vtmpy -- "Vxx.h+=vtmpy(Vuu.b,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 0 0 x x x x x
define pcodeop vtmpyacc_WhWbRb;
:vtmpy+= VddH_0004,VuuB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x0 & Vss_0004 & VddH_0004 & VuuB_0812 & RtB_1620 & $(END_PACKET) {
VddH_0004 = vtmpyacc_WhWbRb(Vss_0004,VuuB_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vtmpy -- "Vxx.h+=vtmpy(Vuu.ub,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 0 1 x x x x x
define pcodeop vtmpyacc_WhWubRb;
:vtmpy+= VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x1 & Vss_0004 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) {
VddH_0004 = vtmpyacc_WhWubRb(Vss_0004,VuuUB_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vtmpy -- "Vxx.w+=vtmpy(Vuu.h,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 1 0 x x x x x
define pcodeop vtmpyacc_WwWhRb;
:vtmpy+= VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x2 & Vss_0004 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) {
VddW_0004 = vtmpyacc_WwWhRb(Vss_0004,VuuH_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vtmpy -- "Vdd.w=vtmpy(Vuu.h,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 1 0 0 d d d d d
define pcodeop vtmpy_WhRb;
:vtmpy VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op0507=0x4 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) {
VddW_0004 = vtmpy_WhRb(VuuH_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vdsad -- "Vdd.uw=vdsad(Vuu.uh,Rt.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 0 1 d d d d d
define pcodeop vdsad_WuhRuh;
:vdsad VddUW_0004,VuuUH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x5 & VddUW_0004 & VuuUH_0812 & RtUH_1620 & $(END_PACKET) {
VddUW_0004 = vdsad_WuhRuh(VuuUH_0812,RtUH_1620);
build EndPacket;
}
# (v60,1) vdsad -- "Vxx.uw+=vdsad(Vuu.uh,Rt.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 0 0 0 x x x x x
define pcodeop vdsadacc_WuwWuhRuh;
:vdsad+= VddUW_0004,VuuUH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op0507=0x0 & Vss_0004 & VddUW_0004 & VuuUH_0812 & RtUH_1620 & $(END_PACKET) {
VddUW_0004 = vdsadacc_WuwWuhRuh(Vss_0004,VuuUH_0812,RtUH_1620);
build EndPacket;
}
# (v60,1) vrsad -- "Vdd.uw=vrsad(Vuu.ub,Rt.ub,#u1)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 1 1 i d d d d d
define pcodeop vrsad_WubRubI;
:vrsad VddUW_0004,VuuUB_0812,RtUB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x0 & op0607=0x3 & VddUW_0004 & VuuUB_0812 & RtUB_1620 & Uimm1_05 & $(END_PACKET) {
VddUW_0004 = vrsad_WubRubI(VuuUB_0812,RtUB_1620,Uimm1_05);
build EndPacket;
}
# (v60,1) vrsad -- "Vxx.uw+=vrsad(Vuu.ub,Rt.ub,#u1)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 1 1 i x x x x x
define pcodeop vrsadacc_WuwWubRubI;
:vrsad+= VddUW_0004,VuuUB_0812,RtUB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0607=0x3 & Vss_0004 & VddUW_0004 & VuuUB_0812 & RtUB_1620 & Uimm1_05 & $(END_PACKET) {
VddUW_0004 = vrsadacc_WuwWubRubI(Vss_0004,VuuUB_0812,RtUB_1620,Uimm1_05);
build EndPacket;
}
# (v60,1) vdmpy -- "Vd.w=vdmpy(Vu.h,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 1 0 d d d d d
define pcodeop vdmpy_VhRb;
:vdmpy VdW_0004,VuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x2 & VdW_0004 & VuH_0812 & RtB_1620 & $(END_PACKET) {
VdW_0004 = vdmpy_VhRb(VuH_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vdmpy -- "Vd.h=vdmpy(Vu.ub,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 1 0 d d d d d
define pcodeop vdmpy_VubRb;
:vdmpy VdH_0004,VuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x6 & VdH_0004 & VuUB_0812 & RtB_1620 & $(END_PACKET) {
VdH_0004 = vdmpy_VubRb(VuUB_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vdmpy -- "Vx.w+=vdmpy(Vu.h,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 1 1 x x x x x
define pcodeop vdmpyacc_VwVhRb;
:vdmpy+= VdW_0004,VuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x3 & vs5 & VdW_0004 & VuH_0812 & RtB_1620 & $(END_PACKET) {
VdW_0004 = vdmpyacc_VwVhRb(vs5,VuH_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vdmpy -- "Vx.h+=vdmpy(Vu.ub,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 1 0 x x x x x
define pcodeop vdmpyacc_VhVubRb;
:vdmpy+= VdH_0004,VuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x6 & vs5 & VdH_0004 & VuUB_0812 & RtB_1620 & $(END_PACKET) {
VdH_0004 = vdmpyacc_VhVubRb(vs5,VuUB_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vdmpy -- "Vd.w=vdmpy(Vu.h,Rt.uh):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 0 0 d d d d d
define pcodeop vdmpy_VhRuh_sat;
:vdmpy^":sat" VdW_0004,VuH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x0 & VdW_0004 & VuH_0812 & RtUH_1620 & $(END_PACKET) {
VdW_0004 = vdmpy_VhRuh_sat(VuH_0812,RtUH_1620);
build EndPacket;
}
# (v60,1) vdmpy -- "Vd.w=vdmpy(Vu.h,Rt.h):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 1 0 d d d d d
define pcodeop vdmpy_VhRh_sat;
:vdmpy^":sat" VdW_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x2 & VdW_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) {
VdW_0004 = vdmpy_VhRh_sat(VuH_0812,RtH_1620);
build EndPacket;
}
# (v60,1) vdmpy -- "Vx.w+=vdmpy(Vu.h,Rt.uh):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 0 0 x x x x x
define pcodeop vdmpyacc_VwVhRuh_sat;
:vdmpy+=^":sat" VdW_0004,VuH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x0 & vs5 & VdW_0004 & VuH_0812 & RtUH_1620 & $(END_PACKET) {
VdW_0004 = vdmpyacc_VwVhRuh_sat(vs5,VuH_0812,RtUH_1620);
build EndPacket;
}
# (v60,1) vdmpy -- "Vx.w+=vdmpy(Vu.h,Rt.h):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 1 1 x x x x x
define pcodeop vdmpyacc_VwVhRh_sat;
:vdmpy+=^":sat" VdW_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x3 & vs5 & VdW_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) {
VdW_0004 = vdmpyacc_VwVhRh_sat(vs5,VuH_0812,RtH_1620);
build EndPacket;
}
# (v60,1) vdmpy -- "Vd.w=vdmpy(Vu.h,Vv.h):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d
define pcodeop vdmpy_VhVh_sat;
:vdmpy^":sat" VdW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x0 & op0507=0x3 & VdW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdW_0004 = vdmpy_VhVh_sat(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vd.h=vmpy(Vu.h,Rt.h):<<1:sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 0 1 d d d d d
define pcodeop vmpy_VhRh_s1_sat;
:vmpy^":<<1:sat" VdH_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x0 & op0507=0x1 & VdH_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) {
VdH_0004 = vmpy_VhRh_s1_sat(VuH_0812,RtH_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vd.h=vmpy(Vu.h,Rt.h):<<1:rnd:sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 1 0 d d d d d
define pcodeop vmpy_VhRh_s1_rnd_sat;
:vmpy^":<<1:rnd:sat" VdH_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x0 & op0507=0x2 & VdH_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) {
VdH_0004 = vmpy_VhRh_s1_rnd_sat(VuH_0812,RtH_1620);
build EndPacket;
}
# (v60,1) vmpy -- "Vd.uh=vmpy(Vu.uh,Vv.uh):>>16"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d
define pcodeop vmpy_VuhVuh_rs16;
:vmpy^":>>16" VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x1 & op0507=0x7 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) {
VdUH_0004 = vmpy_VuhVuh_rs16(VuUH_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vmpyieo -- "Vd.w=vmpyieo(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d
define pcodeop vmpyieo_VhVh;
:vmpyieo VdW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x0 & VdW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdW_0004 = vmpyieo_VhVh(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vmpyi -- "Vx.w+=vmpyi(Vu.w,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 1 0 x x x x x
define pcodeop vmpyiacc_VwVwRb;
:vmpyi+= VdW_0004,VuW_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0507=0x2 & vs5 & VdW_0004 & VuW_0812 & RtB_1620 & $(END_PACKET) {
VdW_0004 = vmpyiacc_VwVwRb(vs5,VuW_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vmpyi -- "Vd.h=vmpyi(Vu.h,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 0 0 d d d d d
define pcodeop vmpyi_VhRb;
:vmpyi VdH_0004,VuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x0 & VdH_0004 & VuH_0812 & RtB_1620 & $(END_PACKET) {
VdH_0004 = vmpyi_VhRb(VuH_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vmpyi -- "Vx.h+=vmpyi(Vu.h,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 0 0 1 x x x x x
define pcodeop vmpyiacc_VhVhRb;
:vmpyi+= VdH_0004,VuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op0507=0x1 & vs5 & VdH_0004 & VuH_0812 & RtB_1620 & $(END_PACKET) {
VdH_0004 = vmpyiacc_VhVhRb(vs5,VuH_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vmpyi -- "Vd.w=vmpyi(Vu.w,Rt.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 1 1 0 d d d d d
define pcodeop vmpyi_VwRub;
:vmpyi VdW_0004,VuW_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x0 & op0507=0x6 & VdW_0004 & VuW_0812 & RtUB_1620 & $(END_PACKET) {
VdW_0004 = vmpyi_VwRub(VuW_0812,RtUB_1620);
build EndPacket;
}
# (v60,1) vmpyi -- "Vx.w+=vmpyi(Vu.w,Rt.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 0 1 x x x x x
define pcodeop vmpyiacc_VwVwRub;
:vmpyi+= VdW_0004,VuW_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x1 & vs5 & VdW_0004 & VuW_0812 & RtUB_1620 & $(END_PACKET) {
VdW_0004 = vmpyiacc_VwVwRub(vs5,VuW_0812,RtUB_1620);
build EndPacket;
}
# (v60,1) vmpyi -- "Vd.w=vmpyi(Vu.w,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 0 0 0 d d d d d
define pcodeop vmpyi_VwRb;
:vmpyi VdW_0004,VuW_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op0507=0x0 & VdW_0004 & VuW_0812 & RtB_1620 & $(END_PACKET) {
VdW_0004 = vmpyi_VwRb(VuW_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vmpye -- "Vd.uw=vmpye(Vu.uh,Rt.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 1 0 d d d d d
define pcodeop vmpye_VuhRuh;
:vmpye VdUW_0004,VuUH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x2 & VdUW_0004 & VuUH_0812 & RtUH_1620 & $(END_PACKET) {
VdUW_0004 = vmpye_VuhRuh(VuUH_0812,RtUH_1620);
build EndPacket;
}
# (v60,1) vmpye -- "Vx.uw+=vmpye(Vu.uh,Rt.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 1 1 x x x x x
define pcodeop vmpyeacc_VuwVuhRuh;
:vmpye+= VdUW_0004,VuUH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x3 & vs5 & VdUW_0004 & VuUH_0812 & RtUH_1620 & $(END_PACKET) {
VdUW_0004 = vmpyeacc_VuwVuhRuh(vs5,VuUH_0812,RtUH_1620);
build EndPacket;
}
# (v60,1) vrmpy -- "Vd.uw=vrmpy(Vu.ub,Rt.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 1 1 d d d d d
define pcodeop vrmpy_VubRub;
:vrmpy VdUW_0004,VuUB_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x3 & VdUW_0004 & VuUB_0812 & RtUB_1620 & $(END_PACKET) {
VdUW_0004 = vrmpy_VubRub(VuUB_0812,RtUB_1620);
build EndPacket;
}
# (v60,1) vrmpy -- "Vd.w=vrmpy(Vu.ub,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 0 0 d d d d d
define pcodeop Vw_vrmpy_VubRb;
:vrmpy VdW_0004,VuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x4 & VdW_0004 & VuUB_0812 & RtB_1620 & $(END_PACKET) {
VdW_0004 = Vw_vrmpy_VubRb(VuUB_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vrmpy -- "Vx.uw+=vrmpy(Vu.ub,Rt.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 0 0 x x x x x
define pcodeop vrmpyacc_VuwVubRub;
:vrmpy+= VdUW_0004,VuUB_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x4 & vs5 & VdUW_0004 & VuUB_0812 & RtUB_1620 & $(END_PACKET) {
VdUW_0004 = vrmpyacc_VuwVubRub(vs5,VuUB_0812,RtUB_1620);
build EndPacket;
}
# (v60,1) vrmpy -- "Vx.w+=vrmpy(Vu.ub,Rt.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 0 1 x x x x x
define pcodeop vrmpyacc_VwVubRb;
:vrmpy+= VdW_0004,VuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x5 & vs5 & VdW_0004 & VuUB_0812 & RtB_1620 & $(END_PACKET) {
VdW_0004 = vrmpyacc_VwVubRb(vs5,VuUB_0812,RtB_1620);
build EndPacket;
}
# (v60,1) vrmpy -- "Vd.uw=vrmpy(Vu.ub,Vv.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d
define pcodeop Vuw_vrmpy_VubVub;
:vrmpy VdUW_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x0 & op0507=0x0 & VdUW_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) {
VdUW_0004 = Vuw_vrmpy_VubVub(VuUB_0812,VvUB_1620);
build EndPacket;
}
# (v60,1) vrmpy -- "Vd.w=vrmpy(Vu.b,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d
define pcodeop Vw_vrmpy_VbVb;
:vrmpy VdW_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x0 & op0507=0x1 & VdW_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) {
VdW_0004 = Vw_vrmpy_VbVb(VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vrmpy -- "Vd.w=vrmpy(Vu.ub,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d
define pcodeop Vw_vrmpy_VubVb;
:vrmpy VdW_0004,VuUB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x0 & op0507=0x2 & VdW_0004 & VuUB_0812 & VvB_1620 & $(END_PACKET) {
VdW_0004 = Vw_vrmpy_VubVb(VuUB_0812,VvB_1620);
build EndPacket;
}
#
# NOTE: The vsplat instruction from V60 was removed in later versions
#
# (v60,1) vsplat -- "Vd=vsplat(Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - - - 0 0 0 1 d d d d d
define pcodeop V_vsplat_R;
:vsplat Vd5,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op0508=0x1 & Vd5 & rx5 & $(END_PACKET) {
Vd5 = V_vsplat_R(rx5);
build EndPacket;
}
# (v60,1) vsplat -- "Vd.h=vsplat(Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 - - - - - 0 0 1 d d d d d
define pcodeop Vh_vsplat_R;
:vsplat VdH_0004,rx5 EndPacket is iclass=0x1 & op2127=0x4e & op13=0x0 & op0507=0x1 & VdH_0004 & rx5 & $(END_PACKET) {
VdH_0004 = Vh_vsplat_R(rx5);
build EndPacket;
}
# (v60,1) vsplat -- "Vd.b=vsplat(Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 - - - - - 0 1 0 d d d d d
define pcodeop Vb_vsplat_R;
:vsplat VdB_0004,rx5 EndPacket is iclass=0x1 & op2127=0x4e & op13=0x0 & op0507=0x2 & VdB_0004 & rx5 & $(END_PACKET) {
VdB_0004 = Vb_vsplat_R(rx5);
build EndPacket;
}
# (v60,1) vand -- "Qx4|=vand(Vu,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 1 0 0 - - - x x
define pcodeop Q_vandor_QVR;
:vand|= Qd2,Vu_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op0507=0x4 & Qd2 & Vu_0812 & rx5 & $(END_PACKET) {
Qd2 = Q_vandor_QVR(Qd2,Vu_0812,rx5);
build EndPacket;
}
# (v60,1) vand -- "Qd4=vand(Vu,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 0 1 0 - 1 0 d d
define pcodeop Q_vand_VR;
:vand Qd2,Vu_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op0507=0x2 & op3=0x1 & op2=0x0 & Qd2 & Vu_0812 & rx5 & $(END_PACKET) {
Qd2 = Q_vand_VR(Vu_0812,rx5);
build EndPacket;
}
# (v60,1) vand -- "Vx|=vand(Qu4,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 - - 0 u u 0 1 1 x x x x x
define pcodeop V_vandor_VQR;
:vand|= Vd5,qv0809,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op10=0x0 & op0507=0x3 & Vd5 & vs5 & qv0809 & rx5 & $(END_PACKET) {
Vd5 = V_vandor_VQR(vs5,qv0809,rx5);
build EndPacket;
}
# (v60,1) vand -- "Vx|=vand(!Qu4,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 - - 1 u u 0 1 1 x x x x x
:vand|= Vd5,Qv0809Not,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op10=0x1 & op0507=0x3 & Vd5 & vs5 & Qv0809Not & rx5 & $(END_PACKET) {
Vd5 = V_vandor_VQR(vs5,Qv0809Not,rx5);
build EndPacket;
}
# (v60,1) vand -- "Vd=vand(Qu4,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - 0 u u 1 0 1 d d d d d
define pcodeop V_vand_QR;
:vand Vd5,qv0809,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op10=0x0 & op0507=0x5 & Vd5 & qv0809 & rx5 & $(END_PACKET) {
Vd5 = V_vand_QR(qv0809,rx5);
build EndPacket;
}
# (v60,1) vand -- "Vd=vand(!Qu4,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - 1 u u 1 0 1 d d d d d
:vand Vd5,Qv0809Not,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op10=0x1 & op0507=0x5 & Vd5 & Qv0809Not & rx5 & $(END_PACKET) {
Vd5 = V_vand_QR(Qv0809Not,rx5);
build EndPacket;
}
# (v60,1) vabsdiff -- "Vd.ub=vabsdiff(Vu.ub,Vv.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d
define pcodeop Vub_vabsdiff_VubVub;
:vabsdiff VdUB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x0 & VdUB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) {
VdUB_0004 = Vub_vabsdiff_VubVub(VuUB_0812,VvUB_1620);
build EndPacket;
}
# (v60,1) vabsdiff -- "Vd.uh=vabsdiff(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d
define pcodeop Vuh_vabsdiff_VhVh;
:vabsdiff VdUH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x1 & VdUH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdUH_0004 = Vuh_vabsdiff_VhVh(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vabsdiff -- "Vd.uh=vabsdiff(Vu.uh,Vv.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d
define pcodeop Vuh_vabsdiff_VuhVuh;
:vabsdiff VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x2 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) {
VdUH_0004 = Vuh_vabsdiff_VuhVuh(VuUH_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vabsdiff -- "Vd.uw=vabsdiff(Vu.w,Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d
define pcodeop Vuw_vabsdiff_VwVw;
:vabsdiff VdUW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x3 & VdUW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) {
VdUW_0004 = Vuw_vabsdiff_VwVw(VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vinsert -- "Vx.w=vinsert(Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 - - - - - 0 0 1 x x x x x
define pcodeop vinsert_VwR;
:vinsert VdW_0004,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x1 & op0507=0x1 & vs5 & VdW_0004 & rx5 & $(END_PACKET) {
VdW_0004 = vinsert_VwR(vs5,rx5);
build EndPacket;
}
# (v60,1) vror -- "Vd=vror(Vu,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 0 1 d d d d d
define pcodeop vror_VR;
:vror Vd5,Vu_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x1 & Vd5 & Vu_0812 & rx5 & $(END_PACKET) {
Vd5 = vror_VR(Vu_0812,rx5);
build EndPacket;
}
# (v60,1) valign -- "Vd=valign(Vu,Vv,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 0 0 d d d d d
define pcodeop valign_VVR;
:valign Vd5,Vu_0812,Vz_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x0 & Vd5 & Vu_0812 & Vz_1923 & rt1618 & $(END_PACKET) {
Vd5 = valign_VVR(Vu_0812,Vz_1923,rt1618);
build EndPacket;
}
# (v60,1) vlalign -- "Vd=vlalign(Vu,Vv,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 0 1 d d d d d
define pcodeop vlalign_VVR;
:vlalign Vd5,Vu_0812,Vz_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x1 & Vd5 & Vu_0812 & Vz_1923 & rt1618 & $(END_PACKET) {
Vd5 = vlalign_VVR(Vu_0812,Vz_1923,rt1618);
build EndPacket;
}
# (v60,1) valign -- "Vd=valign(Vu,Vv,#u3)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 0 0 1 v v v v v P P 1 u u u u u i i i d d d d d
define pcodeop V_valign_VVI;
:valign Vd5,Vu_0812,Vv_1620,Uimm8_0507 EndPacket is iclass=0x1 & op2127=0x71 & op13=0x1 & Vd5 & Vu_0812 & Vv_1620 & Uimm8_0507 & $(END_PACKET) {
Vd5 = V_valign_VVI(Vu_0812,Vv_1620,Uimm8_0507);
build EndPacket;
}
# (v60,1) vlalign -- "Vd=vlalign(Vu,Vv,#u3)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 0 1 1 v v v v v P P 1 u u u u u i i i d d d d d
define pcodeop V_vlalign_VVI;
:vlalign Vd5,Vu_0812,Vv_1620,Uimm8_0507 EndPacket is iclass=0x1 & op2127=0x73 & op13=0x1 & Vd5 & Vu_0812 & Vv_1620 & Uimm8_0507 & $(END_PACKET) {
Vd5 = V_vlalign_VVI(Vu_0812,Vv_1620,Uimm8_0507);
build EndPacket;
}
# (v60,1) vdelta -- "Vd=vdelta(Vu,Vv)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d
define pcodeop vdelta_VV;
:vdelta Vd5,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x1 & Vd5 & Vu_0812 & Vv_1620 & $(END_PACKET) {
Vd5 = vdelta_VV(Vu_0812,Vv_1620);
build EndPacket;
}
# (v60,1) vrdelta -- "Vd=vrdelta(Vu,Vv)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d
define pcodeop vrdelta_VV;
:vrdelta Vd5,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x3 & Vd5 & Vu_0812 & Vv_1620 & $(END_PACKET) {
Vd5 = vrdelta_VV(Vu_0812,Vv_1620);
build EndPacket;
}
# (v60,1) vdeal -- "Vd.h=vdeal(Vu.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 1 1 0 d d d d d
define pcodeop vdeal_Vh;
:vdeal VdH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x0 & op13=0x0 & op0507=0x6 & VdH_0004 & VuH_0812 & $(END_PACKET) {
VdH_0004 = vdeal_Vh(VuH_0812);
build EndPacket;
}
# (v60,1) vdeal -- "Vd.b=vdeal(Vu.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 1 1 1 d d d d d
define pcodeop vdeal_Vb;
:vdeal VdB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x0 & op13=0x0 & op0507=0x7 & VdB_0004 & VuB_0812 & $(END_PACKET) {
VdB_0004 = vdeal_Vb(VuB_0812);
build EndPacket;
}
# (v60,1) vshuff -- "Vd.h=vshuff(Vu.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 1 1 d d d d d
define pcodeop vshuff_Vh;
:vshuff VdH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x7 & VdH_0004 & VuH_0812 & $(END_PACKET) {
VdH_0004 = vshuff_Vh(VuH_0812);
build EndPacket;
}
# (v60,1) vshuff -- "Vd.b=vshuff(Vu.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 0 0 d d d d d
define pcodeop vshuff_Vb;
:vshuff VdB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x0 & VdB_0004 & VuB_0812 & $(END_PACKET) {
VdB_0004 = vshuff_Vb(VuB_0812);
build EndPacket;
}
# (v60,1) vdeale -- "Vd.b=vdeale(Vu.b,Vv.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d
define pcodeop vdeale_VbVb;
:vdeale VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x7 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) {
VdB_0004 = vdeale_VbVb(VuB_0812,VvB_1620);
build EndPacket;
}
# (v60,1) vpacke -- "Vd.b=vpacke(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d
define pcodeop Vb_vpacke_VhVh;
:vpacke VdB_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x2 & VdB_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdB_0004 = Vb_vpacke_VhVh(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vpacke -- "Vd.h=vpacke(Vu.w,Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d
define pcodeop Vh_vpacke_VwVw;
:vpacke VdH_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x3 & VdH_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) {
VdH_0004 = Vh_vpacke_VwVw(VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vpack -- "Vd.ub=vpack(Vu.h,Vv.h):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d
define pcodeop Vb_vpack_VhVh_sat;
:vpack^":sat" VdUB_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x5 & VdUB_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdUB_0004 = Vb_vpack_VhVh_sat(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vpack -- "Vd.b=vpack(Vu.h,Vv.h):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d
define pcodeop Vb_vpacko_VhVh_sat;
:vpack^":sat" VdB_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x6 & VdB_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdB_0004 = Vb_vpacko_VhVh_sat(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vpack -- "Vd.uh=vpack(Vu.w,Vv.w):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d
define pcodeop Vuh_vpack_VwVw_sat;
:vpack^":sat" VdUH_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x7 & VdUH_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) {
VdUH_0004 = Vuh_vpack_VwVw_sat(VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vpack -- "Vd.h=vpack(Vu.w,Vv.w):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d
define pcodeop Vh_vpack_VwVw_sat;
:vpack^":sat" VdH_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x0 & op0507=0x0 & VdH_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) {
VdH_0004 = Vh_vpack_VwVw_sat(VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vpacko -- "Vd.b=vpacko(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d
define pcodeop Vb_vpacko_VhVh;
:vpacko VdB_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x0 & op0507=0x1 & VdB_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdB_0004 = Vb_vpacko_VhVh(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vpacko -- "Vd.h=vpacko(Vu.w,Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d
define pcodeop Vh_vpacko_VwVw;
:vpacko VdH_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x0 & op0507=0x2 & VdH_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) {
VdH_0004 = Vh_vpacko_VwVw(VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vsetq -- "Qd4=vsetq(Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - - - - 0 1 0 - 0 1 d d
define pcodeop Q_vsetq_R;
:vsetq Qd2,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op0507=0x2 & op3=0x0 & op2=0x1 & Qd2 & rx5 & $(END_PACKET) {
Qd2 = Q_vsetq_R(rx5);
build EndPacket;
}
# (v60,1) vsetq2 -- "Qd4=vsetq2(Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - - - - 0 1 0 - 1 1 d d
define pcodeop Q_vsetq2_R;
:vsetq2 Qd2,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op0507=0x2 & op3=0x1 & op2=0x1 & Qd2 & rx5 & $(END_PACKET) {
Qd2 = Q_vsetq2_R(rx5);
build EndPacket;
}
# (v60,1) vlut32 -- "Vd.b=vlut32(Vu.b,Vv.b,Rt):nomatch"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 1 1 d d d d d
define pcodeop Vb_vlut32_VbVbR_nomatch;
:vlut32^":nomatch" VdB_0004,VuB_0812,VzB_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x0 & op0507=0x3 & VdB_0004 & VuB_0812 & VzB_1923 & rt1618 & $(END_PACKET) {
VdB_0004 = Vb_vlut32_VbVbR_nomatch(VuB_0812,VzB_1923,rt1618);
build EndPacket;
}
# (v60,1) vlut32 -- "Vd.b=vlut32(Vu.b,Vv.b,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 0 1 d d d d d
define pcodeop Vb_vlut32_VbVbR;
:vlut32 VdB_0004,VuB_0812,VzB_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x1 & op0507=0x1 & VdB_0004 & VuB_0812 & VzB_1923 & rt1618 & $(END_PACKET) {
VdB_0004 = Vb_vlut32_VbVbR(VuB_0812,VzB_1923,rt1618);
build EndPacket;
}
# (v60,1) vlut32 -- "Vd.b=vlut32(Vu.b,Vv.b,#u3)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 0 0 1 v v v v v P P 0 u u u u u i i i d d d d d
define pcodeop Vb_vlut32_VbVbI;
:vlut32 VdB_0004,VuB_0812,VvB_1620,Uimm8_0507 EndPacket is iclass=0x1 & op2127=0x71 & op13=0x0 & VdB_0004 & VuB_0812 & VvB_1620 & Uimm8_0507 & $(END_PACKET) {
VdB_0004 = Vb_vlut32_VbVbI(VuB_0812,VvB_1620,Uimm8_0507);
build EndPacket;
}
# (v60,1) vasrinto -- "Vxx.w=vasrinto(Vu.w,Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 1 0 1 0 1 v v v v v P P 1 u u u u u 1 1 1 x x x x x
define pcodeop vasrinto_WwVwVw;
:vasrinto VddW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x55 & op13=0x1 & op0507=0x7 & Vss_0004 & VddW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) {
VddW_0004 = vasrinto_WwVwVw(Vss_0004,VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vshuff -- "vshuff(Vy,Vx,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 1 1 t t t t t P P 1 y y y y y 0 0 1 x x x x x
define pcodeop vshuff_VwVwR;
:vshuff vu5,vs5,rx5 EndPacket is iclass=0x1 & op2127=0x4f & op13=0x1 & op0507=0x1 & vu5 & vs5 & rx5 & $(END_PACKET) {
# NOTE: Uncertain if this logic is correct or if .new value store should be updated in some way
pair:$(HVX_VECTOR_PAIR_SIZE) = vshuff_VwVwR(vu5,vs5,rx5);
build EndPacket;
<<COMMIT>>
# Extract updated Vy and Vx vectors from 'pair' result from vshuff
vu5 = pair($(HVX_VECTOR_SIZE));
vs5 = pair:$(HVX_VECTOR_SIZE);
}
# (v60,1) vdeal -- "vdeal(Vy,Vx,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 1 1 t t t t t P P 1 y y y y y 0 1 0 x x x x x
define pcodeop vdeal_VwVwR;
:vdeal vu5,vs5,rx5 EndPacket is iclass=0x1 & op2127=0x4f & op13=0x1 & op0507=0x2 & vu5 & vs5 & rx5 & $(END_PACKET) {
# NOTE: Uncertain if this logic is correct or if .new value store should be updated in some way
pair:$(HVX_VECTOR_PAIR_SIZE) = vdeal_VwVwR(vu5,vs5,rx5);
build EndPacket;
<<COMMIT>>
# Extract updated Vy and Vx vectors from 'pair' result from vdeal
vu5 = pair($(HVX_VECTOR_SIZE));
vs5 = pair:$(HVX_VECTOR_SIZE);
}
# (v60,1) vshuff -- "Vdd=vshuff(Vu,Vv,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 1 1 d d d d d
:vshuff Vdd5,Vu_0812,Vz_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x1 & op0507=0x3 & Vdd5 & Vu_0812 & Vz_1923 & rt1618 & $(END_PACKET) {
Vdd5 = vshuff_VwVwR(Vu_0812,Vz_1923,rt1618);
build EndPacket;
}
# (v60,1) vdeal -- "Vdd=vdeal(Vu,Vv,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 0 0 d d d d d
:vdeal Vdd5,Vu_0812,Vz_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x1 & op0507=0x4 & Vdd5 & Vu_0812 & Vz_1923 & rt1618 & $(END_PACKET) {
Vdd5 = vdeal_VwVwR(Vu_0812,Vz_1923,rt1618);
build EndPacket;
}
# (v60,1) vlut16 -- "Vdd.h=vlut16(Vu.b,Vv.h,Rt):nomatch"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 1 0 0 d d d d d
define pcodeop vlut16_VbVhR_nomatch;
:vlut16^":nomatch" VddH_0004,VuB_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x0 & op0507=0x4 & Vss_0004 & VddH_0004 & VuB_0812 & VzH_1923 & rt1618 & $(END_PACKET) {
VddH_0004 = vlut16_VbVhR_nomatch(Vss_0004,VuB_0812,VzH_1923,rt1618);
build EndPacket;
}
# (v60,1) vlut32 -- "Vx.b|=vlut32(Vu.b,Vv.b,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 0 1 x x x x x
define pcodeop vlut32or_VbVbVbR;
:vlut32|= VdB_0004,VuB_0812,VzB_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x1 & op0507=0x5 & vs5 & VdB_0004 & VuB_0812 & VzB_1923 & rt1618 & $(END_PACKET) {
VdB_0004 = vlut32or_VbVbVbR(vs5,VuB_0812,VzB_1923,rt1618);
build EndPacket;
}
# (v60,1) vlut16 -- "Vdd.h=vlut16(Vu.b,Vv.h,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 1 0 d d d d d
define pcodeop vlut16_VbVhR;
:vlut16 VddH_0004,VuB_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x1 & op0507=0x6 & VddH_0004 & VuB_0812 & VzH_1923 & rt1618 & $(END_PACKET) {
VddH_0004 = vlut16_VbVhR(VuB_0812,VzH_1923,rt1618);
build EndPacket;
}
# (v60,1) vlut16 -- "Vxx.h|=vlut16(Vu.b,Vv.h,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 1 1 x x x x x
define pcodeop vlut16or_WhVbVhR;
:vlut16|= VddH_0004,VuB_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x1 & op0507=0x7 & Vss_0004 & VddH_0004 & VuB_0812 & VzH_1923 & rt1618 & $(END_PACKET) {
VddH_0004 = vlut16or_WhVbVhR(Vss_0004,VuB_0812,VzH_1923,rt1618);
build EndPacket;
}
# (v60,1) vlut32 -- "Vx.b|=vlut32(Vu.b,Vv.b,#u3)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 1 u u u u u i i i x x x x x
define pcodeop vlut32or_VbVbVbI;
:vlut32|= VdB_0004,VuB_0812,VvB_1620,Uimm8_0507 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x1 & vs5 & VdB_0004 & VuB_0812 & VvB_1620 & Uimm8_0507 & $(END_PACKET) {
VdB_0004 = vlut32or_VbVbVbI(vs5,VuB_0812,VvB_1620,Uimm8_0507);
build EndPacket;
}
# (v60,1) vlut16 -- "Vxx.h|=vlut16(Vu.b,Vv.h,#u3)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 1 u u u u u i i i x x x x x
define pcodeop vlut16or_WhVbVhI;
:vlut16|= VddH_0004,VuB_0812,VvH_1620,Uimm8_0507 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x1 & Vss_0004 & VddH_0004 & VuB_0812 & VvH_1620 & Uimm8_0507 & $(END_PACKET) {
VddH_0004 = vlut16or_WhVbVhI(Vss_0004,VuB_0812,VvH_1620,Uimm8_0507);
build EndPacket;
}
# (v60,1) vlut16 -- "Vdd.h=vlut16(Vu.b,Vv.h,#u3)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 0 1 1 v v v v v P P 0 u u u u u i i i d d d d d
define pcodeop vlut16_VbVhI;
:vlut16 VddH_0004,VuB_0812,VvH_1620,Uimm8_0507 EndPacket is iclass=0x1 & op2127=0x73 & op13=0x0 & Vss_0004 & VddH_0004 & VuB_0812 & VvH_1620 & Uimm8_0507 & $(END_PACKET) {
VddH_0004 = vlut16_VbVhI(Vss_0004,VuB_0812,VvH_1620,Uimm8_0507);
build EndPacket;
}
# (v60,1) vunpack -- "Vdd.uh=vunpack(Vu.ub)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 0 0 d d d d d
define pcodeop Wuh_vunpack_Vub;
:vunpack VddUH_0004,VuUB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x0 & VddUH_0004 & VuUB_0812 & $(END_PACKET) {
VddUH_0004 = Wuh_vunpack_Vub(VuUB_0812);
build EndPacket;
}
# (v60,1) vunpack -- "Vdd.uw=vunpack(Vu.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 0 1 d d d d d
define pcodeop Wuw_vunpack_Vuh;
:vunpack VddUW_0004,VuUH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x1 & VddUW_0004 & VuUH_0812 & $(END_PACKET) {
VddUW_0004 = Wuw_vunpack_Vuh(VuUH_0812);
build EndPacket;
}
# (v60,1) vunpack -- "Vdd.h=vunpack(Vu.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 1 0 d d d d d
define pcodeop Wh_vunpack_Vb;
:vunpack VddH_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x2 & VddH_0004 & VuB_0812 & $(END_PACKET) {
VddH_0004 = Wh_vunpack_Vb(VuB_0812);
build EndPacket;
}
# (v60,1) vunpack -- "Vdd.w=vunpack(Vu.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 1 1 d d d d d
define pcodeop Ww_vunpack_Vh;
:vunpack VddW_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x3 & VddW_0004 & VuH_0812 & $(END_PACKET) {
VddW_0004 = Ww_vunpack_Vh(VuH_0812);
build EndPacket;
}
# (v60,1) vunpacko -- "Vxx.h|=vunpacko(Vu.b)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 u u u u u 0 0 0 x x x x x
define pcodeop vunpackoor_WhVb;
:vunpacko|= VddH_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0507=0x0 & Vss_0004 & VddH_0004 & VuB_0812 & $(END_PACKET) {
VddH_0004 = vunpackoor_WhVb(Vss_0004,VuB_0812);
build EndPacket;
}
# (v60,1) vunpacko -- "Vxx.w|=vunpacko(Vu.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 u u u u u 0 0 1 x x x x x
define pcodeop vunpackoor_WwVh;
:vunpacko|= VddW_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0507=0x1 & Vss_0004 & VddW_0004 & VuH_0812 & $(END_PACKET) {
VddW_0004 = vunpackoor_WwVh(Vss_0004,VuH_0812);
build EndPacket;
}
# (v60,2) "vscatter(Rt,Mu,Vvv.w).h=Vw32"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 0 1 0 w w w w w
define pcodeop vscatter_RMWwV;
:vscatter.h rt5,mu,VuuW_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x79 & op0507=0x2 & rt5 & mu & VuuW_0812 & Vs_0004 & $(END_PACKET) {
# May need to splt-up to convey delayed memory commit vs register reads
vscatter_RMWwV(rt5,mu,VuuW_0812,Vs_0004);
build EndPacket;
}
# (v60,2) "vscatter(Rt,Mu,Vvv.w).h+=Vw32"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 1 1 0 w w w w w
define pcodeop vscatteracc_RMWwV;
:vscatter.h+= rt5,mu,VuuW_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x79 & op0507=0x6 & rt5 & mu & VuuW_0812 & Vs_0004 & $(END_PACKET) {
# May need to splt-up to convey delayed memory commit vs register reads
vscatteracc_RMWwV(rt5,mu,VuuW_0812,Vs_0004);
build EndPacket;
}
# (v60,2) "if (Qs4) vscatter(Rt,Mu,Vvv.w).h=Vw32"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 1 1 1 1 0 1 t t t t t P P u v v v v v 0 s s w w w w w
define pcodeop vscatter_QRMWwV;
:vscatter.h^".if("^qv0506^")" rt5,mu,VuuW_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x7d & op7=0x0 & qv0506 & rt5 & mu & VuuW_0812 & Vs_0004 & $(END_PACKET) {
# May need to splt-up to convey delayed memory commit vs register reads
vscatter_QRMWwV(qv0506,rt5,mu,VuuW_0812,Vs_0004);
build EndPacket;
}
# (v60,2) "vscatter(Rt,Mu,Vv.w).w=Vw32"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 0 0 0 w w w w w
define pcodeop vscatter_RMVwV;
:vscatter.w rt5,mu,VuW_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x79 & op0507=0x0 & rt5 & mu & VuW_0812 & Vs_0004 & $(END_PACKET) {
# May need to splt-up to convey delayed memory commit vs register reads
vscatter_RMVwV(rt5,mu,VuW_0812,Vs_0004);
build EndPacket;
}
# (v60,2) "vscatter(Rt,Mu,Vv.h).h=Vw32"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 0 0 1 w w w w w
define pcodeop vscatter_RMVhV;
:vscatter.h rt5,mu,VuH_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x79 & op0507=0x1 & rt5 & mu & VuH_0812 & Vs_0004 & $(END_PACKET) {
# May need to splt-up to convey delayed memory commit vs register reads
vscatter_RMVhV(rt5,mu,VuH_0812,Vs_0004);
build EndPacket;
}
# (v60,2) "vscatter(Rt,Mu,Vv.w).w+=Vw32"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 1 0 0 w w w w w
define pcodeop vscatteracc_RMVwV;
:vscatter.w+= rt5,mu,VuW_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x79 & op0507=0x4 & rt5 & mu & VuW_0812 & Vs_0004 & $(END_PACKET) {
# May need to splt-up to convey delayed memory commit vs register reads
vscatteracc_RMVwV(rt5,mu,VuW_0812,Vs_0004);
build EndPacket;
}
# (v60,2) "vscatter(Rt,Mu,Vv.h).h+=Vw32"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 1 0 1 w w w w w
define pcodeop vscatteracc_RMVhV;
:vscatter.h+= rt5,mu,VuH_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x79 & op0507=0x5 & rt5 & mu & VuH_0812 & Vs_0004 & $(END_PACKET) {
# May need to splt-up to convey delayed memory commit vs register reads
vscatteracc_RMVhV(rt5,mu,VuH_0812,Vs_0004);
build EndPacket;
}
# (v60,2) "if (Qs4) vscatter(Rt,Mu,Vv.w).w=Vw32"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 1 1 1 1 0 0 t t t t t P P u v v v v v 0 s s w w w w w
define pcodeop vscatter_QRMVwV;
:vscatter.w^".if("^qv0506^")" rt5,mu,VuW_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x7c & op7=0x0 & qv0506 & rt5 & mu & VuW_0812 & Vs_0004 & $(END_PACKET) {
# May need to splt-up to convey delayed memory commit vs register reads
vscatter_QRMVwV(qv0506,rt5,mu,VuW_0812,Vs_0004);
build EndPacket;
}
# (v60,2) "if (Qs4) vscatter(Rt,Mu,Vv.h).h=Vw32"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 1 1 1 1 0 0 t t t t t P P u v v v v v 1 s s w w w w w
define pcodeop vscatter_QRMVhV;
:vscatter.h^".if("^qv0506^")" rt5,mu,VuH_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x7c & op7=0x1 & qv0506 & rt5 & mu & VuH_0812 & Vs_0004 & $(END_PACKET) {
# May need to splt-up to convey delayed memory commit vs register reads
vscatter_QRMVhV(qv0506,rt5,mu,VuH_0812,Vs_0004);
build EndPacket;
}
# (v60,1) vasr -- "Vd.b=vasr(Vu.h,Vv.h,Rt):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 0 0 d d d d d
define pcodeop Vb_vasr_VhVhR_sat;
:vasr^":sat" VdB_0004,VuH_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x0 & op0507=0x0 & VdB_0004 & VuH_0812 & VzH_1923 & rt1618 & $(END_PACKET) {
VdB_0004 = Vb_vasr_VhVhR_sat(VuH_0812,VzH_1923,rt1618);
build EndPacket;
}
# (v60,1) vasr -- "Vd.uh=vasr(Vu.uw,Vv.uw,Rt):rnd:sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 0 1 d d d d d
define pcodeop vasr_VhVhR_rnd_sat;
:vasr^":rnd:sat" VdUH_0004,VuUW_0812,VzUW_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x0 & op0507=0x1 & VdUH_0004 & VuUW_0812 & VzUW_1923 & rt1618 & $(END_PACKET) {
VdUH_0004 = vasr_VhVhR_rnd_sat(VuUW_0812,VzUW_1923,rt1618);
build EndPacket;
}
# (v60,1) vasr -- "Vd.uh=vasr(Vu.w,Vv.w,Rt):rnd:sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 1 0 d d d d d
define pcodeop Vuh_vasr_VwVwR_rnd_sat;
:vasr^":rnd:sat" VdUH_0004,VuW_0812,VzW_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x0 & op0507=0x2 & VdUH_0004 & VuW_0812 & VzW_1923 & rt1618 & $(END_PACKET) {
VdUH_0004 = Vuh_vasr_VwVwR_rnd_sat(VuW_0812,VzW_1923,rt1618);
build EndPacket;
}
# (v60,1) vasr -- "Vd.ub=vasr(Vu.uh,Vv.uh,Rt):rnd:sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 1 1 1 d d d d d
define pcodeop Vub_vasr_VuhVuhR_rnd_sat;
:vasr^":rnd:sat" VdUB_0004,VuUH_0812,VzUH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x0 & op0507=0x7 & VdUB_0004 & VuUH_0812 & VzUH_1923 & rt1618 & $(END_PACKET) {
VdUB_0004 = Vub_vasr_VuhVuhR_rnd_sat(VuUH_0812,VzUH_1923,rt1618);
build EndPacket;
}
# (v60,1) vasr -- "Vd.uh=vasr(Vu.uw,Vv.uw,Rt):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 0 v v v v v t t t P P 1 u u u u u 1 0 0 d d d d d
define pcodeop Vuh_vasr_VuwVuwR_sat;
:vasr^":sat" VdUH_0004,VuUW_0812,VzUW_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x1 & op0507=0x4 & VdUH_0004 & VuUW_0812 & VzUW_1923 & rt1618 & $(END_PACKET) {
VdUH_0004 = Vuh_vasr_VuwVuwR_sat(VuUW_0812,VzUW_1923,rt1618);
build EndPacket;
}
# (v60,1) vasr -- "Vd.ub=vasr(Vu.uh,Vv.uh,Rt):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 0 v v v v v t t t P P 1 u u u u u 1 0 1 d d d d d
define pcodeop Vub_vasr_VuhVuhR_sat;
:vasr^":sat" VdUB_0004,VuUH_0812,VzUH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x1 & op0507=0x5 & VdUB_0004 & VuUH_0812 & VzUH_1923 & rt1618 & $(END_PACKET) {
VdUB_0004 = Vub_vasr_VuhVuhR_sat(VuUH_0812,VzUH_1923,rt1618);
build EndPacket;
}
# (v60,1) vasr -- "Vd.h=vasr(Vu.w,Vv.w,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 1 0 d d d d d
define pcodeop Vh_vasr_VwVwR;
:vasr VdH_0004,VuW_0812,VzW_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x2 & VdH_0004 & VuW_0812 & VzW_1923 & rt1618 & $(END_PACKET) {
VdH_0004 = Vh_vasr_VwVwR(VuW_0812,VzW_1923,rt1618);
build EndPacket;
}
# (v60,1) vasr -- "Vd.h=vasr(Vu.w,Vv.w,Rt):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 1 1 d d d d d
define pcodeop Vh_vasr_VwVwR_sat;
:vasr^":sat" VdH_0004,VuW_0812,VzW_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x3 & VdH_0004 & VuW_0812 & VzW_1923 & rt1618 & $(END_PACKET) {
VdH_0004 = Vh_vasr_VwVwR_sat(VuW_0812,VzW_1923,rt1618);
build EndPacket;
}
# (v60,1) vasr -- "Vd.h=vasr(Vu.w,Vv.w,Rt):rnd:sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 0 0 d d d d d
define pcodeop Vh_vasr_VwVwR_rnd_sat;
:vasr^":rnd:sat" VdH_0004,VuW_0812,VzW_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x4 & VdH_0004 & VuW_0812 & VzW_1923 & rt1618 & $(END_PACKET) {
VdH_0004 = Vh_vasr_VwVwR_rnd_sat(VuW_0812,VzW_1923,rt1618);
build EndPacket;
}
# (v60,1) vasr -- "Vd.uh=vasr(Vu.w,Vv.w,Rt):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 0 1 d d d d d
define pcodeop Vuh_vasr_VwVwR_sat;
:vasr^":sat" VdUH_0004,VuW_0812,VzW_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x5 & VdUH_0004 & VuW_0812 & VzW_1923 & rt1618 & $(END_PACKET) {
VdUH_0004 = Vuh_vasr_VwVwR_sat(VuW_0812,VzW_1923,rt1618);
build EndPacket;
}
# (v60,1) vasr -- "Vd.ub=vasr(Vu.h,Vv.h,Rt):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 1 0 d d d d d
define pcodeop Vub_vasr_VhVhR_sat;
:vasr^":sat" VdUB_0004,VuH_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x6 & VdUB_0004 & VuH_0812 & VzH_1923 & rt1618 & $(END_PACKET) {
VdUB_0004 = Vub_vasr_VhVhR_sat(VuH_0812,VzH_1923,rt1618);
build EndPacket;
}
# (v60,1) vasr -- "Vd.ub=vasr(Vu.h,Vv.h,Rt):rnd:sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 1 1 d d d d d
define pcodeop Vub_vasr_VhVhR_rnd_sat;
:vasr^":rnd:sat" VdUB_0004,VuH_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x7 & VdUB_0004 & VuH_0812 & VzH_1923 & rt1618 & $(END_PACKET) {
VdUB_0004 = Vub_vasr_VhVhR_rnd_sat(VuH_0812,VzH_1923,rt1618);
build EndPacket;
}
# (v60,1) vasr -- "Vd.b=vasr(Vu.h,Vv.h,Rt):rnd:sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 0 0 d d d d d
define pcodeop Vb_vasr_VhVhR_rnd_sat;
:vasr^":rnd:sat" VdB_0004,VuH_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x1 & op0507=0x0 & VdB_0004 & VuH_0812 & VzH_1923 & rt1618 & $(END_PACKET) {
VdB_0004 = Vb_vasr_VhVhR_rnd_sat(VuH_0812,VzH_1923,rt1618);
build EndPacket;
}
# (v60,1) prefixsum -- "Vd.b=prefixsum(Qv4)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 - - 0 0 0 0 1 0 d d d d d
define pcodeop Vb_prefixsum_Q;
:prefixsum VdB_0004,qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x3 & op13=0x1 & op0810=0x0 & op0507=0x2 & VdB_0004 & qv2223 & $(END_PACKET) {
VdB_0004 = Vb_prefixsum_Q(qv2223);
build EndPacket;
}
# (v60,1) prefixsum -- "Vd.h=prefixsum(Qv4)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 - - 0 0 1 0 1 0 d d d d d
define pcodeop Vh_prefixsum_Q;
:prefixsum VdH_0004,qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x3 & op13=0x1 & op0810=0x1 & op0507=0x2 & VdH_0004 & qv2223 & $(END_PACKET) {
VdH_0004 = Vh_prefixsum_Q(qv2223);
build EndPacket;
}
# (v60,1) prefixsum -- "Vd.w=prefixsum(Qv4)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 - - 0 1 0 0 1 0 d d d d d
define pcodeop Vw_prefixsum_Q;
:prefixsum VdW_0004,qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x3 & op13=0x1 & op0810=0x2 & op0507=0x2 & VdW_0004 & qv2223 & $(END_PACKET) {
VdW_0004 = Vw_prefixsum_Q(qv2223);
build EndPacket;
}
# (v60,1) vadd -- "Vd.qf16=vadd(Vu.qf16,Vv.qf16)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 0 1 0 d d d d d
define pcodeop Vqf16_vadd_Vqf16Vqf16;
:vadd VdQF16_0004,VuQF16_0812,VvQF16_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x1 & op0507=0x2 & VdQF16_0004 & VuQF16_0812 & VvQF16_1620 & $(END_PACKET) {
VdQF16_0004 = Vqf16_vadd_Vqf16Vqf16(VuQF16_0812,VvQF16_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vd.qf16=vadd(Vu.hf,Vv.hf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 0 1 1 d d d d d
define pcodeop Vqf16_vadd_VhfVhf;
:vadd VdQF16_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x1 & op0507=0x3 & VdQF16_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) {
VdQF16_0004 = Vqf16_vadd_VhfVhf(VuHF_0812,VvHF_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vd.qf16=vadd(Vu.qf16,Vv.hf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 0 0 d d d d d
define pcodeop Vqf16_vadd_Vqf16Vhf;
:vadd VdQF16_0004,VuQF16_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x1 & op0507=0x4 & VdQF16_0004 & VuQF16_0812 & VvHF_1620 & $(END_PACKET) {
VdQF16_0004 = Vqf16_vadd_Vqf16Vhf(VuQF16_0812,VvHF_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vd.qf32=vadd(Vu.qf32,Vv.qf32)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 0 0 d d d d d
define pcodeop Vqf32_vadd_Vqf32Vqf32;
:vadd VdQF32_0004,VuQF32_0812,VvQF32_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x1 & op0507=0x0 & VdQF32_0004 & VuQF32_0812 & VvQF32_1620 & $(END_PACKET) {
VdQF32_0004 = Vqf32_vadd_Vqf32Vqf32(VuQF32_0812,VvQF32_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vd.qf32=vadd(Vu.sf,Vv.sf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 0 1 d d d d d
define pcodeop Vqf32_vadd_VsfVsf;
:vadd VdQF32_0004,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x1 & op0507=0x1 & VdQF32_0004 & VuSF_0812 & VvSF_1620 & $(END_PACKET) {
VdQF32_0004 = Vqf32_vadd_VsfVsf(VuSF_0812,VvSF_1620);
build EndPacket;
}
# (v60,1) vadd -- "Vd.qf32=vadd(Vu.qf32,Vv.sf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 1 0 d d d d d
define pcodeop Vqf32_vadd_Vqf32Vsf;
:vadd VdQF32_0004,VuQF32_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x1 & op0507=0x2 & VdQF32_0004 & VuQF32_0812 & VvSF_1620 & $(END_PACKET) {
VdQF32_0004 = Vqf32_vadd_Vqf32Vsf(VuQF32_0812,VvSF_1620);
build EndPacket;
}
# (v60,1) vasl -- "Vx.w+=vasl(Vu.w,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 0 1 0 x x x x x
define pcodeop vaslacc_VwVwR;
:vasl+= VdW_0004,VuW_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op0507=0x2 & vs5 & VdW_0004 & VuW_0812 & rx5 & $(END_PACKET) {
VdW_0004 = vaslacc_VwVwR(vs5,VuW_0812,rx5);
build EndPacket;
}
# (v60,1) vasr -- "Vx.w+=vasr(Vu.w,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 1 0 1 x x x x x
define pcodeop vasracc_VwVwR;
:vasr+= VdW_0004,VuW_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op0507=0x5 & vs5 & VdW_0004 & VuW_0812 & rx5 & $(END_PACKET) {
VdW_0004 = vasracc_VwVwR(vs5,VuW_0812,rx5);
build EndPacket;
}
# (v60,1) vasr -- "Vx.h+=vasr(Vu.h,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 1 1 x x x x x
define pcodeop vasracc_VhVhR;
:vasr+= VdH_0004,VuH_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x7 & vs5 & VdH_0004 & VuH_0812 & rx5 & $(END_PACKET) {
VdH_0004 = vasracc_VhVhR(vs5,VuH_0812,rx5);
build EndPacket;
}
# (v60,1) vasl -- "Vx.h+=vasl(Vu.h,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 u u u u u 1 0 1 x x x x x
define pcodeop vaslacc_VhVhR;
:vasl+= VdH_0004,VuH_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x1 & op0507=0x5 & vs5 & VdH_0004 & VuH_0812 & rx5 & $(END_PACKET) {
VdH_0004 = vaslacc_VhVhR(vs5,VuH_0812,rx5);
build EndPacket;
}
# (v60,1) vasr -- "Vd.w=vasr(Vu.w,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 0 1 d d d d d
define pcodeop vasr_VwR;
:vasr VdW_0004,VuW_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x5 & VdW_0004 & VuW_0812 & rx5 & $(END_PACKET) {
VdW_0004 = vasr_VwR(VuW_0812,rx5);
build EndPacket;
}
# (v60,1) vasr -- "Vd.h=vasr(Vu.h,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 1 0 d d d d d
define pcodeop vasr_VhR;
:vasr VdH_0004,VuH_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x6 & VdH_0004 & VuH_0812 & rx5 & $(END_PACKET) {
VdH_0004 = vasr_VhR(VuH_0812,rx5);
build EndPacket;
}
# (v60,1) vasl -- "Vd.w=vasl(Vu.w,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 1 1 d d d d d
define pcodeop vasl_VwR;
:vasl VdW_0004,VuW_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x7 & VdW_0004 & VuW_0812 & rx5 & $(END_PACKET) {
VdW_0004 = vasl_VwR(VuW_0812,rx5);
build EndPacket;
}
# (v60,1) vasl -- "Vd.h=vasl(Vu.h,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d
define pcodeop vasl_VhR;
:vasl VdH_0004,VuH_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x0 & op0507=0x0 & VdH_0004 & VuH_0812 & rx5 & $(END_PACKET) {
VdH_0004 = vasl_VhR(VuH_0812,rx5);
build EndPacket;
}
# (v60,1) vlsr -- "Vd.uw=vlsr(Vu.uw,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 0 1 d d d d d
define pcodeop vlsr_VuwR;
:vlsr VdUW_0004,VuUW_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x0 & op0507=0x1 & VdUW_0004 & VuUW_0812 & rx5 & $(END_PACKET) {
VdUW_0004 = vlsr_VuwR(VuUW_0812,rx5);
build EndPacket;
}
# (v60,1) vlsr -- "Vd.uh=vlsr(Vu.uh,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 1 0 d d d d d
define pcodeop vlsr_VuhR;
:vlsr VdUH_0004,VuUH_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x0 & op0507=0x2 & VdUH_0004 & VuUH_0812 & rx5 & $(END_PACKET) {
VdUH_0004 = vlsr_VuhR(VuUH_0812,rx5);
build EndPacket;
}
# (v60,1) vlsr -- "Vd.ub=vlsr(Vu.ub,Rt)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 1 1 d d d d d
define pcodeop vlsr_VubR;
:vlsr VdUB_0004,VuUB_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x0 & op0507=0x3 & VdUB_0004 & VuUB_0812 & rx5 & $(END_PACKET) {
VdUB_0004 = vlsr_VubR(VuUB_0812,rx5);
build EndPacket;
}
# (v60,1) vasr -- "Vd.w=vasr(Vu.w,Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d
define pcodeop vasr_VwVw;
:vasr VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x0 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) {
VdW_0004 = vasr_VwVw(VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vlsr -- "Vd.w=vlsr(Vu.w,Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d
define pcodeop vlsr_VwVw;
:vlsr VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x1 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) {
VdW_0004 = vlsr_VwVw(VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vlsr -- "Vd.h=vlsr(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d
define pcodeop vlsr_VhVh;
:vlsr VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x2 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdH_0004 = vlsr_VhVh(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vasr -- "Vd.h=vasr(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d
define pcodeop vasr_VhVh;
:vasr VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x3 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdH_0004 = vasr_VhVh(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vasl -- "Vd.w=vasl(Vu.w,Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d
define pcodeop vasl_VwVw;
:vasl VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x4 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) {
VdW_0004 = vasl_VwVw(VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vasl -- "Vd.h=vasl(Vu.h,Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d
define pcodeop vasl_VhVh;
:vasl VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x5 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdH_0004 = vasl_VhVh(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vasr -- "Vd.uh=vasr(Vuu.w,Vv.uh):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d
define pcodeop Vuh_vasr_WwVuh_sat;
:vasr^":sat" VdUH_0004,VuuW_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x68 & op13=0x0 & op0507=0x0 & VdUH_0004 & VuuW_0812 & VvUH_1620 & $(END_PACKET) {
VdUH_0004 = Vuh_vasr_WwVuh_sat(VuuW_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vasr -- "Vd.uh=vasr(Vuu.w,Vv.uh):rnd:sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d
define pcodeop Vuh_vasr_WwVuh_rnd_sat;
:vasr^":rnd:sat" VdUH_0004,VuuW_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x68 & op13=0x0 & op0507=0x1 & VdUH_0004 & VuuW_0812 & VvUH_1620 & $(END_PACKET) {
VdUH_0004 = Vuh_vasr_WwVuh_rnd_sat(VuuW_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vasr -- "Vd.ub=vasr(Vuu.uh,Vv.ub):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d
define pcodeop Vub_vasr_WuhVub_sat;
:vasr^":sat" VdUB_0004,VuuUH_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x68 & op13=0x0 & op0507=0x2 & VdUB_0004 & VuuUH_0812 & VvUB_1620 & $(END_PACKET) {
VdUB_0004 = Vub_vasr_WuhVub_sat(VuuUH_0812,VvUB_1620);
build EndPacket;
}
# (v60,1) vasr -- "Vd.ub=vasr(Vuu.uh,Vv.ub):rnd:sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d
define pcodeop Vub_vasr_WuhVub_rnd_sat;
:vasr^":rnd:sat" VdUB_0004,VuuUH_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x68 & op13=0x0 & op0507=0x3 & VdUB_0004 & VuuUH_0812 & VvUB_1620 & $(END_PACKET) {
VdUB_0004 = Vub_vasr_WuhVub_rnd_sat(VuuUH_0812,VvUB_1620);
build EndPacket;
}
# (v60,1) "Vd.sf=Vu.qf32"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - 1 0 0 P P 1 u u u u u 0 0 0 d d d d d
define pcodeop Vsf_equals_Vqf32;
:assign VdSF_0004,VuQF32_0812 EndPacket is iclass=0x1 & op2427=0xe & op2123=0x0 & op1620=0x4 & op13=0x1 & op0507=0x0 & VdSF_0004 & VuQF32_0812 & $(END_PACKET) {
VdSF_0004 = Vsf_equals_Vqf32(VuQF32_0812);
build EndPacket;
}
# (v60,1) "Vd.hf=Vu.qf16"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - 1 0 0 P P 1 u u u u u 0 1 1 d d d d d
define pcodeop Vhf_equals_Vqf16;
:assign VdHF_0004,VuQF16_0812 EndPacket is iclass=0x1 & op2427=0xe & op2123=0x0 & op1620=0x4 & op13=0x1 & op0507=0x3 & VdHF_0004 & VuQF16_0812 & $(END_PACKET) {
VdHF_0004 = Vhf_equals_Vqf16(VuQF16_0812);
build EndPacket;
}
# (v60,1) "Vd.hf=Vuu.qf32"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - 1 0 0 P P 1 u u u u u 1 1 0 d d d d d
define pcodeop Vhf_equals_Wqf32;
:assign VdHF_0004,VuuQF32_0812 EndPacket is iclass=0x1 & op2427=0xe & op2123=0x0 & op1620=0x4 & op13=0x1 & op0507=0x6 & VdHF_0004 & VuuQF32_0812 & $(END_PACKET) {
VdHF_0004 = Vhf_equals_Wqf32(VuuQF32_0812);
build EndPacket;
}
# (v60,1) vround -- "Vd.h=vround(Vu.w,Vv.w):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d
define pcodeop Vh_vround_VwVw_sat;
:vround^":sat" VdH_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x4 & VdH_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) {
VdH_0004 = Vh_vround_VwVw_sat(VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vround -- "Vd.uh=vround(Vu.w,Vv.w):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d
define pcodeop Vuh_vround_VwVw_sat;
:vround^":sat" VdUH_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x5 & VdUH_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) {
VdUH_0004 = Vuh_vround_VwVw_sat(VuW_0812,VvW_1620);
build EndPacket;
}
# (v60,1) vround -- "Vd.b=vround(Vu.h,Vv.h):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d
define pcodeop Vb_vround_VhVh_sat;
:vround^":sat" VdB_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x6 & VdB_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdB_0004 = Vb_vround_VhVh_sat(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vround -- "Vd.ub=vround(Vu.h,Vv.h):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d
define pcodeop Vub_vround_VhVh_sat;
:vround^":sat" VdUB_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x7 & VdUB_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdUB_0004 = Vub_vround_VhVh_sat(VuH_0812,VvH_1620);
build EndPacket;
}
# (v60,1) vround -- "Vd.ub=vround(Vu.uh,Vv.uh):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d
define pcodeop Vub_vround_VuhVuh_sat;
:vround^":sat" VdUB_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x0 & op0507=0x3 & VdUB_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) {
VdUB_0004 = Vub_vround_VuhVuh_sat(VuUH_0812,VvUH_1620);
build EndPacket;
}
# (v60,1) vround -- "Vd.uh=vround(Vu.uw,Vv.uw):sat"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d
define pcodeop Vuh_vround_VuwVuw_sat;
:vround^":sat" VdUH_0004,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x0 & op0507=0x4 & VdUH_0004 & VuUW_0812 & VvUW_1620 & $(END_PACKET) {
VdUH_0004 = Vuh_vround_VuwVuw_sat(VuUW_0812,VvUW_1620);
build EndPacket;
}
# (v60,1) vrotr -- "Vd.uw=vrotr(Vu.uw,Vv.uw)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 1 0 1 0 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d
define pcodeop Vuw_vrotr_VuwVuw;
:vrotr VdUW_0004,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x54 & op13=0x1 & op0507=0x7 & VdUW_0004 & VuUW_0812 & VvUW_1620 & $(END_PACKET) {
VdUW_0004 = Vuw_vrotr_VuwVuw(VuUW_0812,VvUW_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vd.qf16=vsub(Vu.qf16,Vv.qf16)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 0 1 d d d d d
define pcodeop Vqf16_vsub_Vqf16Vqf16;
:vsub VdQF16_0004,VuQF16_0812,VvQF16_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x1 & op0507=0x5 & VdQF16_0004 & VuQF16_0812 & VvQF16_1620 & $(END_PACKET) {
VdQF16_0004 = Vqf16_vsub_Vqf16Vqf16(VuQF16_0812,VvQF16_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vd.qf16=vsub(Vu.hf,Vv.hf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 1 0 d d d d d
define pcodeop Vqf16_vsub_VhfVhf;
:vsub VdQF16_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x1 & op0507=0x6 & VdQF16_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) {
VdQF16_0004 = Vqf16_vsub_VhfVhf(VuHF_0812,VvHF_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vd.qf16=vsub(Vu.qf16,Vv.hf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 1 1 d d d d d
define pcodeop Vqf16_vsub_Vqf16Vhf;
:vsub VdQF16_0004,VuQF16_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x1 & op0507=0x7 & VdQF16_0004 & VuQF16_0812 & VvHF_1620 & $(END_PACKET) {
VdQF16_0004 = Vqf16_vsub_Vqf16Vhf(VuQF16_0812,VvHF_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vd.qf32=vsub(Vu.qf32,Vv.qf32)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 1 1 d d d d d
define pcodeop Vqf32_vsub_Vqf32Vqf32;
:vsub VdQF32_0004,VuQF32_0812,VvQF32_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x1 & op0507=0x3 & VdQF32_0004 & VuQF32_0812 & VvQF32_1620 & $(END_PACKET) {
VdQF32_0004 = Vqf32_vsub_Vqf32Vqf32(VuQF32_0812,VvQF32_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vd.qf32=vsub(Vu.sf,Vv.sf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 1 0 0 d d d d d
define pcodeop Vqf32_vsub_VsfVsf;
:vsub VdQF32_0004,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x1 & op0507=0x4 & VdQF32_0004 & VuSF_0812 & VvSF_1620 & $(END_PACKET) {
VdQF32_0004 = Vqf32_vsub_VsfVsf(VuSF_0812,VvSF_1620);
build EndPacket;
}
# (v60,1) vsub -- "Vd.qf32=vsub(Vu.qf32,Vv.sf)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 1 0 1 d d d d d
define pcodeop Vqf32_vsub_Vqf32Vsf;
:vsub VdQF32_0004,VuQF32_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x1 & op0507=0x5 & VdQF32_0004 & VuQF32_0812 & VvSF_1620 & $(END_PACKET) {
VdQF32_0004 = Vqf32_vsub_Vqf32Vsf(VuQF32_0812,VvSF_1620);
build EndPacket;
}
# (v60,1) vcl0 -- "Vd.uw=vcl0(Vu.uw)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 0 1 d d d d d
define pcodeop Vuw_vcl0_Vuw;
:vcl0 VdUW_0004,VuUW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x5 & VdUW_0004 & VuUW_0812 & $(END_PACKET) {
VdUW_0004 = Vuw_vcl0_Vuw(VuUW_0812);
build EndPacket;
}
# (v60,1) vpopcount -- "Vd.h=vpopcount(Vu.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 1 0 d d d d d
define pcodeop Vh_vpopcount_Vh;
:vpopcount VdH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x6 & VdH_0004 & VuH_0812 & $(END_PACKET) {
VdH_0004 = Vh_vpopcount_Vh(VuH_0812);
build EndPacket;
}
# (v60,1) vcl0 -- "Vd.uh=vcl0(Vu.uh)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 1 1 d d d d d
define pcodeop Vuh_vcl0_Vuh;
:vcl0 VdUH_0004,VuUH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x7 & VdUH_0004 & VuUH_0812 & $(END_PACKET) {
VdUH_0004 = Vuh_vcl0_Vuh(VuUH_0812);
build EndPacket;
}
# (v60,1) vnormamt -- "Vd.w=vnormamt(Vu.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 1 1 P P 0 u u u u u 1 0 0 d d d d d
define pcodeop Vw_vnormamt_Vw;
:vnormamt VdW_0004,VuW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0507=0x4 & VdW_0004 & VuW_0812 & $(END_PACKET) {
VdW_0004 = Vw_vnormamt_Vw(VuW_0812);
build EndPacket;
}
# (v60,1) vnormamt -- "Vd.h=vnormamt(Vu.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 0 - - 0 - - - 1 1 P P 0 u u u u u 1 0 1 d d d d d
define pcodeop Vh_vnormamt_Vh;
:vnormamt VdH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0507=0x5 & VdH_0004 & VuH_0812 & $(END_PACKET) {
VdH_0004 = Vh_vnormamt_Vh(VuH_0812);
build EndPacket;
}
# (v60,1) vadd -- "Vd.h=vadd(vclb(Vu.h),Vv.h)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 0 0 d d d d d
define pcodeop vadd_vclb_VhVh;
:vadd VdH_0004,"vclb("^VuH_0812^")",VvH_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x1 & op0507=0x0 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) {
VdH_0004 = vadd_vclb_VhVh(VuH_0812,VvH_1620); # writes vd5_ at issue time; Vd5 commits vd5=vd5_
build EndPacket;
}
# (v60,1) vadd -- "Vd.w=vadd(vclb(Vu.w),Vv.w)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 0 1 d d d d d
define pcodeop vadd_vclb_VwVw;
:vadd VdW_0004,"vclb("^VuW_0812^")",VvW_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x1 & op0507=0x1 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) {
VdW_0004 = vadd_vclb_VwVw(VuW_0812,VvW_1620); # writes vd5_ at issue time; Vd5 commits vd5=vd5_
build EndPacket;
}
# (v60,2) "if (Qv4) vmem(Rt+#s4)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 n 0 t t t t t P P i v v i i i 0 0 0 s s s s s
#
# (v60,2) "if (Qv4) vmem(Rt+#s4):nt=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 n 0 t t t t t P P i v v i i i 0 0 0 s s s s s
#
# (v60,2) "if (!Qv4) vmem(Rt+#s4)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 n 0 t t t t t P P i v v i i i 0 0 1 s s s s s
#
# (v60,2) "if (!Qv4) vmem(Rt+#s4):nt=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 n 0 t t t t t P P i v v i i i 0 0 1 s s s s s
define pcodeop vmemStoreIf; # aligned store of vector bytes where corresponding predicate bit is set
:vmem^".if("^Qv_1112_S05^")"^ntHint22 VAlignMemAddrRxS4,Vs_0004 EndPacket is iclass=0x2 & op2327=0x11 & op21=0 & op0607=0x0 & ntHint22 & Qv_1112_S05 & VAlignMemAddrRxS4 & Vs_0004 & $(END_PACKET) {
build Qv_1112_S05;
build Vs_0004;
build VAlignMemAddrRxS4;
build EndPacket;
<<COMMIT>>
vmemStoreIf(Qv_1112_S05, VAlignMemAddrRxS4, Vs_0004);
}
# (v60,2) "if (Qv4) vmem(Rx++#s3)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 n 0 x x x x x P P - v v i i i 0 0 0 s s s s s
#
# (v60,2) "if (Qv4) vmem(Rx++#s3):nt=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 n 0 x x x x x P P - v v i i i 0 0 0 s s s s s
#
# (v60,2) "if (!Qv4) vmem(Rx++#s3)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 n 0 x x x x x P P - v v i i i 0 0 1 s s s s s
#
# (v60,2) "if (!Qv4) vmem(Rx++#s3):nt=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 n 0 x x x x x P P - v v i i i 0 0 1 s s s s s
:vmem^".if("^Qv_1112_S05^")"^ntHint22 VAlignMemAddrRxAIS3,Vs_0004 EndPacket is iclass=0x2 & op2327=0x13 & op21=0 & op0607=0x0 & ntHint22 & Qv_1112_S05 & VAlignMemAddrRxAIS3 & Vs_0004 & $(END_PACKET) {
build VAlignMemAddrRxAIS3;
build Qv_1112_S05;
build Vs_0004;
build EndPacket;
<<COMMIT>>
build VAlignMemAddrRxAIS3;
vmemStoreIf(Qv_1112_S05, VAlignMemAddrRxAIS3, Vs_0004);
}
# (v60,2) "if (Qv4) vmem(Rx++Mu)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 n 0 x x x x x P P u v v - - - 0 0 0 s s s s s
#
# (v60,2) "if (Qv4) vmem(Rx++Mu):nt=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 n 0 x x x x x P P u v v - - - 0 0 0 s s s s s
#
# (v60,2) "if (!Qv4) vmem(Rx++Mu)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 n 0 x x x x x P P u v v - - - 0 0 1 s s s s s
#
# (v60,2) "if (!Qv4) vmem(Rx++Mu):nt=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 n 0 x x x x x P P u v v - - - 0 0 1 s s s s s
:vmem^".if("^Qv_1112_S05^")"^ntHint22 VAlignMemAddrRxAIMu,Vs_0004 EndPacket is iclass=0x2 & op2327=0x17 & op21=0 & op0607=0x0 & ntHint22 & Qv_1112_S05 & VAlignMemAddrRxAIMu & Vs_0004 & $(END_PACKET) {
build VAlignMemAddrRxAIMu;
build Qv_1112_S05;
build Vs_0004;
build EndPacket;
<<COMMIT>>
build VAlignMemAddrRxAIMu;
vmemStoreIf(Qv_1112_S05, VAlignMemAddrRxAIMu, Vs_0004);
}
# (v60,2) "vmem(Rt+#s4)=Os8.new"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 0 n 1 t t t t t P P i - - i i i 0 0 1 - 0 s s s
:vmem VAlignMemAddrRxS4,VNreg0002 EndPacket is iclass=0x2 & op2327=0x10 & op22=0 & op21=1 & op0507=0x1 & op3=0x0 & VAlignMemAddrRxS4 & VNreg0002 & $(END_PACKET) {
build VAlignMemAddrRxS4;
build EndPacket;
<<COMMIT>>
VAlignMemAddrRxS4 = VNreg0002;
}
# (v60,2) "vmem(Rt+#s4):nt=Os8.new"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 0 n 1 t t t t t P P i - - i i i 0 0 1 - - s s s
:vmem^":nt" VAlignMemAddrRxS4,VNreg0002 EndPacket is iclass=0x2 & op2327=0x10 & op22=1 & op21=1 & op0507=0x1 & VAlignMemAddrRxS4 & VNreg0002 & $(END_PACKET) {
build VAlignMemAddrRxS4;
build EndPacket;
<<COMMIT>>
VAlignMemAddrRxS4 = VNreg0002;
}
# (v60,2) "if (Pv) vmem(Rt+#s4)=Os8.new"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 1 0 0 0 s s s
#
# (v60,2) "if (!Pv) vmem(Rt+#s4)=Os8.new"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 1 1 0 1 s s s
#
# (v60,2) "if (Pv) vmem(Rt+#s4):nt=Os8.new"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 1 0 1 0 s s s
#
# (v60,2) "if (!Pv) vmem(Rt+#s4):nt=Os8.new"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 1 1 1 1 s s s
#
# NOTE: We tie op4=op22 & op3=op5 to reduce the number of constructors
:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxS4,VNreg0002 EndPacket is iclass=0x2 & op2327=0x11 & op21=1 & op0607=0x1 & op4=op22 & op3=op5 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxS4 & VNreg0002 & $(END_PACKET) {
build VPuCond1112_S05;
build VAlignMemAddrRxS4;
build EndPacket;
<<COMMIT_COND>>
build VPuCond1112_S05;
if (ConditionReg == 0) goto <nocommit>;
VAlignMemAddrRxS4 = VNreg0002;
<nocommit>
}
# (v60,2) "vmem(Rx++#s3)=Os8.new"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 0 0 1 - 0 s s s
:vmem VAlignMemAddrRxAIS3,VNreg0002 EndPacket is iclass=0x2 & op2127=0x49 & op0507=0x1 & op3=0x0 & VAlignMemAddrRxAIS3 & VNreg0002 & $(END_PACKET) [ cond=0; ] {
build VAlignMemAddrRxAIS3;
build EndPacket;
<<COMMIT>>
build VAlignMemAddrRxAIS3;
VAlignMemAddrRxAIS3 = VNreg0002;
}
# (v60,2) "vmem(Rx++#s3):nt=Os8.new"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 0 1 1 x x x x x P P - - - i i i 0 0 1 - - s s s
:vmem^":nt" VAlignMemAddrRxAIS3,VNreg0002 EndPacket is iclass=0x2 & op2127=0x4b & op0507=0x1 & VAlignMemAddrRxAIS3 & VNreg0002 & $(END_PACKET) [ cond=0; ] {
build VAlignMemAddrRxAIS3;
build EndPacket;
<<COMMIT>>
build VAlignMemAddrRxAIS3;
VAlignMemAddrRxAIS3 = VNreg0002;
}
# (v60,2) "if (Pv) vmem(Rx++#s3)=Os8.new"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 1 0 0 0 s s s
#
# (v60,2) "if (!Pv) vmem(Rx++#s3)=Os8.new"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 1 1 0 1 s s s
#
# (v60,2) "if (Pv) vmem(Rx++#s3):nt=Os8.new"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 1 0 1 0 s s s
#
# (v60,2) "if (!Pv) vmem(Rx++#s3):nt=Os8.new"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 1 1 1 1 s s s
#
# NOTE: We tie op4=op22 & op3=op5 to reduce the number of constructors
:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxAIS3,VNreg0002 EndPacket is iclass=0x2 & op2327=0x13 & op21=1 & op0607=0x1 & op4=op22 & op3=op5 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxAIS3 & VNreg0002 & $(END_PACKET) [ cond=1; ] {
build VPuCond1112_S05;
build VAlignMemAddrRxAIS3;
build EndPacket;
<<COMMIT_COND>>
build VPuCond1112_S05; # set ConditionReg before any conditional commit below
build VAlignMemAddrRxAIS3; # conditional Rx post-increment
if (ConditionReg == 0) goto <nocommit>;
VAlignMemAddrRxAIS3 = VNreg0002;
<nocommit>
}
# (v60,2) "vmem(Rx++Mu)=Os8.new"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 0 0 1 - 0 s s s
:vmem VAlignMemAddrRxAIMu,VNreg0002 EndPacket is iclass=0x2 & op2127=0x59 & op0507=0x1 & op3=0x0 & VAlignMemAddrRxAIMu & VNreg0002 & $(END_PACKET) [ cond=0; ] {
build VAlignMemAddrRxAIMu;
build EndPacket;
<<COMMIT>>
build VAlignMemAddrRxAIMu;
VAlignMemAddrRxAIMu = VNreg0002;
}
# (v60,2) "vmem(Rx++Mu):nt=Os8.new"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 0 1 1 x x x x x P P u - - - - - 0 0 1 - - s s s
:vmem^":nt" VAlignMemAddrRxAIMu,VNreg0002 EndPacket is iclass=0x2 & op2127=0x5b & op0507=0x1 & VAlignMemAddrRxAIMu & VNreg0002 & $(END_PACKET) [ cond=0; ] {
build VAlignMemAddrRxAIMu;
build EndPacket;
<<COMMIT>>
build VAlignMemAddrRxAIMu;
VAlignMemAddrRxAIMu = VNreg0002;
}
# (v60,2) "if (Pv) vmem(Rx++Mu)=Os8.new"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 1 0 0 0 s s s
#
# (v60,2) "if (!Pv) vmem(Rx++Mu)=Os8.new"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 1 1 0 1 s s s
#
# (v60,2) "if (Pv) vmem(Rx++Mu):nt=Os8.new"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 1 0 1 0 s s s
#
# (v60,2) "if (!Pv) vmem(Rx++Mu):nt=Os8.new"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 1 1 1 1 s s s
#
# NOTE: We tie op4=op22 & op3=op5 to reduce the number of constructors
:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxAIMu,VNreg0002 EndPacket is iclass=0x2 & op2327=0x17 & op21=1 & op0607=0x1 & op4=op22 & op3=op5 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxAIMu & VNreg0002 & $(END_PACKET) [ cond=1; ] {
build VPuCond1112_S05;
build VAlignMemAddrRxAIMu;
build EndPacket;
<<COMMIT_COND>>
build VPuCond1112_S05;
build VAlignMemAddrRxAIMu; # conditionally commit Rx post-increment update
if (ConditionReg == 0) goto <nocommit>;
VAlignMemAddrRxAIMu = VNreg0002;
<nocommit>
}
# (v60,2) "vmem(Rt+#s4)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 0 0 0 s s s s s
#
# (v60,2) "vmem(Rt+#s4):nt=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 0 1 1 t t t t t P P i - - i i i 0 0 0 s s s s s
:vmem^ntHint22 VAlignMemAddrRxS4,Vs_0004 EndPacket is iclass=0x2 & op2327=0x10 & op21=1 & op0507=0x0 & ntHint22 & VAlignMemAddrRxS4 & Vs_0004 & $(END_PACKET) {
build Vs_0004;
build VAlignMemAddrRxS4;
build EndPacket;
<<COMMIT>>
VAlignMemAddrRxS4 = Vs_0004;
}
# (v60,2) "if (Pv) vmem(Rt+#s4)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 0 0 s s s s s
#
# (v60,2) "if (!Pv) vmem(Rt+#s4)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 0 1 s s s s s
#
# (v60,2) "if (Pv) vmem(Rt+#s4):nt=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 0 0 s s s s s
#
# (v60,2) "if (!Pv) vmem(Rt+#s4):nt=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 0 1 s s s s s
:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxS4,Vs_0004 EndPacket is iclass=0x2 & op2327=0x11 & op21=1 & op0607=0x0 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxS4 & Vs_0004 & $(END_PACKET) {
build VPuCond1112_S05;
build Vs_0004;
build VAlignMemAddrRxS4;
build EndPacket;
<<COMMIT_COND>>
build VPuCond1112_S05;
if (ConditionReg == 0) goto <nocommit>;
VAlignMemAddrRxS4 = Vs_0004;
<nocommit>
}
# (v60,2) "vmem(Rx++#s3)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 0 n 1 x x x x x P P - - - i i i 0 0 0 s s s s s
#
# (v60,2) "vmem(Rx++#s3):nt=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 0 n 1 x x x x x P P - - - i i i 0 0 0 s s s s s
:vmem^ntHint22 VAlignMemAddrRxAIS3,Vs_0004 EndPacket is iclass=0x2 & op2327=0x12 & op21=1 & op0507=0x0 & ntHint22 & VAlignMemAddrRxAIS3 & Vs_0004 & $(END_PACKET) [ cond=0; ] {
build VAlignMemAddrRxAIS3;
build Vs_0004;
build EndPacket;
<<COMMIT>>
build VAlignMemAddrRxAIS3;
VAlignMemAddrRxAIS3 = Vs_0004;
}
# (v60,2) "if (Pv) vmem(Rx++#s3)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 0 0 s s s s s
#
# (v60,2) "if (!Pv) vmem(Rx++#s3)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 0 1 s s s s s
#
# (v60,2) "if (Pv) vmem(Rx++#s3):nt=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 0 0 s s s s s
#
# (v60,2) "if (!Pv) vmem(Rx++#s3):nt=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 0 1 s s s s s
:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxAIS3,Vs_0004 EndPacket is iclass=0x2 & op2327=0x13 & op21=1 & op0607=0x0 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxAIS3 & Vs_0004 & $(END_PACKET) [ cond=1; ] {
build VPuCond1112_S05;
build VAlignMemAddrRxAIS3;
build Vs_0004;
build EndPacket;
<<COMMIT_COND>>
build VPuCond1112_S05; # set ConditionReg before any conditional commit below
build VAlignMemAddrRxAIS3; # conditional Rx post-increment
if (ConditionReg == 0) goto <nocommit>;
VAlignMemAddrRxAIS3 = Vs_0004;
<nocommit>
}
# (v60,2) "vmem(Rx++Mu)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 0 0 0 s s s s s
#
# (v60,2) "vmem(Rx++Mu):nt=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 0 1 1 x x x x x P P u - - - - - 0 0 0 s s s s s
:vmem^ntHint22 VAlignMemAddrRxAIMu,Vs_0004 EndPacket is iclass=0x2 & op2327=0x16 & op21=1 & op0507=0x0 & ntHint22 & VAlignMemAddrRxAIMu & Vs_0004 & $(END_PACKET) [ cond=0; ] {
build VAlignMemAddrRxAIMu;
build Vs_0004;
build EndPacket;
<<COMMIT>>
build VAlignMemAddrRxAIMu;
VAlignMemAddrRxAIMu = Vs_0004;
}
# (v60,2) "if (Pv) vmem(Rx++Mu)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 0 0 s s s s s
#
# (v60,2) "if (!Pv) vmem(Rx++Mu)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 0 1 s s s s s
#
# (v60,2) "if (Pv) vmem(Rx++Mu):nt=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 0 0 s s s s s
#
# (v60,2) "if (!Pv) vmem(Rx++Mu):nt=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 0 1 s s s s s
:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxAIMu,Vs_0004 EndPacket is iclass=0x2 & op2327=0x17 & op21=1 & op0607=0x0 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxAIMu & Vs_0004 & $(END_PACKET) [ cond=1; ] {
build VPuCond1112_S05;
build VAlignMemAddrRxAIMu;
build Vs_0004;
build EndPacket;
<<COMMIT_COND>>
build VPuCond1112_S05;
build VAlignMemAddrRxAIMu; # conditionally commit Rx post-increment update
if (ConditionReg == 0) goto <nocommit>;
VAlignMemAddrRxAIMu = Vs_0004;
<nocommit>
}
# (v60,2) "vmemu(Rt+#s4)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 1 1 1 s s s s s
:vmemu VMemAddrRxS4,Vs_0004 EndPacket is iclass=0x2 & op2127=0x41 & op0507=0x7 & VMemAddrRxS4 & Vs_0004 & $(END_PACKET) {
build Vs_0004;
build VMemAddrRxS4;
build EndPacket;
<<COMMIT>>
VMemAddrRxS4 = Vs_0004;
}
# (v60,2) "if (Pv) vmemu(Rt+#s4)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 1 1 0 s s s s s
#
# (v60,2) "if (!Pv) vmemu(Rt+#s4)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 1 1 1 s s s s s
#
:vmemu^VPuCond1112_S05 VMemAddrRxS4,Vs_0004 EndPacket is iclass=0x2 & op2127=0x45 & op0607=0x3 & VPuCond1112_S05 & VMemAddrRxS4 & Vs_0004 & $(END_PACKET) {
build VPuCond1112_S05;
build Vs_0004;
build VMemAddrRxS4;
build EndPacket;
<<COMMIT_COND>>
build VPuCond1112_S05;
if (ConditionReg == 0) goto <nocommit>;
VMemAddrRxS4 = Vs_0004;
<nocommit>
}
# (v60,2) "vmemu(Rx++#s3)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 1 1 1 s s s s s
:vmemu VMemAddrRxAIS3,Vs_0004 EndPacket is iclass=0x2 & op2127=0x49 & op0507=0x7 & VMemAddrRxAIS3 & Vs_0004 & $(END_PACKET) [ cond=0; ] {
build VMemAddrRxAIS3;
build Vs_0004;
build EndPacket;
<<COMMIT>>
build VMemAddrRxAIS3;
VMemAddrRxAIS3 = Vs_0004;
}
#
# (v60,2) "if (Pv) vmemu(Rx++#s3)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 1 1 0 s s s s s
#
# (v60,2) "if (!Pv) vmemu(Rx++#s3)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 1 1 1 s s s s s
:vmemu^VPuCond1112_S05 VMemAddrRxAIS3,Vs_0004 EndPacket is iclass=0x2 & op2127=0x4d & op0607=0x3 & VPuCond1112_S05 & VMemAddrRxAIS3 & Vs_0004 & $(END_PACKET) [ cond=1; ] {
build VPuCond1112_S05;
build VMemAddrRxAIS3;
build Vs_0004;
build EndPacket;
<<COMMIT_COND>>
build VPuCond1112_S05; # set ConditionReg before any conditional commit below
build VMemAddrRxAIS3; # conditional Rx post-increment
if (ConditionReg == 0) goto <nocommit>;
VMemAddrRxAIS3 = Vs_0004;
<nocommit>
}
# (v60,2) "vmemu(Rx++Mu)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 1 1 1 s s s s s
:vmemu VMemAddrRxAIMu,Vs_0004 EndPacket is iclass=0x2 & op2127=0x59 & op0507=0x7 & VMemAddrRxAIMu & Vs_0004 & $(END_PACKET) [ cond=0; ] {
build VMemAddrRxAIMu;
build Vs_0004;
build EndPacket;
<<COMMIT>>
build VMemAddrRxAIMu;
VMemAddrRxAIMu = Vs_0004;
}
# (v60,2) "if (Pv) vmemu(Rx++Mu)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 1 1 0 s s s s s
#
# (v60,2) "if (!Pv) vmemu(Rx++Mu)=Vs"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 1 1 1 s s s s s
:vmemu^VPuCond1112_S05 VMemAddrRxAIMu,Vs_0004 EndPacket is iclass=0x2 & op2127=0x5d & op0607=0x3 & VPuCond1112_S05 & VMemAddrRxAIMu & Vs_0004 & $(END_PACKET) [ cond=1; ] {
build VPuCond1112_S05;
build VMemAddrRxAIMu;
build Vs_0004;
build EndPacket;
<<COMMIT_COND>>
build VPuCond1112_S05; # set ConditionReg before any conditional commit below
build VMemAddrRxAIMu; # conditional Rx post-increment
if (ConditionReg == 0) goto <nocommit>;
VMemAddrRxAIMu = Vs_0004;
<nocommit>
}
#
# NOTE: vmem scatter_release is specific to the V66 to address a V60/V61 pipeline issue where an
# explicit release was required to avoid a scatter storage hazard. These vmem instructions were
# a microarchitectural workaround that existed only for V60-class cores and was never part of the
# stable, forward-compatible HVX ISA.
#
define pcodeop scatter_release;
# (v60,2) vmem -- "vmem(Rt+#s4):scatter_release"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 0 0 1 - 1 - - -
:vmem^":scatter_release" VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op2127=0x41 & op0507=0x1 & op3=0x1 & VAlignMemAddrRxS4 & $(END_PACKET) {
build VAlignMemAddrRxS4;
build EndPacket;
<<COMMIT>>
scatter_release(VAlignMemAddrRxS4);
}
# (v60,2) vmem -- "vmem(Rx++#s3):scatter_release"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 0 0 1 - 1 - - -
:vmem^":scatter_release" VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op2127=0x49 & op0507=0x1 & op3=0x1 & VAlignMemAddrRxAIS3 & $(END_PACKET) {
build VAlignMemAddrRxAIS3;
build EndPacket;
<<COMMIT>>
build VAlignMemAddrRxAIS3;
scatter_release(VAlignMemAddrRxAIS3);
}
# (v60,2) vmem -- "vmem(Rx++Mu):scatter_release"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 0 0 1 - 1 - - -
:vmem^":scatter_release" VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op2127=0x59 & op0507=0x1 & op3=0x1 & VAlignMemAddrRxAIMu & $(END_PACKET) {
build VAlignMemAddrRxAIMu;
build EndPacket;
<<COMMIT>>
build VAlignMemAddrRxAIMu;
scatter_release(VAlignMemAddrRxAIMu);
}
# (hvx,1) valign4 -- "Vd = valign4(Vu, Vv, Rt8)"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 0 1 1 0 0 0 0 0 0 z z t t t P P 0 u u u u u 1 0 1 d d d d d
define pcodeop valign4;
:valign4 Vd5,Vu_0812,Vz_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op2123=0x0 & op13=0x0 & op0507=0x5 & Vd5 & Vu_0812 & Vz_1923 & rt1618 & $(END_PACKET) {
Vd5 = valign4(Vu_0812,Vz_1923,rt1618);
}
Reference in New Issue View Git Blame Copy Permalink