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ghidra/Ghidra/Processors/Hexagon/data/languages/hexagon_right.sinc
ghidra1 ce276c838a GP-7110 Rework of Hexagon module, includes dont-care-bit fixes plus 
added missing instructions
2026-08-25 16:32:29 -04:00

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#
# Second/Right Packed 'EE' Instructions
#
# (v4,right,2,3) add -- "Rd16 = add ( Rs16 , #-1 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 0 1 1 s s s s d d d d
:add Rd4r,rs4r,MinusOne EndPackedRight is iclass2931=1 & op0813=0x33 & Rd4r & MinusOne & rs4r & $(END_PACKED_RIGHT) {
Rd4r = rs4r - 1;
build EndPackedRight;
}
# (v4,right,2,3) add -- "Rd16 = add ( Rs16 , #1 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 0 0 1 s s s s d d d d
:add Rd4r,rs4r,One EndPackedRight is iclass2931=1 & op0813=0x31 & Rd4r & One & rs4r & $(END_PACKED_RIGHT) {
Rd4r = rs4r + 1;
build EndPackedRight;
}
# (v4,right,2,3) add -- "Rd16 = add ( Sp , #u6:2 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 1 0 1 1 i i i i i i d d d d
:add Rd4r,SP,Uimm8_0409_shift2 EndPackedRight is iclass2931=1 & op1013=11 & Rd4r & SP & Uimm8_0409_shift2 & $(END_PACKED_RIGHT) {
Rd4r = SP + zext(Uimm8_0409_shift2);
build EndPackedRight;
}
# (v4,right,2,3) add -- "Rx16 = add ( Rs16 , Rx16 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 0 0 s s s s x x x x
:add Rd4r,rs4r,rd4r EndPackedRight is iclass2931=1 & op0813=0x38 & Rd4r & rd4r & rs4r & $(END_PACKED_RIGHT) {
Rd4r = rs4r + rd4r;
build EndPackedRight;
}
# (v4,right,2,3) add -- "Rx16 = add ( Rx16 , #s7 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 1 0 0 i i i i i i i x x x x
:add Rd4r,rd4r,Simm8_0410 EndPackedRight is iclass2931=1 & op1113=4 & Rd4r & rd4r & Simm8_0410 & $(END_PACKED_RIGHT) {
Rd4r = rd4r + sext(Simm8_0410);
build EndPackedRight;
}
# (v4,right,6,7) allocframe -- "allocframe ( #u5:3 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 1 1 - - - - - - - - - - - - - - - 1 1 1 1 0 i i i i i 0 0 0 0
#
# (v4,right,10,11) allocframe -- "allocframe ( #u5:3 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 1 0 1 - - - - - - - - - - - - - - - 1 1 1 1 0 i i i i i 0 0 0 0
:allocframe Uimm8_0408_shift3 EndPackedRight is op0913=0x1e & op3=0 & op0002=0 & (iclass2931=3 | iclass2931=5) & Uimm8_0408_shift3 & AllocFrameSPU5x8Right & $(END_PACKED_RIGHT) {
build AllocFrameSPU5x8Right; # allocframe(SP, Uimm8_0408_shift3)
build EndPackedRight;
}
# (v4,right,12,13) allocframe -- "allocframe ( #u5:3 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 1 1 0 - - - - - - - - - - - - - - - - 1 1 1 0 i i i i i 0 0 0 0
:allocframe Uimm8_0408_shift3 EndPackedRight is iclass2931=6 & op0912=14 & op3=0 & op0002=0 & Uimm8_0408_shift3 & AllocFrameSPU5x8Right & $(END_PACKED_RIGHT) {
build AllocFrameSPU5x8Right; # allocframe(SP, Uimm8_0408_shift3)
build EndPackedRight;
}
# (v4,right,14,15) allocframe -- "allocframe ( #u5:3 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 1 1 1 - - - - - - - - - - - - - - - 0 1 1 1 0 i i i i i 0 0 0 0
:allocframe Uimm8_0408_shift3 EndPackedRight is iclass2931=7 & op0913=0x0e & op3=0 & op0002=0 & Uimm8_0408_shift3 & AllocFrameSPU5x8Right & $(END_PACKED_RIGHT) {
build AllocFrameSPU5x8Right; # allocframe(SP, Uimm8_0408_shift3);
build EndPackedRight;
}
# (v4,right,2,3) and -- "Rd16 = and ( Rs16 , #1 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 0 1 0 s s s s d d d d
:and Rd4r,rs4r,One EndPackedRight is iclass2931=1 & op0813=0x32 & Rd4r & One & rs4r & $(END_PACKED_RIGHT) {
Rd4r = rs4r & 1;
build EndPackedRight;
}
# (v4,right,2,3) and -- "Rd16 = and ( Rs16 , #255 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 1 1 1 s s s s d d d d
:and Rd4r,rs4r,FF EndPackedRight is iclass2931=1 & op0813=0x37 & Rd4r & FF & rs4r & $(END_PACKED_RIGHT) {
Rd4r = rs4r & 0xff;
build EndPackedRight;
}
# (v4,right,2,3) assign -- "Rd16 = #-1"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 0 0 0 0 0 d d d d
:assign Rd4r,MinusOne EndPackedRight is iclass2931=1 & op13=1 & op0412=0x1a0 & Rd4r & MinusOne & $(END_PACKED_RIGHT) {
Rd4r = -1;
build EndPackedRight;
}
# (v4,right,2,3) assign -- "Rd16 = #u6"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 1 0 1 0 i i i i i i d d d d
:assign Rd4r,Uimm8_0409 EndPackedRight is iclass2931=1 & op1013=10 & Rd4r & Uimm8_0409 & $(END_PACKED_RIGHT) {
Rd4r = zext(Uimm8_0409);
build EndPackedRight;
}
# (v4,right,2,3) assign -- "Rd16 = Rs16"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 0 0 0 s s s s d d d d
:assign Rd4r,rs4r EndPackedRight is iclass2931=1 & op13=1 & op0812=0x10 & Rd4r & rs4r & $(END_PACKED_RIGHT) {
Rd4r = rs4r;
build EndPackedRight;
}
# (v4,right,2,3) assign -- "if ( ! p0 ) Rd16 = #0"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 0 0 1 1 1 d d d d
#
# (v4,right,2,3) assign -- "if ( ! p0 .new ) Rd16 = #0"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 0 0 1 0 1 d d d d
#
# (v4,right,2,3) assign -- "if ( p0 ) Rd16 = #0"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 0 0 1 1 0 d d d d
#
# (v4,right,2,3) assign -- "if ( p0 .new ) Rd16 = #0"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 0 0 1 0 0 d d d d
:assign^P0Cond_N05_S04 rd4r,Zero EndPackedRight is iclass2931=1 & op13=1 & op0612=0x69 & rd4r & Zero & P0Cond_N05_S04 & $(END_PACKED_RIGHT) {
build P0Cond_N05_S04;
build EndPackedRight;
<<COMMIT_COND>>
build P0Cond_N05_S04;
if (ConditionReg == 0) goto <nocommit>;
rd4r = 0;
<nocommit>
}
# (v4,right,2,3) cmp.eq -- "p0 = cmp.eq ( Rs16 , #u2 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 0 1 s s s s - - i i
:cmp.eq P0,rs4r,Uimm8_0001 EndPackedRight is iclass2931=1 & op13=1 & op0812=0x19 & P0 & rs4r & Uimm8_0001 & $(END_PACKED_RIGHT) {
bool:1 = (rs4r == zext(Uimm8_0001));
P0.new = P0.new & (bool * 0xff);
build EndPackedRight;
<<COMMIT>>
P0 = P0.new;
}
# (v4,right,2,3) combine -- "Rdd8 = combine ( #n2 , #u2 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 1 0 0 - i i n n d d d
:combine Rdd3r,Uimm2_0304,Uimm2_0506 EndPackedRight is iclass2931=1 & op0813=0x3c & Uimm2_0304 & Uimm2_0506 & Rdd3r & $(END_PACKED_RIGHT) {
Rdd3r = (zext(Uimm2_0304) << 32) + zext(Uimm2_0506);
build EndPackedRight;
}
# (v4,right,2,3) combine -- "Rdd8 = combine ( #0 , Rs16 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 1 0 1 s s s s 0 d d d
:combine Rdd3r,Zero,rs4r EndPackedRight is iclass2931=1 & op0813=0x3d & op3=0 & rs4r & Rdd3r & Zero & $(END_PACKED_RIGHT) {
Rdd3r = zext(rs4r);
build EndPackedRight;
}
# (v4,right,2,3) combine -- "Rdd8 = combine ( Rs16 , #0 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 1 0 1 s s s s 1 d d d
:combine Rdd3r,rs4r,Zero EndPackedRight is iclass2931=1 & op0813=0x3d & op3=1 & rs4r & Rdd3r & Zero & $(END_PACKED_RIGHT) {
Rdd3r = zext(rs4r) << 32;
build EndPackedRight;
}
# (v4,right,0,1,4,5) dealloc_return -- "dealloc_return"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 0 0 0 0 0 0
:dealloc_return EndPackedRight is iclass31=0 & iclass29=0 & op0013=0x3F40 & DeallocFrameRaw & $(END_PACKED_RIGHT) {
build DeallocFrameRaw;
build EndPackedRight;
<<FLOW>>
return [LR];
}
# (v4,right,2,3) dealloc_return -- "dealloc_return"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 0 0 0 0 0 0
:dealloc_return EndPackedRight is iclass2931=1 & op0013=0x1F40 & DeallocFrameRaw & $(END_PACKED_RIGHT) {
build DeallocFrameRaw;
build EndPackedRight;
<<FLOW>>
return [LR];
}
# (v4,right,0,1,4,5) dealloc_return -- "if ( ! p0 ) dealloc_return"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 0 0 0 1 0 1
#
# (v4,right,0,1,4,5) dealloc_return:nt -- "if ( ! p0 .new ) dealloc_return:nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 0 0 0 1 1 1
#
# (v4,right,0,1,4,5) dealloc_return -- "if ( p0 ) dealloc_return"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 0 0 0 1 0 0
#
# (v4,right,0,1,4,5) dealloc_return:nt -- "if ( p0 .new ) dealloc_return:nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 0 0 0 1 1 0
:dealloc_return^FlowP0Cond_N01_S00^NotTaken01 EndPackedRight is iclass31=0 & iclass29=0 & op0213=0xFD1 & FlowP0Cond_N01_S00 & NotTaken01 & DeallocFrameRawCond & $(END_PACKED_RIGHT) {
build FlowP0Cond_N01_S00;
build DeallocFrameRawCond;
build EndPackedRight;
<<FLOW>>
build FlowP0Cond_N01_S00;
if (ConditionReg == 0) goto <non_flow>;
return [LR];
<non_flow>
}
# (v4,right,2,3) dealloc_return -- "if ( ! p0 ) dealloc_return"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 0 0 0 1 0 1
#
# (v4,right,2,3) dealloc_return:nt -- "if ( ! p0 .new ) dealloc_return:nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 0 0 0 1 1 1
#
# (v4,right,2,3) dealloc_return -- "if ( p0 ) dealloc_return"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 0 0 0 1 0 0
#
# (v4,right,2,3) dealloc_return:nt -- "if ( p0 .new ) dealloc_return:nt"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 0 0 0 1 1 0
:dealloc_return^FlowP0Cond_N01_S00^NotTaken01 EndPackedRight is iclass2931=1 & op0213=0x7D1 & FlowP0Cond_N01_S00 & NotTaken01 & DeallocFrameRawCond & $(END_PACKED_RIGHT) {
build FlowP0Cond_N01_S00;
build DeallocFrameRawCond;
build EndPackedRight;
<<FLOW>>
build FlowP0Cond_N01_S00;
if (ConditionReg == 0) goto <non_flow>;
return [LR];
<non_flow>
}
# (v4,right,0,1,4,5) deallocframe -- "deallocframe"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 0 0 0 0 0 0 0
:deallocframe EndPackedRight is iclass31=0 & iclass29=0 & op0013=0x3F00 & DeallocFrameRaw & $(END_PACKED_RIGHT) {
build DeallocFrameRaw;
build EndPackedRight;
}
# (v4,right,2,3) deallocframe -- "deallocframe"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 0 0 0 0 0 0 0
:deallocframe EndPackedRight is iclass2931=1 & op0013=0x1F00 & DeallocFrameRaw & $(END_PACKED_RIGHT) {
build DeallocFrameRaw;
build EndPackedRight;
}
# (v4,right,0,1,4,5) jumpr -- "jumpr Lr"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 0 0 0 0 0 0
:jumpr LR EndPackedRight is iclass31=0 & iclass29=0 & op0013=0x3FC0 & LR & $(END_PACKED_RIGHT) {
dest:4 = LR;
build EndPackedRight;
<<FLOW>>
return [dest];
}
# (v4,right,2,3) jumpr -- "jumpr Lr"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 0 0 0 0 0 0
:jumpr LR EndPackedRight is iclass2931=1 & op0013=0x1FC0 & LR & $(END_PACKED_RIGHT) {
dest:4 = LR;
build EndPackedRight;
<<FLOW>>
return [dest];
}
# (v4,right,0,1,4,5) jumpr -- "if ( ! p0 ) jumpr Lr"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 0 0 0 1 0 1
#
# (v4,right,0,1,4,5) jumpr:nt -- "if ( ! p0 .new ) jumpr:nt Lr"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 0 0 0 1 1 1
#
# (v4,right,0,1,4,5) jumpr -- "if ( p0 ) jumpr Lr"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 0 0 0 1 0 0
#
# (v4,right,0,1,4,5) jumpr:nt -- "if ( p0 .new ) jumpr:nt Lr"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 0 0 0 1 1 0
# Conditional Return
:jumpr^FlowP0Cond_N01_S00^NotTaken01 LR EndPackedRight is iclass31=0 & iclass29=0 & op0213=0xFF1 & FlowP0Cond_N01_S00 & NotTaken01 & LR & $(END_PACKED_RIGHT) {
dest:4 = LR;
build FlowP0Cond_N01_S00;
build EndPackedRight;
<<FLOW>>
build FlowP0Cond_N01_S00;
if (ConditionReg == 0) goto <non_flow>;
return [dest];
<non_flow>
}
# (v4,right,2,3) jumpr -- "if ( ! p0 ) jumpr Lr"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 0 0 0 1 0 1
#
# (v4,right,2,3) jumpr:nt -- "if ( ! p0 .new ) jumpr:nt Lr"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 0 0 0 1 1 1
#
# (v4,right,2,3) jumpr -- "if ( p0 ) jumpr Lr"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 0 0 0 1 0 0
#
# (v4,right,2,3) jumpr:nt -- "if ( p0 .new ) jumpr:nt Lr"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 0 0 0 1 1 0
:jumpr^FlowP0Cond_N01_S00^NotTaken01 LR EndPackedRight is iclass2931=1 & op0213=0x7F1 & FlowP0Cond_N01_S00 & NotTaken01 & LR & $(END_PACKED_RIGHT) {
dest:4 = LR;
build FlowP0Cond_N01_S00;
build EndPackedRight;
<<FLOW>>
build FlowP0Cond_N01_S00;
if (ConditionReg == 0) goto <non_flow>;
return [dest];
<non_flow>
}
# (v4,right,0,1,4,5) memb -- "Rd16 = memb ( Rs16 + #u3:0 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 - 0 - - - - - - - - - - - - - - - 1 1 0 i i i s s s s d d d d
:memb Rd4r,MemRsRelU3Rb EndPackedRight is iclass31=0 & iclass29=0 & op1113=6 & MemRsRelU3Rb & Rd4r & $(END_PACKED_RIGHT) {
Rd4r = sext(MemRsRelU3Rb);
build EndPackedRight;
}
# (v4,right,2,3) memb -- "Rd16 = memb ( Rs16 + #u3:0 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 0 1 0 i i i s s s s d d d d
:memb Rd4r,MemRsRelU3Rb EndPackedRight is iclass2931=1 & op1113=2 & MemRsRelU3Rb & Rd4r & $(END_PACKED_RIGHT) {
Rd4r = sext(MemRsRelU3Rb);
build EndPackedRight;
}
# (v4,right,6,7) memb -- "memb ( Rs16 + #u4:0 ) = #n1"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 1 1 - - - - - - - - - - - - - - - 1 1 0 0 1 n s s s s i i i i
#
# (v4,right,10,11) memb -- "memb ( Rs16 + #u4:0 ) = #n1"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 1 0 1 - - - - - - - - - - - - - - - 1 1 0 0 1 n s s s s i i i i
:memb MemRsRelU4Rnb,Uimm1_08 EndPackedRight is op0913=0x19 & (iclass2931=3 | iclass2931=5) & MemRsRelU4Rnb & Uimm1_08 & $(END_PACKED_RIGHT) {
MemRsRelU4Rnb = Uimm1_08;
build EndPackedRight;
}
# (v4,right,12,13) memb -- "memb ( Rs16 + #u4:0 ) = #n1"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 1 1 0 - - - - - - - - - - - - - - - - 1 0 0 1 n s s s s i i i i
:memb MemRsRelU4Rnb,Uimm1_08 EndPackedRight is iclass2931=6 & op0912=9 & MemRsRelU4Rnb & Uimm1_08 & $(END_PACKED_RIGHT) {
MemRsRelU4Rnb = Uimm1_08;
build EndPackedRight;
}
# (v4,right,14,15) memb -- "memb ( Rs16 + #u4:0 ) = #n1"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 1 1 1 - - - - - - - - - - - - - - - 0 1 0 0 1 n s s s s i i i i
:memb MemRsRelU4Rnb,Uimm1_08 EndPackedRight is iclass2931=7 & op0913=9 & MemRsRelU4Rnb & Uimm1_08 & $(END_PACKED_RIGHT) {
MemRsRelU4Rnb = Uimm1_08;
build EndPackedRight;
}
# (v4,right,6,7) memb -- "memb ( Rs16 + #u4:0 ) = Rt16"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 1 1 - - - - - - - - - - - - - - - 0 1 i i i i s s s s t t t t
#
# (v4,right,10,11) memb -- "memb ( Rs16 + #u4:0 ) = Rt16"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 1 0 1 - - - - - - - - - - - - - - - 0 1 i i i i s s s s t t t t
:memb MemRsRelU4Rb,rt4r EndPackedRight is op1213=1 & (iclass2931=3 | iclass2931=5) & MemRsRelU4Rb & rt4r & $(END_PACKED_RIGHT) {
MemRsRelU4Rb = rt4r:1;
build EndPackedRight;
}
# (v4,right,8,9) memb -- "memb ( Rs16 + #u4:0 ) = Rt16"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 1 0 0 - - - - - - - - - - - - - - - - 1 i i i i s s s s t t t t
:memb MemRsRelU4Rb,rt4r EndPackedRight is iclass2931=4 & op12=1 & MemRsRelU4Rb & rt4r & $(END_PACKED_RIGHT) {
MemRsRelU4Rb = rt4r:1;
build EndPackedRight;
}
# (v4,right,0,1,4,5) memd -- "Rdd8 = memd ( Sp + #u5:3 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 0 i i i i i d d d
:memd Rdd3r,MemSpRelU5Rd EndPackedRight is iclass31=0 & iclass29=0 & op0813=0x3e & MemSpRelU5Rd & Rdd3r & $(END_PACKED_RIGHT) {
Rdd3r = MemSpRelU5Rd;
build EndPackedRight;
}
# (v4,right,2,3) memd -- "Rdd8 = memd ( Sp + #u5:3 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 0 i i i i i d d d
:memd Rdd3r,MemSpRelU5Rd EndPackedRight is iclass2931=1 & op0813=0x1e & MemSpRelU5Rd & Rdd3r & $(END_PACKED_RIGHT) {
Rdd3r = MemSpRelU5Rd;
build EndPackedRight;
}
# (v4,right,6,7) memd -- "memd ( Sp + #s6:3 ) = Rtt8"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 1 1 - - - - - - - - - - - - - - - 1 0 1 0 1 i i i i i i t t t
#
# (v4,right,10,11) memd -- "memd ( Sp + #s6:3 ) = Rtt8"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 1 0 1 - - - - - - - - - - - - - - - 1 0 1 0 1 i i i i i i t t t
:memd MemSpRelS6Rd,rtt3r EndPackedRight is op0913=0x15 & (iclass2931=3 | iclass2931=5) & MemSpRelS6Rd & rtt3r & $(END_PACKED_RIGHT) {
MemSpRelS6Rd = rtt3r;
build EndPackedRight;
}
# (v4,right,12,13) memd -- "memd ( Sp + #s6:3 ) = Rtt8"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 1 1 0 - - - - - - - - - - - - - - - - 0 1 0 1 i i i i i i t t t
:memd MemSpRelS6Rd,rtt3r EndPackedRight is iclass2931=6 & op0912=5 & MemSpRelS6Rd & rtt3r & $(END_PACKED_RIGHT) {
MemSpRelS6Rd = rtt3r;
build EndPackedRight;
}
# (v4,right,14,15) memd -- "memd ( Sp + #s6:3 ) = Rtt8"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 1 1 1 - - - - - - - - - - - - - - - 0 0 1 0 1 i i i i i i t t t
:memd MemSpRelS6Rd,rtt3r EndPackedRight is iclass2931=7 & op0913=0x05 & MemSpRelS6Rd & rtt3r & $(END_PACKED_RIGHT) {
MemSpRelS6Rd = rtt3r;
build EndPackedRight;
}
# (v4,right,0,1,4,5) memh -- "Rd16 = memh ( Rs16 + #u3:1 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 - 0 - - - - - - - - - - - - - - - 1 0 0 i i i s s s s d d d d
:memh Rd4r,MemRsRelU3Rh EndPackedRight is iclass31=0 & iclass29=0 & op1113=4 & MemRsRelU3Rh & Rd4r & $(END_PACKED_RIGHT) {
Rd4r = sext(MemRsRelU3Rh);
build EndPackedRight;
}
# (v4,right,2,3) memh -- "Rd16 = memh ( Rs16 + #u3:1 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 0 0 0 i i i s s s s d d d d
:memh Rd4r,MemRsRelU3Rh EndPackedRight is iclass2931=1 & op1113=0 & MemRsRelU3Rh & Rd4r & $(END_PACKED_RIGHT) {
Rd4r = sext(MemRsRelU3Rh);
build EndPackedRight;
}
# (v4,right,6,7) memh -- "memh ( Rs16 + #u3:1 ) = Rt16"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 1 1 - - - - - - - - - - - - - - - 1 0 0 i i i s s s s t t t t
#
# (v4,right,10,11) memh -- "memh ( Rs16 + #u3:1 ) = Rt16"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 1 0 1 - - - - - - - - - - - - - - - 1 0 0 i i i s s s s t t t t
:memh MemRsRelU3Rh,rt4r EndPackedRight is op1113=4 & (iclass2931=3 | iclass2931=5) & MemRsRelU3Rh & rt4r & $(END_PACKED_RIGHT) {
MemRsRelU3Rh = rt4r:2;
build EndPackedRight;
}
# (v4,right,12,13) memh -- "memh ( Rs16 + #u3:1 ) = Rt16"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 1 1 0 - - - - - - - - - - - - - - - - 0 0 i i i s s s s t t t t
:memh MemRsRelU3Rh,rt4r EndPackedRight is iclass2931=6 & op1112=0 & MemRsRelU3Rh & rt4r & $(END_PACKED_RIGHT) {
MemRsRelU3Rh = rt4r:2;
build EndPackedRight;
}
# (v4,right,14,15) memh -- "memh ( Rs16 + #u3:1 ) = Rt16"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 1 1 1 - - - - - - - - - - - - - - - 0 0 0 i i i s s s s t t t t
:memh MemRsRelU3Rh,rt4r EndPackedRight is iclass2931=7 & op1113=0 & MemRsRelU3Rh & rt4r & $(END_PACKED_RIGHT) {
MemRsRelU3Rh = rt4r:2;
build EndPackedRight;
}
# (v4,right,0,1,4,5) memub -- "Rd16 = memub ( Rs16 + #u4:0 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 - 0 - - - - - - - - - - - - - - - 0 1 i i i i s s s s d d d d
:memub Rd4r,MemRsRelU4Rb EndPackedRight is iclass31=0 & iclass29=0 & op1213=1 & MemRsRelU4Rb & Rd4r & $(END_PACKED_RIGHT) {
Rd4r = zext(MemRsRelU4Rb);
build EndPackedRight;
}
# (v4,right,0,1,4,5) memuh -- "Rd16 = memuh ( Rs16 + #u3:1 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 - 0 - - - - - - - - - - - - - - - 1 0 1 i i i s s s s d d d d
:memuh Rd4r,MemRsRelU3Rh EndPackedRight is iclass31=0 & iclass29=0 & op1113=5 & MemRsRelU3Rh & Rd4r & $(END_PACKED_RIGHT) {
Rd4r = zext(MemRsRelU3Rh);
build EndPackedRight;
}
# (v4,right,2,3) memuh -- "Rd16 = memuh ( Rs16 + #u3:1 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 0 0 1 i i i s s s s d d d d
:memuh Rd4r,MemRsRelU3Rh EndPackedRight is iclass2931=1 & op1113=1 & MemRsRelU3Rh & Rd4r & $(END_PACKED_RIGHT) {
Rd4r = zext(MemRsRelU3Rh);
build EndPackedRight;
}
# (v4,right,0,1,4,5) memw -- "Rd16 = memw ( Rs16 + #u4:2 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 - 0 - - - - - - - - - - - - - - - 0 0 i i i i s s s s d d d d
:memw Rd4r,MemRsRelU4Rw EndPackedRight is iclass31=0 & iclass29=0 & op1213=0 & MemRsRelU4Rw & Rd4r & $(END_PACKED_RIGHT) {
Rd4r = MemRsRelU4Rw;
build EndPackedRight;
}
# (v4,right,6,7) memw -- "memw ( Rs16 + #u4:2 ) = #n1"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 1 1 - - - - - - - - - - - - - - - 1 1 0 0 0 n s s s s i i i i
#
# (v4,right,10,11) memw -- "memw ( Rs16 + #u4:2 ) = #n1"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 1 0 1 - - - - - - - - - - - - - - - 1 1 0 0 0 n s s s s i i i i
:memw StMemRsRelC15Rw,Uimm1_08 EndPackedRight is op13=1 & op0912=8 & (iclass2931=3 | iclass2931=5) & StMemRsRelC15Rw & Uimm1_08 & $(END_PACKED_RIGHT) {
StMemRsRelC15Rw = zext(Uimm1_08);
build EndPackedRight;
}
# (v4,right,12,13) memw -- "memw ( Rs16 + #u4:2 ) = #n1"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 1 1 0 - - - - - - - - - - - - - - - - 1 0 0 0 n s s s s i i i i
:memw StMemRsRelC15Rw,Uimm1_08 EndPackedRight is iclass2931=6 & op0912=8 & StMemRsRelC15Rw & Uimm1_08 & $(END_PACKED_RIGHT) {
StMemRsRelC15Rw = zext(Uimm1_08);
build EndPackedRight;
}
# (v4,right,14,15) memw -- "memw ( Rs16 + #u4:2 ) = #n1"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 1 1 1 - - - - - - - - - - - - - - - 0 1 0 0 0 n s s s s i i i i
:memw StMemRsRelC15Rw,Uimm1_08 EndPackedRight is iclass2931=7 & op13=0 & op0912=8 & StMemRsRelC15Rw & Uimm1_08 & $(END_PACKED_RIGHT) {
StMemRsRelC15Rw = zext(Uimm1_08);
build EndPackedRight;
}
# (v4,right,8,9) memw -- "memw ( Rs16 + #u4:2 ) = Rt16"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 1 0 0 - - - - - - - - - - - - - - - - 0 i i i i s s s s t t t t
:memw MemRsRelU4Rw,rt4r EndPackedRight is iclass2931=4 & op12=0 & MemRsRelU4Rw & rt4r & $(END_PACKED_RIGHT) {
MemRsRelU4Rw = rt4r;
build EndPackedRight;
}
# (v4,right,6,7) memw -- "memw ( Rs16 + #u4:2 ) = Rt16"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 1 1 - - - - - - - - - - - - - - - 0 0 i i i i s s s s t t t t
#
# (v4,right,10,11) memw -- "memw ( Rs16 + #u4:2 ) = Rt16"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 1 0 1 - - - - - - - - - - - - - - - 0 0 i i i i s s s s t t t t
:memw MemRsRelU4Rw,rt4r EndPackedRight is op1213=0 & (iclass2931=5 | iclass2931=3) & MemRsRelU4Rw & rt4r & $(END_PACKED_RIGHT) {
MemRsRelU4Rw = rt4r;
build EndPackedRight;
}
# (v4,right,0,1,4,5) memw -- "Rd16 = memw ( Sp + #u5:2 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 0 i i i i i d d d d
:memw Rd4r,MemSpRelU5Rw EndPackedRight is iclass31=0 & iclass29=0 & op0913=0x1e & MemSpRelU5Rw & Rd4r & $(END_PACKED_RIGHT) {
Rd4r = MemSpRelU5Rw;
build EndPackedRight;
}
# (v4,right,2,3) memw -- "Rd16 = memw ( Sp + #u5:2 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 0 i i i i i d d d d
:memw Rd4r,MemSpRelU5Rw EndPackedRight is iclass2931=1 & op0913=0x0e & MemSpRelU5Rw & Rd4r & $(END_PACKED_RIGHT) {
Rd4r = MemSpRelU5Rw;
build EndPackedRight;
}
# (v4,right,6,7) memw -- "memw ( Sp + #u5:2 ) = Rt16"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 1 1 - - - - - - - - - - - - - - - 1 0 1 0 0 i i i i i t t t t
#
# (v4,right,10,11) memw -- "memw ( Sp + #u5:2 ) = Rt16"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 1 0 1 - - - - - - - - - - - - - - - 1 0 1 0 0 i i i i i t t t t
:memw MemSpRelU5Rw,rt4r EndPackedRight is op0913=0x14 & (iclass2931=3 | iclass2931=5) & MemSpRelU5Rw & rt4r & $(END_PACKED_RIGHT) {
MemSpRelU5Rw = rt4r;
build EndPackedRight;
}
# (v4,right,12,13) memw -- "memw ( Sp + #u5:2 ) = Rt16"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 1 1 0 - - - - - - - - - - - - - - - - 0 1 0 0 i i i i i t t t t
:memw MemSpRelU5Rw,rt4r EndPackedRight is iclass2931=6 & op0912=4 & MemSpRelU5Rw & rt4r & $(END_PACKED_RIGHT) {
MemSpRelU5Rw = rt4r;
build EndPackedRight;
}
# (v4,right,14,15) memw -- "memw ( Sp + #u5:2 ) = Rt16"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 1 1 1 - - - - - - - - - - - - - - - 0 0 1 0 0 i i i i i t t t t
:memw MemSpRelU5Rw,rt4r EndPackedRight is iclass2931=7 & op0913=0x04 & MemSpRelU5Rw & rt4r & $(END_PACKED_RIGHT) {
MemSpRelU5Rw = rt4r;
build EndPackedRight;
}
# (v4,right,2,3) sxtb -- "Rd16 = sxtb ( Rs16 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 1 0 1 s s s s d d d d
:sxtb Rd4r,rs4r EndPackedRight is iclass2931=1 & op0813=0x35 & rs4r & Rd4r & $(END_PACKED_RIGHT) {
Rd4r = (rs4r << 24) s>> 24;
build EndPackedRight;
}
# (v4,right,2,3) sxth -- "Rd16 = sxth ( Rs16 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 1 0 0 s s s s d d d d
:sxth Rd4r,rs4r EndPackedRight is iclass2931=1 & op0813=0x34 & rs4r & Rd4r & $(END_PACKED_RIGHT) {
Rd4r = (rs4r << 16) s>> 16;
build EndPackedRight;
}
# (v4,right,2,3) zxth -- "Rd16 = zxth ( Rs16 )"
# _________________________________________________________________________________________________
# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 1 1 0 s s s s d d d d
:zxth Rd4r,rs4r EndPackedRight is iclass2931=1 & op0813=0x36 & rs4r & Rd4r & $(END_PACKED_RIGHT) {
Rd4r = rs4r & 0xffff;
build EndPackedRight;
}
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