mirror of
https://github.com/NationalSecurityAgency/ghidra.git
synced 2026-09-28 17:11:11 -09:00
17535 lines
764 KiB
Plaintext
17535 lines
764 KiB
Plaintext
# INFO This file automatically generated by andre on Wed May 8 15:10:16 2024
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# INFO Direct edits to this file may be lost in future updates
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# INFO Command line arguments: ['--cpuid-match', 'AVX512', '--sinc', '--skip-sinc', '../../../../../../../ghidra/Ghidra/Processors/x86/data/languages/avx512_manual.sinc']
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# ADDPD 3-33 PAGE 603 LINE 33411
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define pcodeop vaddpd_avx512vl ;
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:VADDPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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XmmResult = vaddpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
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XmmMask = XmmReg1;
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build XmmOpMask64;
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ZmmReg1 = zext(XmmResult);
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}
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# ADDPD 3-33 PAGE 603 LINE 33414
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:VADDPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x58; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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YmmResult = vaddpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
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YmmMask = YmmReg1;
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build YmmOpMask64;
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ZmmReg1 = zext(YmmResult);
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}
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# ADDPD 3-33 PAGE 603 LINE 33417
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define pcodeop vaddpd_avx512f ;
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:VADDPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x58; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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ZmmResult = vaddpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
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ZmmMask = ZmmReg1;
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build ZmmOpMask64;
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ZmmReg1 = ZmmResult;
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}
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# ADDPS 3-36 PAGE 606 LINE 33562
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define pcodeop vaddps_avx512vl ;
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:VADDPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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XmmResult = vaddps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
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XmmMask = XmmReg1;
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build XmmOpMask32;
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ZmmReg1 = zext(XmmResult);
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}
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# ADDPS 3-36 PAGE 606 LINE 33565
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:VADDPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x58; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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YmmResult = vaddps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst);
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YmmMask = YmmReg1;
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build YmmOpMask32;
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ZmmReg1 = zext(YmmResult);
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}
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# ADDPS 3-36 PAGE 606 LINE 33568
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define pcodeop vaddps_avx512f ;
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:VADDPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x58; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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ZmmResult = vaddps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
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ZmmMask = ZmmReg1;
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build ZmmOpMask32;
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ZmmReg1 = ZmmResult;
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}
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# ADDSD 3-39 PAGE 609 LINE 33721
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define pcodeop vaddsd_avx512f ;
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:VADDSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
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[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
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{
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XmmResult = vaddsd_avx512f( evexV5_XmmReg, XmmReg2_m64 );
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XmmMask = XmmReg1;
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build XmmOpMask64;
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ZmmReg1 = zext(XmmResult);
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}
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# ADDSS 3-41 PAGE 611 LINE 33815
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define pcodeop vaddss_avx512f ;
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:VADDSS XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m32
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[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
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{
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XmmResult = vaddss_avx512f( evexV5_XmmReg, XmmReg2_m32 );
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XmmMask = XmmReg1;
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build XmmOpMask64;
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ZmmReg1 = zext(XmmResult);
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}
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# ANDPD 3-64 PAGE 634 LINE 34827
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define pcodeop vandpd_avx512vl ;
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:VANDPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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XmmResult = vandpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
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XmmMask = XmmReg1;
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build XmmOpMask64;
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ZmmReg1 = zext(XmmResult);
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}
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# ANDPD 3-64 PAGE 634 LINE 34830
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:VANDPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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YmmResult = vandpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
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YmmMask = YmmReg1;
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build YmmOpMask64;
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ZmmReg1 = zext(YmmResult);
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}
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# ANDPD 3-64 PAGE 634 LINE 34833
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define pcodeop vandpd_avx512dq ;
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:VANDPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x54; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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ZmmResult = vandpd_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
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ZmmMask = ZmmReg1;
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build ZmmOpMask64;
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ZmmReg1 = ZmmResult;
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}
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# ANDPS 3-67 PAGE 637 LINE 34953
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define pcodeop vandps_avx512vl ;
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:VANDPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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XmmResult = vandps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
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XmmMask = XmmReg1;
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build XmmOpMask32;
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ZmmReg1 = zext(XmmResult);
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}
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# ANDPS 3-67 PAGE 637 LINE 34956
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:VANDPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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YmmResult = vandps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
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YmmMask = YmmReg1;
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build YmmOpMask32;
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ZmmReg1 = zext(YmmResult);
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}
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# ANDPS 3-67 PAGE 637 LINE 34959
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define pcodeop vandps_avx512dq ;
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:VANDPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x54; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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ZmmResult = vandps_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
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ZmmMask = ZmmReg1;
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build ZmmOpMask32;
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ZmmReg1 = ZmmResult;
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}
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# ANDNPD 3-70 PAGE 640 LINE 35087
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define pcodeop vandnpd_avx512vl ;
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:VANDNPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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XmmResult = vandnpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
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XmmMask = XmmReg1;
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build XmmOpMask64;
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ZmmReg1 = zext(XmmResult);
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}
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# ANDNPD 3-70 PAGE 640 LINE 35090
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:VANDNPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x55; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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YmmResult = vandnpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
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YmmMask = YmmReg1;
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build YmmOpMask64;
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ZmmReg1 = zext(YmmResult);
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}
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# ANDNPD 3-70 PAGE 640 LINE 35093
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define pcodeop vandnpd_avx512dq ;
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:VANDNPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x55; (ZmmReg1 & ZmmOpMask & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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ZmmResult = vandnpd_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
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ZmmMask = ZmmReg1;
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build ZmmOpMask64;
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ZmmReg1 = ZmmResult;
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}
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# ANDNPS 3-73 PAGE 643 LINE 35213
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define pcodeop vandnps_avx512vl ;
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:VANDNPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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XmmResult = vandnps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
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XmmMask = XmmReg1;
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build XmmOpMask32;
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ZmmReg1 = zext(XmmResult);
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}
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# ANDNPS 3-73 PAGE 643 LINE 35216
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:VANDNPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x55; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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YmmResult = vandnps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
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YmmMask = YmmReg1;
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build YmmOpMask32;
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ZmmReg1 = zext(YmmResult);
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}
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# ANDNPS 3-73 PAGE 643 LINE 35219
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define pcodeop vandnps_avx512dq ;
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:VANDNPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x55; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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ZmmResult = vandnps_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
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ZmmMask = ZmmReg1;
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build ZmmOpMask32;
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ZmmReg1 = ZmmResult;
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}
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# CMPPD 3-155 PAGE 725 LINE 39246
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define pcodeop vcmppd_avx512vl ;
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:^VCMPPD_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m64bcst^VCMPPD_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0xC2; KReg_reg ... & XmmReg2_m128_m64bcst; VCMPPD_mon & VCMPPD_op
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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local tmp = vcmppd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst, VCMPPD_op );
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KReg_reg = zext(AVXOpMask[0,2]) & tmp;
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}
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# CMPPD 3-155 PAGE 725 LINE 39250
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:^VCMPPD_mon KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m64bcst^VCMPPD_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & AVXOpMask & evexV5_YmmReg; byte=0xC2; KReg_reg ... & YmmReg2_m256_m64bcst; VCMPPD_mon & VCMPPD_op
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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local tmp = vcmppd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, VCMPPD_op );
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KReg_reg = zext(AVXOpMask[0,4]) & tmp;
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}
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# CMPPD 3-155 PAGE 725 LINE 39254
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define pcodeop vcmppd_avx512f ;
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:^VCMPPD_mon KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst^VCMPPD_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & AVXOpMask & evexV5_ZmmReg; byte=0xC2; KReg_reg ... & ZmmReg2_m512_m64bcst; VCMPPD_mon & VCMPPD_op
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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local tmp = vcmppd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, VCMPPD_op );
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KReg_reg = zext(AVXOpMask[0,8]) & tmp;
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}
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# CMPPS 3-162 PAGE 732 LINE 39613
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define pcodeop vcmpps_avx512vl ;
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:^VCMPPS_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m32bcst^VCMPPS_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0xC2; KReg_reg ... & XmmReg2_m128_m32bcst; VCMPPS_mon & VCMPPS_op
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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local tmp = vcmpps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst, VCMPPS_op );
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KReg_reg = zext(AVXOpMask[0,8]) & tmp;
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}
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# CMPPS 3-162 PAGE 732 LINE 39617
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:^VCMPPS_mon KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m32bcst^VCMPPS_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & AVXOpMask & evexV5_YmmReg; byte=0xC2; KReg_reg ... & YmmReg2_m256_m32bcst; VCMPPS_mon & VCMPPS_op
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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local tmp = vcmpps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst, VCMPPS_op );
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KReg_reg = zext(AVXOpMask[0,8]) & tmp;
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}
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# CMPPS 3-162 PAGE 732 LINE 39621
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define pcodeop vcmpps_avx512f ;
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:^VCMPPS_mon KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst^VCMPPS_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & AVXOpMask & evexV5_ZmmReg; byte=0xC2; KReg_reg ... & ZmmReg2_m512_m32bcst; VCMPPS_mon & VCMPPS_op
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vcmpps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, VCMPPS_op );
|
|
KReg_reg = zext(AVXOpMask[0,16]) & tmp;
|
|
}
|
|
|
|
# CMPSD 3-173 PAGE 743 LINE 40157
|
|
define pcodeop vcmpsd_avx512f ;
|
|
:^VCMPSD_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m64^VCMPSD_op is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0xC2; KReg_reg ... & XmmReg2_m64; VCMPSD_mon & VCMPSD_op
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
local tmp = vcmpsd_avx512f( evexV5_XmmReg, XmmReg2_m64, VCMPSD_op );
|
|
KReg_reg = zext(AVXOpMask[0,1]) & tmp;
|
|
}
|
|
|
|
# CMPSS 3-177 PAGE 747 LINE 40393
|
|
define pcodeop vcmpss_avx512f ;
|
|
:^VCMPSS_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m32^VCMPSS_op is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0xC2; KReg_reg ... & XmmReg2_m32; VCMPSS_mon & VCMPSS_op
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
local tmp = vcmpss_avx512f( evexV5_XmmReg, XmmReg2_m32, VCMPSS_op );
|
|
KReg_reg = zext(AVXOpMask[0,1]) & tmp;
|
|
}
|
|
|
|
# COMISD 3-186 PAGE 756 LINE 40863
|
|
define pcodeop vcomisd_avx512f ;
|
|
:VCOMISD XmmReg1, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x2F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
local tmp:16 = vcomisd_avx512f( XmmReg2_m64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# COMISS 3-188 PAGE 758 LINE 40941
|
|
define pcodeop vcomiss_avx512f ;
|
|
:VCOMISS XmmReg1, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x2F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
local tmp:16 = vcomiss_avx512f( XmmReg2_m32 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# CVTDQ2PD 3-228 PAGE 798 LINE 43080
|
|
define pcodeop vcvtdq2pd_avx512vl ;
|
|
:VCVTDQ2PD XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0xE6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexBType=1; ] # (TupleType HV)
|
|
{
|
|
XmmResult = vcvtdq2pd_avx512vl( XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# CVTDQ2PD 3-228 PAGE 798 LINE 43083
|
|
:VCVTDQ2PD YmmReg1^YmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0xE6; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)
|
|
{
|
|
YmmResult = vcvtdq2pd_avx512vl( XmmReg2_m128_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# CVTDQ2PD 3-228 PAGE 798 LINE 43086
|
|
define pcodeop vcvtdq2pd_avx512f ;
|
|
:VCVTDQ2PD ZmmReg1^ZmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0xE6; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexBType=1; ] # (TupleType HV)
|
|
{
|
|
ZmmResult = vcvtdq2pd_avx512f( YmmReg2_m256_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# CVTDQ2PS 3-232 PAGE 802 LINE 43248
|
|
define pcodeop vcvtdq2ps_avx512vl ;
|
|
:VCVTDQ2PS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvtdq2ps_avx512vl( XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# CVTDQ2PS 3-232 PAGE 802 LINE 43251
|
|
:VCVTDQ2PS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vcvtdq2ps_avx512vl( YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# CVTDQ2PS 3-232 PAGE 802 LINE 43254
|
|
define pcodeop vcvtdq2ps_avx512f ;
|
|
:VCVTDQ2PS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vcvtdq2ps_avx512f( ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# CVTPD2DQ 3-235 PAGE 805 LINE 43414
|
|
define pcodeop vcvtpd2dq_avx512vl ;
|
|
:VCVTPD2DQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvtpd2dq_avx512vl( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# CVTPD2DQ 3-235 PAGE 805 LINE 43417
|
|
:VCVTPD2DQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vcvtpd2dq_avx512vl( YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# CVTPD2DQ 3-235 PAGE 805 LINE 43420
|
|
define pcodeop vcvtpd2dq_avx512f ;
|
|
:VCVTPD2DQ YmmReg1^YmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vcvtpd2dq_avx512f( ZmmReg2_m512_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# CVTPD2PS 3-240 PAGE 810 LINE 43649
|
|
define pcodeop vcvtpd2ps_avx512vl ;
|
|
:VCVTPD2PS XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x5A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvtpd2ps_avx512vl( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# CVTPD2PS 3-240 PAGE 810 LINE 43653
|
|
:VCVTPD2PS XmmReg1^XmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x5A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvtpd2ps_avx512vl( YmmReg2_m256_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# CVTPD2PS 3-240 PAGE 810 LINE 43657
|
|
define pcodeop vcvtpd2ps_avx512f ;
|
|
:VCVTPD2PS YmmReg1^YmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x5A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vcvtpd2ps_avx512f( ZmmReg2_m512_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# CVTPS2DQ 3-246 PAGE 816 LINE 43933
|
|
define pcodeop vcvtps2dq_avx512vl ;
|
|
:VCVTPS2DQ XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvtps2dq_avx512vl( XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# CVTPS2DQ 3-246 PAGE 816 LINE 43936
|
|
:VCVTPS2DQ YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vcvtps2dq_avx512vl( YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# CVTPS2DQ 3-246 PAGE 816 LINE 43939
|
|
define pcodeop vcvtps2dq_avx512f ;
|
|
:VCVTPS2DQ ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vcvtps2dq_avx512f( ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# CVTPS2PD 3-249 PAGE 819 LINE 44104
|
|
define pcodeop vcvtps2pd_avx512vl ;
|
|
:VCVTPS2PD XmmReg1^XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)
|
|
{
|
|
XmmResult = vcvtps2pd_avx512vl( XmmReg2_m64_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# CVTPS2PD 3-249 PAGE 819 LINE 44107
|
|
:VCVTPS2PD YmmReg1^YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)
|
|
{
|
|
YmmResult = vcvtps2pd_avx512vl( XmmReg2_m128_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# CVTPS2PD 3-249 PAGE 819 LINE 44110
|
|
define pcodeop vcvtps2pd_avx512f ;
|
|
:VCVTPS2PD ZmmReg1^ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5A; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)
|
|
{
|
|
ZmmResult = vcvtps2pd_avx512f( YmmReg2_m256_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# CVTSD2SI 3-253 PAGE 823 LINE 44320
|
|
define pcodeop vcvtsd2si_avx512f ;
|
|
:VCVTSD2SI Reg32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x2D; (Reg32 & check_Reg32_dest) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)
|
|
{
|
|
Reg32 = vcvtsd2si_avx512f( XmmReg2_m64 );
|
|
build check_Reg32_dest;
|
|
}
|
|
|
|
# CVTSD2SI 3-253 PAGE 823 LINE 44322
|
|
@ifdef IA64
|
|
:VCVTSD2SI Reg64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x2D; Reg64 ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)
|
|
{
|
|
Reg64 = vcvtsd2si_avx512f( XmmReg2_m64 );
|
|
}
|
|
@endif
|
|
|
|
# CVTSD2SS 3-255 PAGE 825 LINE 44417
|
|
define pcodeop vcvtsd2ss_avx512f ;
|
|
:VCVTSD2SS XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x5A; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vcvtsd2ss_avx512f( evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
XmmResult[0,32] = (zext(XmmOpMask[0,1]) * XmmResult[0,32]) + (zext(!XmmOpMask[0,1]) * XmmMask[0,32]);
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# CVTSI2SD 3-257 PAGE 827 LINE 44522
|
|
define pcodeop vcvtsi2sd_avx512f ;
|
|
:VCVTSI2SD XmmReg1, evexV5_XmmReg, rm32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x2A; (XmmReg1 & ZmmReg1) ... & rm32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
local tmp:16 = vcvtsi2sd_avx512f( evexV5_XmmReg, rm32 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# CVTSI2SD 3-257 PAGE 827 LINE 44525
|
|
@ifdef IA64
|
|
:VCVTSI2SD XmmReg1, evexV5_XmmReg, rm64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x2A; (XmmReg1 & ZmmReg1) ... & rm64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
local tmp:16 = vcvtsi2sd_avx512f( evexV5_XmmReg, rm64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
@endif
|
|
|
|
# CVTSI2SS 3-259 PAGE 829 LINE 44636
|
|
define pcodeop vcvtsi2ss_avx512f ;
|
|
:VCVTSI2SS XmmReg1, evexV5_XmmReg, rm32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x2A; (XmmReg1 & ZmmReg1) ... & rm32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
local tmp:16 = vcvtsi2ss_avx512f( evexV5_XmmReg, rm32 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# CVTSI2SS 3-259 PAGE 829 LINE 44638
|
|
@ifdef IA64
|
|
:VCVTSI2SS XmmReg1, evexV5_XmmReg, rm64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x2A; (XmmReg1 & ZmmReg1) ... & rm64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
local tmp:16 = vcvtsi2ss_avx512f( evexV5_XmmReg, rm64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
@endif
|
|
|
|
# CVTSS2SD 3-261 PAGE 831 LINE 44747
|
|
define pcodeop vcvtss2sd_avx512f ;
|
|
:VCVTSS2SD XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x5A; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vcvtss2sd_avx512f( evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
XmmResult[0,64] = (zext(XmmOpMask[0,1]) * XmmResult[0,64]) + (zext(!XmmOpMask[0,1]) * XmmMask[0,64]);
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# CVTSS2SI 3-263 PAGE 833 LINE 44839
|
|
define pcodeop vcvtss2si_avx512f ;
|
|
:VCVTSS2SI Reg32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x2D; (Reg32 & check_Reg32_dest) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)
|
|
{
|
|
Reg32 = vcvtss2si_avx512f( XmmReg2_m32 );
|
|
build check_Reg32_dest;
|
|
}
|
|
|
|
# CVTSS2SI 3-263 PAGE 833 LINE 44841
|
|
@ifdef IA64
|
|
:VCVTSS2SI Reg64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x2D; Reg64 ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)
|
|
{
|
|
Reg64 = vcvtss2si_avx512f( XmmReg2_m32 );
|
|
}
|
|
@endif
|
|
|
|
# CVTTPD2DQ 3-265 PAGE 835 LINE 44936
|
|
define pcodeop vcvttpd2dq_avx512vl ;
|
|
:VCVTTPD2DQ XmmReg1^XmmOpMask32, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvttpd2dq_avx512vl( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# CVTTPD2DQ 3-265 PAGE 835 LINE 44940
|
|
:VCVTTPD2DQ XmmReg1^XmmOpMask32, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvttpd2dq_avx512vl( YmmReg2_m256_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# CVTTPD2DQ 3-265 PAGE 835 LINE 44944
|
|
define pcodeop vcvttpd2dq_avx512f ;
|
|
:VCVTTPD2DQ YmmReg1^YmmOpMask32, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vcvttpd2dq_avx512f( ZmmReg2_m512_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# CVTTPS2DQ 3-270 PAGE 840 LINE 45169
|
|
define pcodeop vcvttps2dq_avx512vl ;
|
|
:VCVTTPS2DQ XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvttps2dq_avx512vl( XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# CVTTPS2DQ 3-270 PAGE 840 LINE 45173
|
|
:VCVTTPS2DQ YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vcvttps2dq_avx512vl( YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# CVTTPS2DQ 3-270 PAGE 840 LINE 45177
|
|
define pcodeop vcvttps2dq_avx512f ;
|
|
:VCVTTPS2DQ ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vcvttps2dq_avx512f( ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# CVTTSD2SI 3-274 PAGE 844 LINE 45385
|
|
define pcodeop vcvttsd2si_avx512f ;
|
|
:VCVTTSD2SI Reg32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x2C; (Reg32 & check_Reg32_dest) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)
|
|
{
|
|
Reg32 = vcvttsd2si_avx512f( XmmReg2_m64 );
|
|
build check_Reg32_dest;
|
|
}
|
|
|
|
# CVTTSD2SI 3-274 PAGE 844 LINE 45388
|
|
@ifdef IA64
|
|
:VCVTTSD2SI Reg64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x2C; Reg64 ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)
|
|
{
|
|
Reg64 = vcvttsd2si_avx512f( XmmReg2_m64 );
|
|
}
|
|
@endif
|
|
|
|
# CVTTSS2SI 3-276 PAGE 846 LINE 45479
|
|
define pcodeop vcvttss2si_avx512f ;
|
|
:VCVTTSS2SI Reg32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x2C; (Reg32 & check_Reg32_dest) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)
|
|
{
|
|
Reg32 = vcvttss2si_avx512f( XmmReg2_m32 );
|
|
build check_Reg32_dest;
|
|
}
|
|
|
|
# CVTTSS2SI 3-276 PAGE 846 LINE 45482
|
|
@ifdef IA64
|
|
:VCVTTSS2SI Reg64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x2C; Reg64 ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)
|
|
{
|
|
Reg64 = vcvttss2si_avx512f( XmmReg2_m32 );
|
|
}
|
|
@endif
|
|
|
|
# DIVPD 3-288 PAGE 858 LINE 46029
|
|
define pcodeop vdivpd_avx512vl ;
|
|
:VDIVPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vdivpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# DIVPD 3-288 PAGE 858 LINE 46033
|
|
:VDIVPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x5E; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vdivpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# DIVPD 3-288 PAGE 858 LINE 46037
|
|
define pcodeop vdivpd_avx512f ;
|
|
:VDIVPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x5E; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vdivpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# DIVPS 3-291 PAGE 861 LINE 46170
|
|
define pcodeop vdivps_avx512vl ;
|
|
:VDIVPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vdivps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# DIVPS 3-291 PAGE 861 LINE 46174
|
|
:VDIVPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x5E; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vdivps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# DIVPS 3-291 PAGE 861 LINE 46178
|
|
define pcodeop vdivps_avx512f ;
|
|
:VDIVPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x5E; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vdivps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# DIVSD 3-294 PAGE 864 LINE 46315
|
|
define pcodeop vdivsd_avx512f ;
|
|
:VDIVSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vdivsd_avx512f( evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# DIVSS 3-296 PAGE 866 LINE 46413
|
|
define pcodeop vdivss_avx512f ;
|
|
:VDIVSS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vdivss_avx512f( evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# EXTRACTPS 3-307 PAGE 877 LINE 46983
|
|
define pcodeop vextractps_avx512f ;
|
|
:VEXTRACTPS rm32, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x17; XmmReg1 ... & rm32; imm8
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
rm32 = vextractps_avx512f( XmmReg1, imm8:1 );
|
|
}
|
|
|
|
# INSERTPS 3-454 PAGE 1024 LINE 53785
|
|
define pcodeop vinsertps_avx512f ;
|
|
:VINSERTPS XmmReg1, evexV5_XmmReg, XmmReg2_m32, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x21; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32; imm8
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
local tmp:16 = vinsertps_avx512f( evexV5_XmmReg, XmmReg2_m32, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
|
|
# MAXPD 4-12 PAGE 1132 LINE 59206
|
|
define pcodeop vmaxpd_avx512vl ;
|
|
:VMAXPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vmaxpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MAXPD 4-12 PAGE 1132 LINE 59210
|
|
:VMAXPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x5F; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vmaxpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# MAXPD 4-12 PAGE 1132 LINE 59214
|
|
define pcodeop vmaxpd_avx512f ;
|
|
:VMAXPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x5F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vmaxpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# MAXPS 4-15 PAGE 1135 LINE 59356
|
|
define pcodeop vmaxps_avx512vl ;
|
|
:VMAXPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vmaxps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MAXPS 4-15 PAGE 1135 LINE 59359
|
|
:VMAXPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x5F; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vmaxps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# MAXPS 4-15 PAGE 1135 LINE 59362
|
|
define pcodeop vmaxps_avx512f ;
|
|
:VMAXPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x5F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vmaxps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# MAXSD 4-18 PAGE 1138 LINE 59506
|
|
define pcodeop vmaxsd_avx512f ;
|
|
:VMAXSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vmaxsd_avx512f( evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MAXSS 4-20 PAGE 1140 LINE 59609
|
|
define pcodeop vmaxss_avx512f ;
|
|
:VMAXSS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vmaxss_avx512f( evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MINPD 4-23 PAGE 1143 LINE 59771
|
|
define pcodeop vminpd_avx512vl ;
|
|
:VMINPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vminpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MINPD 4-23 PAGE 1143 LINE 59774
|
|
:VMINPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x5D; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vminpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# MINPD 4-23 PAGE 1143 LINE 59777
|
|
define pcodeop vminpd_avx512f ;
|
|
:VMINPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x5D; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vminpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# MINPS 4-26 PAGE 1146 LINE 59915
|
|
define pcodeop vminps_avx512vl ;
|
|
:VMINPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vminps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MINPS 4-26 PAGE 1146 LINE 59918
|
|
:VMINPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x5D; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vminps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# MINPS 4-26 PAGE 1146 LINE 59921
|
|
define pcodeop vminps_avx512f ;
|
|
:VMINPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x5D; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vminps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# MINSD 4-29 PAGE 1149 LINE 60063
|
|
define pcodeop vminsd_avx512f ;
|
|
:VMINSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vminsd_avx512f( evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MINSS 4-31 PAGE 1151 LINE 60166
|
|
define pcodeop vminss_avx512f ;
|
|
:VMINSS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vminss_avx512f( evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MOVAPD 4-45 PAGE 1165 LINE 60852
|
|
:VMOVAPD XmmReg1^XmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x28; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
XmmResult = XmmReg2_m128 ;
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MOVAPD 4-45 PAGE 1165 LINE 60855
|
|
:VMOVAPD YmmReg1^YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x28; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
YmmResult = YmmReg2_m256;
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# MOVAPD 4-45 PAGE 1165 LINE 60858
|
|
define pcodeop vmovapd_avx512f ;
|
|
:VMOVAPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x28; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
ZmmResult = ZmmReg2_m512;
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
:VMOVAPD XmmReg2^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & XmmOpMask64; byte=0x29; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
XmmResult = XmmReg1 ;
|
|
XmmMask = XmmReg2;
|
|
build XmmOpMask64;
|
|
ZmmReg2 = zext(XmmResult);
|
|
}
|
|
|
|
:VMOVAPD m128^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & XmmOpMask64; byte=0x29; XmmReg1 ... & m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
XmmResult = XmmReg1 ;
|
|
XmmMask = m128;
|
|
build XmmOpMask64;
|
|
m128 = XmmResult;
|
|
}
|
|
|
|
# MOVAPD 4-45 PAGE 1165 LINE 60864
|
|
:VMOVAPD YmmReg2^YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & YmmOpMask64; byte=0x29; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
YmmResult = YmmReg1 ;
|
|
YmmMask = YmmReg2;
|
|
build YmmOpMask64;
|
|
ZmmReg2 = zext(YmmResult);
|
|
}
|
|
|
|
:VMOVAPD m256 YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & YmmOpMask64; byte=0x29; YmmReg1 ... & m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
YmmResult = YmmReg1 ;
|
|
YmmMask = m256;
|
|
build YmmOpMask64;
|
|
m256 = YmmResult;
|
|
}
|
|
|
|
# MOVAPD 4-45 PAGE 1165 LINE 60867
|
|
:VMOVAPD ZmmReg2^ZmmOpMask64, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & ZmmOpMask64; byte=0x29; ZmmReg1 & mod=3 & ZmmReg2
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
ZmmResult = ZmmReg1 ;
|
|
ZmmMask = ZmmReg2;
|
|
build ZmmOpMask64;
|
|
ZmmReg2 = ZmmResult;
|
|
}
|
|
|
|
:VMOVAPD m512 ZmmOpMask64, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & ZmmOpMask64; byte=0x29; ZmmReg1 ... & m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
ZmmResult = ZmmReg1 ;
|
|
ZmmMask = m512;
|
|
build ZmmOpMask64;
|
|
m512 = ZmmResult;
|
|
}
|
|
|
|
# MOVAPS 4-49 PAGE 1169 LINE 61047
|
|
:VMOVAPS XmmReg1^XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x28; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
XmmResult = XmmReg2_m128;
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MOVAPS 4-49 PAGE 1169 LINE 61050
|
|
:VMOVAPS YmmReg1^YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x28; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
YmmResult = YmmReg2_m256;
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# MOVAPS 4-49 PAGE 1169 LINE 61053
|
|
define pcodeop vmovaps_avx512f ;
|
|
:VMOVAPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x28; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
ZmmResult = ZmmReg2_m512 ;
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# MOVAPS 4-49 PAGE 1169 LINE 61056
|
|
:VMOVAPS XmmReg2^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & XmmOpMask32; byte=0x29; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
XmmResult = XmmReg1;
|
|
XmmMask = XmmReg2;
|
|
build XmmOpMask32;
|
|
ZmmReg2 = zext(XmmResult);
|
|
}
|
|
|
|
:VMOVAPS m128^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & XmmOpMask32; byte=0x29; (XmmReg1) ... & m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
XmmResult = XmmReg1;
|
|
XmmMask = m128;
|
|
build XmmOpMask32;
|
|
m128 = XmmResult;
|
|
}
|
|
|
|
# MOVAPS 4-49 PAGE 1169 LINE 61059
|
|
:VMOVAPS YmmReg2^YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & YmmOpMask32; byte=0x29; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
YmmResult = YmmReg1;
|
|
YmmMask = YmmReg2;
|
|
build YmmOpMask32;
|
|
ZmmReg2 = zext(YmmResult);
|
|
}
|
|
|
|
:VMOVAPS m256 YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x29; (YmmReg1 & YmmOpMask32) ... & m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
YmmResult = YmmReg1;
|
|
YmmMask = m256;
|
|
build YmmOpMask32;
|
|
m256 = YmmResult;
|
|
}
|
|
|
|
# MOVAPS 4-49 PAGE 1169 LINE 61062
|
|
:VMOVAPS ZmmReg2^ZmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x29; ZmmReg1 & mod=3 & ZmmOpMask32 & ZmmReg2
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
ZmmResult = ZmmReg1 ;
|
|
ZmmMask = ZmmReg2;
|
|
build ZmmOpMask32;
|
|
ZmmReg2 = ZmmResult;
|
|
}
|
|
|
|
:VMOVAPS m512 ZmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x29; (ZmmReg1 & ZmmOpMask32) ... & m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
ZmmResult = ZmmReg1 ;
|
|
ZmmMask = m512;
|
|
build ZmmOpMask32;
|
|
m512 = ZmmResult;
|
|
}
|
|
|
|
# MOVD/MOVQ 4-55 PAGE 1175 LINE 61366
|
|
:VMOVD XmmReg1, rm32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x6E; XmmReg1 ... & rm32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-RM)
|
|
{
|
|
XmmReg1 = zext(rm32);
|
|
}
|
|
|
|
# MOVD/MOVQ 4-55 PAGE 1175 LINE 61368
|
|
@ifdef IA64
|
|
:VMOVQ XmmReg1, rm64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x6E; XmmReg1 ... & rm64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-RM)
|
|
{
|
|
XmmReg1 = zext(rm64);
|
|
}
|
|
@endif
|
|
|
|
# MOVD/MOVQ 4-55 PAGE 1175 LINE 61370
|
|
:VMOVD rm32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7E; (XmmReg1 & check_rm32_dest) ... & rm32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-MR)
|
|
{
|
|
rm32 = XmmReg1[0,32];
|
|
build check_rm32_dest;
|
|
}
|
|
|
|
# MOVD/MOVQ 4-55 PAGE 1175 LINE 61372
|
|
@ifdef IA64
|
|
:VMOVQ rm64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x7E; XmmReg1 ... & rm64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-MR)
|
|
{
|
|
rm64 = XmmReg1[0,64];
|
|
}
|
|
@endif
|
|
|
|
# MOVDDUP 4-59 PAGE 1179 LINE 61526
|
|
define pcodeop vmovddup_avx512vl ;
|
|
:VMOVDDUP XmmReg1^XmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x12; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 13; ] # (TupleType DUP-RM)
|
|
{
|
|
XmmResult = vmovddup_avx512vl( XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MOVDDUP 4-59 PAGE 1179 LINE 61529
|
|
:VMOVDDUP YmmReg1^YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x12; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 13; ] # (TupleType DUP-RM)
|
|
{
|
|
YmmResult = vmovddup_avx512vl( YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# MOVDDUP 4-59 PAGE 1179 LINE 61532
|
|
define pcodeop vmovddup_avx512f ;
|
|
:VMOVDDUP ZmmReg1^ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x12; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 13; ] # (TupleType DUP-RM)
|
|
{
|
|
ZmmResult = vmovddup_avx512f( ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61675
|
|
define pcodeop vmovdqa32_avx512vl ;
|
|
:VMOVDQA32 XmmReg1^XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
XmmResult = vmovdqa32_avx512vl( XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61678
|
|
:VMOVDQA32 YmmReg1^YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
YmmResult = vmovdqa32_avx512vl( YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61681
|
|
define pcodeop vmovdqa32_avx512f ;
|
|
:VMOVDQA32 ZmmReg1^ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
ZmmResult = vmovdqa32_avx512f( ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61684
|
|
:VMOVDQA32 XmmReg2_m128^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (XmmReg1 & XmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
XmmReg2_m128 = vmovdqa32_avx512vl( XmmReg1 );
|
|
}
|
|
|
|
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61687
|
|
:VMOVDQA32 YmmReg2_m256^YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (YmmReg1 & YmmOpMask32) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
YmmReg2_m256 = vmovdqa32_avx512vl( YmmReg1 );
|
|
}
|
|
|
|
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61690
|
|
:VMOVDQA32 ZmmReg2_m512^ZmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
ZmmReg2_m512 = vmovdqa32_avx512f( ZmmReg1 );
|
|
}
|
|
|
|
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61693
|
|
define pcodeop vmovdqa64_avx512vl ;
|
|
:VMOVDQA64 XmmReg1^XmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
XmmResult = vmovdqa64_avx512vl( XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61696
|
|
:VMOVDQA64 YmmReg1^YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
YmmResult = vmovdqa64_avx512vl( YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61699
|
|
define pcodeop vmovdqa64_avx512f ;
|
|
:VMOVDQA64 ZmmReg1^ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
ZmmResult = vmovdqa64_avx512f( ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61702
|
|
:VMOVDQA64 XmmReg2_m128^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (XmmReg1 & XmmOpMask64) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
XmmReg2_m128 = vmovdqa64_avx512vl( XmmReg1 );
|
|
}
|
|
|
|
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61705
|
|
:VMOVDQA64 YmmReg2_m256^YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (YmmReg1 & YmmOpMask64) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
YmmReg2_m256 = vmovdqa64_avx512vl( YmmReg1 );
|
|
}
|
|
|
|
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61708
|
|
:VMOVDQA64 ZmmReg2_m512^ZmmOpMask64, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
ZmmReg2_m512 = vmovdqa64_avx512f( ZmmReg1 );
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61938
|
|
define pcodeop vmovdqu8_avx512vl ;
|
|
:VMOVDQU8 XmmReg1^XmmOpMask8, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
XmmResult = vmovdqu8_avx512vl( XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61941
|
|
:VMOVDQU8 YmmReg1^YmmOpMask8, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
YmmResult = vmovdqu8_avx512vl( YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61944
|
|
define pcodeop vmovdqu8_avx512bw ;
|
|
:VMOVDQU8 ZmmReg1^ZmmOpMask8, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
ZmmResult = vmovdqu8_avx512bw( ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61947
|
|
:VMOVDQU8 XmmReg2_m128^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (XmmReg1 & XmmOpMask8) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
XmmReg2_m128 = vmovdqu8_avx512vl( XmmReg1 );
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61950
|
|
:VMOVDQU8 YmmReg2_m256^YmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (YmmReg1 & YmmOpMask8) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
YmmReg2_m256 = vmovdqu8_avx512vl( YmmReg1 );
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61953
|
|
:VMOVDQU8 ZmmReg2_m512^ZmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
ZmmReg2_m512 = vmovdqu8_avx512bw( ZmmReg1 );
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61956
|
|
define pcodeop vmovdqu16_avx512vl ;
|
|
:VMOVDQU16 XmmReg1^XmmOpMask16, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
XmmResult = vmovdqu16_avx512vl( XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61959
|
|
:VMOVDQU16 YmmReg1^YmmOpMask16, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
YmmResult = vmovdqu16_avx512vl( YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61962
|
|
define pcodeop vmovdqu16_avx512bw ;
|
|
:VMOVDQU16 ZmmReg1^ZmmOpMask16, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
ZmmResult = vmovdqu16_avx512bw( ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61965
|
|
:VMOVDQU16 XmmReg2_m128^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (XmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
XmmReg2_m128 = vmovdqu16_avx512vl( XmmReg1 );
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61968
|
|
:VMOVDQU16 YmmReg2_m256^YmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (YmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
YmmReg2_m256 = vmovdqu16_avx512vl( YmmReg1 );
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61971
|
|
:VMOVDQU16 ZmmReg2_m512^ZmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
ZmmReg2_m512 = vmovdqu16_avx512bw( ZmmReg1 );
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61974
|
|
define pcodeop vmovdqu32_avx512vl ;
|
|
:VMOVDQU32 XmmReg1^XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
XmmResult = vmovdqu32_avx512vl( XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 61987
|
|
:VMOVDQU32 YmmReg1^YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
YmmResult = vmovdqu32_avx512vl( YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 61990
|
|
define pcodeop vmovdqu32_avx512f ;
|
|
:VMOVDQU32 ZmmReg1^ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
ZmmResult = vmovdqu32_avx512f( ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 61993
|
|
:VMOVDQU32 XmmReg2_m128^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (XmmReg1 & XmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
XmmReg2_m128 = vmovdqu32_avx512vl( XmmReg1 );
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 61996
|
|
:VMOVDQU32 YmmReg2_m256^YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (YmmReg1 & YmmOpMask32) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
YmmReg2_m256 = vmovdqu32_avx512vl( YmmReg1 );
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 61999
|
|
:VMOVDQU32 ZmmReg2_m512^ZmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
ZmmReg2_m512 = vmovdqu32_avx512f( ZmmReg1 );
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62002
|
|
define pcodeop vmovdqu64_avx512vl ;
|
|
:VMOVDQU64 XmmReg1^XmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
XmmResult = vmovdqu64_avx512vl( XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62005
|
|
:VMOVDQU64 YmmReg1^YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
YmmResult = vmovdqu64_avx512vl( YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62008
|
|
define pcodeop vmovdqu64_avx512f ;
|
|
:VMOVDQU64 ZmmReg1^ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
ZmmResult = vmovdqu64_avx512f( ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62011
|
|
:VMOVDQU64 XmmReg2_m128^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (XmmReg1 & XmmOpMask64) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
XmmReg2_m128 = vmovdqu64_avx512vl( XmmReg1 );
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62014
|
|
:VMOVDQU64 YmmReg2_m256^YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (YmmReg1 & YmmOpMask64) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
YmmReg2_m256 = vmovdqu64_avx512vl( YmmReg1 );
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62017
|
|
:VMOVDQU64 ZmmReg2_m512^ZmmOpMask64, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
ZmmReg2_m512 = vmovdqu64_avx512f( ZmmReg1 );
|
|
}
|
|
|
|
# MOVHLPS 4-76 PAGE 1196 LINE 62412
|
|
:VMOVHLPS XmmReg1, evexV5_XmmReg, XmmReg2 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x12; (XmmReg1 & ZmmReg1) & (mod=0x3 & XmmReg2)
|
|
{
|
|
local src1 = evexV5_XmmReg[64,64];
|
|
local src2 = XmmReg2[64,64];
|
|
XmmReg1[0,64] = src2;
|
|
XmmReg1[64,64] = src1;
|
|
ZmmReg1 = zext(XmmReg1);
|
|
}
|
|
|
|
# MOVHPD 4-78 PAGE 1198 LINE 62485
|
|
define pcodeop vmovhpd_avx512f ;
|
|
:VMOVHPD XmmReg1, evexV5_XmmReg, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x16; (XmmReg1 & ZmmReg1) ... & m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
local src1 = evexV5_XmmReg[0,64];
|
|
local src2 = m64[0,64];
|
|
XmmReg1[0,64] = src1;
|
|
XmmReg1[64,64] = src2;
|
|
ZmmReg1 = zext(XmmReg1);
|
|
}
|
|
|
|
# MOVHPD 4-78 PAGE 1198 LINE 62491
|
|
:VMOVHPD m64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x17; XmmReg1 ... & m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-MR)
|
|
{
|
|
m64 = vmovhpd_avx512f( XmmReg1 );
|
|
}
|
|
|
|
# MOVHPS 4-80 PAGE 1200 LINE 62572
|
|
define pcodeop vmovhps_avx512f ;
|
|
:VMOVHPS XmmReg1, evexV5_XmmReg, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x16; (XmmReg1 & ZmmReg1) ... & m64
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2)
|
|
{
|
|
XmmResult = vmovhps_avx512f( evexV5_XmmReg, m64 );
|
|
XmmMask = XmmReg1;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MOVHPS 4-80 PAGE 1200 LINE 62578
|
|
:VMOVHPS m64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x17; XmmReg1 ... & m64
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2-MR)
|
|
{
|
|
m64 = vmovhps_avx512f( XmmReg1 );
|
|
}
|
|
|
|
# MOVLHPS 4-82 PAGE 1202 LINE 62660
|
|
# WARNING: duplicate opcode EVEX.NDS.128.0F.W0 16 /r last seen on 4-80 PAGE 1200 LINE 62572 for "VMOVLHPS xmm1, xmm2, xmm3"
|
|
define pcodeop vmovlhps_avx512f ;
|
|
:VMOVLHPS XmmReg1, evexV5_XmmReg, XmmReg2 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x16; (XmmReg1 & ZmmReg1) & (mod=0x3 & XmmReg2)
|
|
{
|
|
local tmp:16 = vmovlhps_avx512f( evexV5_XmmReg, XmmReg2 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MOVLPD 4-84 PAGE 1204 LINE 62733
|
|
define pcodeop vmovlpd_avx512f ;
|
|
:VMOVLPD XmmReg1, evexV5_XmmReg, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x12; (XmmReg1 & ZmmReg1) ... & m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
local tmp:16 = vmovlpd_avx512f( evexV5_XmmReg, m64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MOVLPD 4-84 PAGE 1204 LINE 62739
|
|
:VMOVLPD m64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x13; XmmReg1 ... & m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-MR)
|
|
{
|
|
m64 = vmovlpd_avx512f( XmmReg1 );
|
|
}
|
|
|
|
# MOVLPS 4-86 PAGE 1206 LINE 62818
|
|
# WARNING: duplicate opcode EVEX.NDS.128.0F.W0 12 /r last seen on 4-76 PAGE 1196 LINE 62412 for "VMOVLPS xmm2, xmm1, m64"
|
|
define pcodeop vmovlps_avx512f ;
|
|
:VMOVLPS XmmReg1, evexV5_XmmReg, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x12; (XmmReg1 & ZmmReg1) ... & m64
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2)
|
|
{
|
|
local tmp:16 = vmovlps_avx512f( evexV5_XmmReg, m64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MOVLPS 4-86 PAGE 1206 LINE 62824
|
|
:VMOVLPS m64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x13; XmmReg1 ... & m64
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2-MR)
|
|
{
|
|
m64 = vmovlps_avx512f( XmmReg1 );
|
|
}
|
|
|
|
# MOVNTDQA 4-92 PAGE 1212 LINE 63088
|
|
define pcodeop vmovntdqa_avx512vl ;
|
|
:VMOVNTDQA XmmReg1, m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x2A; (XmmReg1 & ZmmReg1) ... & m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp:16 = vmovntdqa_avx512vl( m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MOVNTDQA 4-92 PAGE 1212 LINE 63090
|
|
:VMOVNTDQA YmmReg1, m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x2A; (YmmReg1 & ZmmReg1) ... & m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp:32 = vmovntdqa_avx512vl( m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MOVNTDQA 4-92 PAGE 1212 LINE 63092
|
|
define pcodeop vmovntdqa_avx512f ;
|
|
:VMOVNTDQA ZmmReg1, m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x2A; ZmmReg1 ... & m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmReg1 = vmovntdqa_avx512f( m512 );
|
|
|
|
}
|
|
|
|
# MOVNTDQ 4-94 PAGE 1214 LINE 63191
|
|
define pcodeop vmovntdq_avx512vl ;
|
|
:VMOVNTDQ m128, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0xE7; XmmReg1 ... & m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
m128 = vmovntdq_avx512vl( XmmReg1 );
|
|
}
|
|
|
|
# MOVNTDQ 4-94 PAGE 1214 LINE 63193
|
|
:VMOVNTDQ m256, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0xE7; YmmReg1 ... & m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
m256 = vmovntdq_avx512vl( YmmReg1 );
|
|
}
|
|
|
|
# MOVNTDQ 4-94 PAGE 1214 LINE 63195
|
|
define pcodeop vmovntdq_avx512f ;
|
|
:VMOVNTDQ m512, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0xE7; ZmmReg1 ... & m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
m512 = vmovntdq_avx512f( ZmmReg1 );
|
|
}
|
|
|
|
# MOVNTPD 4-98 PAGE 1218 LINE 63361
|
|
define pcodeop vmovntpd_avx512vl ;
|
|
:VMOVNTPD m128, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x2B; XmmReg1 ... & m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
m128 = vmovntpd_avx512vl( XmmReg1 );
|
|
}
|
|
|
|
# MOVNTPD 4-98 PAGE 1218 LINE 63363
|
|
:VMOVNTPD m256, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x2B; YmmReg1 ... & m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
m256 = vmovntpd_avx512vl( YmmReg1 );
|
|
}
|
|
|
|
# MOVNTPD 4-98 PAGE 1218 LINE 63365
|
|
define pcodeop vmovntpd_avx512f ;
|
|
:VMOVNTPD m512, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x2B; ZmmReg1 ... & m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
m512 = vmovntpd_avx512f( ZmmReg1 );
|
|
}
|
|
|
|
# MOVNTPS 4-100 PAGE 1220 LINE 63445
|
|
define pcodeop vmovntps_avx512vl ;
|
|
:VMOVNTPS m128, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x2B; XmmReg1 ... & m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
m128 = vmovntps_avx512vl( XmmReg1 );
|
|
}
|
|
|
|
# MOVNTPS 4-100 PAGE 1220 LINE 63447
|
|
:VMOVNTPS m256, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x2B; YmmReg1 ... & m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
m256 = vmovntps_avx512vl( YmmReg1 );
|
|
}
|
|
|
|
# MOVNTPS 4-100 PAGE 1220 LINE 63449
|
|
define pcodeop vmovntps_avx512f ;
|
|
:VMOVNTPS m512, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x2B; ZmmReg1 ... & m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
m512 = vmovntps_avx512f( ZmmReg1 );
|
|
}
|
|
|
|
# MOVQ 4-103 PAGE 1223 LINE 63581
|
|
:VMOVQ XmmReg1, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x7E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-RM)
|
|
{
|
|
ZmmReg1 = zext(XmmReg2_m64[0,64]);
|
|
}
|
|
|
|
# MOVQ 4-103 PAGE 1223 LINE 63587
|
|
:VMOVQ XmmReg2, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0xD6; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-MR)
|
|
{
|
|
ZmmReg2 = zext( XmmReg1[0,64] );
|
|
}
|
|
|
|
:VMOVQ m64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0xD6; XmmReg1 ... & m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-MR)
|
|
{
|
|
m64 = XmmReg1[0,64];
|
|
}
|
|
|
|
# MOVSD 4-111 PAGE 1231 LINE 63978
|
|
define pcodeop vmovsd_avx512f ;
|
|
:VMOVSD XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask) & (mod=0x3 & XmmReg2)
|
|
{
|
|
XmmResult = XmmReg2;
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
XmmResult[0,64] = (zext(XmmOpMask[0,1]) * XmmResult[0,64]) + (zext(!XmmOpMask[0,1]) * XmmMask[0,64]);
|
|
XmmResult[64,64] = evexV5_XmmReg[64,64];
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MOVSD 4-111 PAGE 1231 LINE 63981
|
|
:VMOVSD XmmReg1^XmmOpMask, m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-RM)
|
|
{
|
|
local tmp:8 = m64;
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
tmp = (zext(XmmOpMask[0,1]) * tmp) + (zext(!XmmOpMask[0,1]) * XmmMask[0,64]);
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MOVSD 4-111 PAGE 1231 LINE 63983
|
|
:VMOVSD XmmReg2^XmmOpMask, evexV5_XmmReg, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x11; XmmReg1 & ZmmReg1 & XmmOpMask & (mod=0x3 & XmmReg2)
|
|
{
|
|
XmmResult = XmmReg1;
|
|
XmmMask = XmmReg2;
|
|
build XmmOpMask;
|
|
XmmResult[0,64] = (zext(XmmOpMask[0,1]) * XmmResult[0,64]) + (zext(!XmmOpMask[0,1]) * XmmMask[0,64]);
|
|
XmmResult[64,64] = evexV5_XmmReg[64,64];
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MOVSD 4-111 PAGE 1231 LINE 63986
|
|
:VMOVSD m64^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & XmmOpMask; byte=0x11; XmmReg1 ... & m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-MR)
|
|
{
|
|
XmmResult = vmovsd_avx512f( XmmReg1 );
|
|
local tmp:8 = m64;
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
tmp = (zext(XmmOpMask[0,1]) * tmp) + (zext(!XmmOpMask[0,1]) * XmmMask[0,64]);
|
|
m64 = tmp;
|
|
|
|
}
|
|
|
|
# MOVSHDUP 4-114 PAGE 1234 LINE 64130
|
|
define pcodeop vmovshdup_avx512vl ;
|
|
:VMOVSHDUP XmmReg1^XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x16; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vmovshdup_avx512vl( XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MOVSHDUP 4-114 PAGE 1234 LINE 64133
|
|
:VMOVSHDUP YmmReg1^YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x16; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vmovshdup_avx512vl( YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# MOVSHDUP 4-114 PAGE 1234 LINE 64136
|
|
define pcodeop vmovshdup_avx512f ;
|
|
:VMOVSHDUP ZmmReg1^ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x16; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vmovshdup_avx512f( ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# MOVSLDUP 4-117 PAGE 1237 LINE 64284
|
|
define pcodeop vmovsldup_avx512vl ;
|
|
:VMOVSLDUP XmmReg1^XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x12; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vmovsldup_avx512vl( XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MOVSLDUP 4-117 PAGE 1237 LINE 64287
|
|
:VMOVSLDUP YmmReg1^YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x12; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vmovsldup_avx512vl( YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# MOVSLDUP 4-117 PAGE 1237 LINE 64290
|
|
define pcodeop vmovsldup_avx512f ;
|
|
:VMOVSLDUP ZmmReg1^ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x12; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vmovsldup_avx512f( ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# MOVSS 4-120 PAGE 1240 LINE 64443
|
|
:VMOVSS XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask) & (mod=0x3 & XmmReg2)
|
|
{
|
|
local tmp:4 = XmmReg2[0,32];
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
XmmResult = evexV5_XmmReg;
|
|
XmmResult[0,32] = (zext(XmmOpMask[0,1]) * tmp) + (zext(!XmmOpMask[0,1]) * XmmMask[0,32]);
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MOVSS 4-120 PAGE 1240 LINE 64446
|
|
:VMOVSS XmmReg1^XmmOpMask, m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-RM)
|
|
{
|
|
local tmp:4 = m32;
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
tmp = (zext(XmmOpMask[0,1]) * tmp) + (zext(!XmmOpMask[0,1]) * XmmMask[0,32]);
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MOVSS 4-120 PAGE 1240 LINE 64448
|
|
:VMOVSS XmmReg2^XmmOpMask, evexV5_XmmReg, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x11; XmmReg1 & (mod=0x3 & (XmmReg2 & ZmmReg2))
|
|
{
|
|
local tmp:4 = XmmReg1[0,32];
|
|
XmmMask = XmmReg2;
|
|
build XmmOpMask;
|
|
XmmResult = evexV5_XmmReg;
|
|
XmmResult[0,32] = (zext(XmmOpMask[0,1]) * tmp) + (zext(!XmmOpMask[0,1]) * XmmMask[0,32]);
|
|
ZmmReg2 = zext(XmmResult);
|
|
}
|
|
|
|
# MOVSS 4-120 PAGE 1240 LINE 64451
|
|
:VMOVSS m32^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & XmmOpMask; byte=0x11; XmmReg1 ... & m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-MR)
|
|
{
|
|
local tmp:4 = XmmReg1[0,32];
|
|
XmmMask = zext(m32);
|
|
build XmmOpMask;
|
|
m32 = (zext(XmmOpMask[0,1]) * tmp) + (zext(!XmmOpMask[0,1]) * XmmMask[0,32]);
|
|
}
|
|
|
|
# MOVUPD 4-126 PAGE 1246 LINE 64695
|
|
:VMOVUPD XmmReg1^XmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
XmmResult = XmmReg2_m128 ;
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MOVUPD 4-126 PAGE 1246 LINE 64698
|
|
:VMOVUPD XmmReg2^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & XmmOpMask64; byte=0x11; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
XmmResult = XmmReg1;
|
|
XmmMask = XmmReg2;
|
|
build XmmOpMask64;
|
|
ZmmReg2 = zext(XmmResult);
|
|
}
|
|
|
|
:VMOVUPD m128^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & XmmOpMask64; byte=0x11; (XmmReg1) ... & m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
XmmResult = XmmReg1;
|
|
XmmMask = m128;
|
|
build XmmOpMask64;
|
|
m128 = XmmResult;
|
|
}
|
|
|
|
# MOVUPD 4-126 PAGE 1246 LINE 64701
|
|
:VMOVUPD YmmReg1^YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x10; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
YmmResult = YmmReg2_m256;
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# MOVUPD 4-126 PAGE 1246 LINE 64704
|
|
:VMOVUPD YmmReg2^YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & YmmOpMask64; byte=0x11; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
YmmResult = YmmReg1;
|
|
YmmMask = YmmReg2;
|
|
build YmmOpMask64;
|
|
ZmmReg2 = zext(YmmResult);
|
|
}
|
|
|
|
:VMOVUPD m256 YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & YmmOpMask64; byte=0x11; YmmReg1 ... & m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
YmmResult = YmmReg1;
|
|
YmmMask = m256;
|
|
build YmmOpMask64;
|
|
m256 = YmmResult;
|
|
}
|
|
|
|
# MOVUPD 4-126 PAGE 1246 LINE 64707
|
|
:VMOVUPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x10; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
ZmmResult = ZmmReg2_m512;
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# MOVUPD 4-126 PAGE 1246 LINE 64710
|
|
:VMOVUPD ZmmReg2_m512^ZmmOpMask64, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & ZmmOpMask64; byte=0x11; ZmmReg1 ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
ZmmResult = ZmmReg1;
|
|
ZmmMask = ZmmReg2_m512;
|
|
build ZmmOpMask64;
|
|
ZmmReg2_m512 = ZmmResult;
|
|
}
|
|
|
|
# MOVUPS 4-130 PAGE 1250 LINE 64880
|
|
:VMOVUPS XmmReg1^XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
XmmResult = XmmReg2_m128;
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MOVUPS 4-130 PAGE 1250 LINE 64883
|
|
:VMOVUPS YmmReg1^YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x10; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
YmmResult = YmmReg2_m256;
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# MOVUPS 4-130 PAGE 1250 LINE 64886
|
|
:VMOVUPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x10; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM)
|
|
{
|
|
ZmmResult = ZmmReg2_m512;
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# MOVUPS 4-130 PAGE 1250 LINE 64889
|
|
:VMOVUPS XmmReg2^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & XmmOpMask32; byte=0x11; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
XmmResult = XmmReg1;
|
|
XmmMask = XmmReg2;
|
|
build XmmOpMask32;
|
|
ZmmReg2 = zext(XmmResult);
|
|
}
|
|
|
|
:VMOVUPS m128^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & XmmOpMask32; byte=0x11; XmmReg1 ... & m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
XmmResult = XmmReg1;
|
|
XmmMask = m128;
|
|
build XmmOpMask32;
|
|
m128 = XmmResult;
|
|
}
|
|
|
|
# MOVUPS 4-130 PAGE 1250 LINE 64892
|
|
:VMOVUPS YmmReg2^YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & YmmOpMask32; byte=0x11; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
YmmResult = YmmReg1;
|
|
YmmMask = YmmReg2;
|
|
build YmmOpMask32;
|
|
ZmmReg2 = zext(YmmResult);
|
|
}
|
|
|
|
:VMOVUPS m256 YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & YmmOpMask32; byte=0x11; YmmReg1 ... & m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
YmmResult = YmmReg1;
|
|
YmmMask = m256;
|
|
build YmmOpMask32;
|
|
m256 = YmmResult;
|
|
}
|
|
|
|
# MOVUPS 4-130 PAGE 1250 LINE 64895
|
|
:VMOVUPS ZmmReg2_m512^ZmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & ZmmOpMask32; byte=0x11; ZmmReg1 ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR)
|
|
{
|
|
ZmmResult = ZmmReg1;
|
|
ZmmMask = ZmmReg2_m512;
|
|
build ZmmOpMask32;
|
|
ZmmReg2_m512 = ZmmResult;
|
|
}
|
|
|
|
# MULPD 4-146 PAGE 1266 LINE 65686
|
|
define pcodeop vmulpd_avx512vl ;
|
|
:VMULPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vmulpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MULPD 4-146 PAGE 1266 LINE 65689
|
|
:VMULPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x59; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vmulpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# MULPD 4-146 PAGE 1266 LINE 65692
|
|
define pcodeop vmulpd_avx512f ;
|
|
:VMULPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x59; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vmulpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# MULPS 4-149 PAGE 1269 LINE 65817
|
|
define pcodeop vmulps_avx512vl ;
|
|
:VMULPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vmulps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MULPS 4-149 PAGE 1269 LINE 65820
|
|
:VMULPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x59; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vmulps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# MULPS 4-149 PAGE 1269 LINE 65823
|
|
define pcodeop vmulps_avx512f ;
|
|
:VMULPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x59; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vmulps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# MULSD 4-152 PAGE 1272 LINE 65959
|
|
define pcodeop vmulsd_avx512f ;
|
|
:VMULSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vmulsd_avx512f( evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# MULSS 4-154 PAGE 1274 LINE 66055
|
|
define pcodeop vmulss_avx512f ;
|
|
:VMULSS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vmulss_avx512f( evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# ORPD 4-168 PAGE 1288 LINE 66724
|
|
:VORPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = evexV5_XmmReg | XmmReg2_m128_m64bcst;
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# ORPD 4-168 PAGE 1288 LINE 66727
|
|
:VORPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = evexV5_YmmReg | YmmReg2_m256_m64bcst;
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# ORPD 4-168 PAGE 1288 LINE 66730
|
|
:VORPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x56; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = evexV5_ZmmReg | ZmmReg2_m512_m64bcst;
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# ORPS 4-171 PAGE 1291 LINE 66850
|
|
:VORPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = evexV5_XmmReg | XmmReg2_m128_m32bcst;
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# ORPS 4-171 PAGE 1291 LINE 66853
|
|
:VORPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = evexV5_YmmReg | YmmReg2_m256_m32bcst;
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# ORPS 4-171 PAGE 1291 LINE 66856
|
|
:VORPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x56; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = evexV5_ZmmReg | ZmmReg2_m512_m32bcst;
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67320
|
|
define pcodeop vpabsb_avx512vl ;
|
|
:VPABSB XmmReg1^XmmOpMask8, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1C; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpabsb_avx512vl( XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67323
|
|
:VPABSB YmmReg1^YmmOpMask8, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1C; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpabsb_avx512vl( YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67326
|
|
define pcodeop vpabsb_avx512bw ;
|
|
:VPABSB ZmmReg1^ZmmOpMask8, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1C; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpabsb_avx512bw( ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67329
|
|
define pcodeop vpabsw_avx512vl ;
|
|
:VPABSW XmmReg1^XmmOpMask16, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1D; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpabsw_avx512vl( XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67344
|
|
:VPABSW YmmReg1^YmmOpMask16, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1D; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpabsw_avx512vl( YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67347
|
|
define pcodeop vpabsw_avx512bw ;
|
|
:VPABSW ZmmReg1^ZmmOpMask16, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1D; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpabsw_avx512bw( ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67350
|
|
define pcodeop vpabsd_avx512vl ;
|
|
:VPABSD XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1E; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpabsd_avx512vl( XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67353
|
|
:VPABSD YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1E; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpabsd_avx512vl( YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67357
|
|
define pcodeop vpabsd_avx512f ;
|
|
:VPABSD ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1E; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpabsd_avx512f( ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67360
|
|
define pcodeop vpabsq_avx512vl ;
|
|
:VPABSQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpabsq_avx512vl( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67363
|
|
:VPABSQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1F; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpabsq_avx512vl( YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67366
|
|
define pcodeop vpabsq_avx512f ;
|
|
:VPABSQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpabsq_avx512f( ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67645
|
|
define pcodeop vpacksswb_avx512vl ;
|
|
:VPACKSSWB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0x63; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpacksswb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67649
|
|
:VPACKSSWB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0x63; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpacksswb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67653
|
|
define pcodeop vpacksswb_avx512bw ;
|
|
:VPACKSSWB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x63; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpacksswb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67657
|
|
define pcodeop vpackssdw_avx512vl ;
|
|
:VPACKSSDW XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x6B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpackssdw_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PACKSSWB/PACKSSDW 4-187 PAGE 1307 LINE 67674
|
|
:VPACKSSDW YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x6B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpackssdw_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PACKSSWB/PACKSSDW 4-187 PAGE 1307 LINE 67678
|
|
define pcodeop vpackssdw_avx512bw ;
|
|
:VPACKSSDW ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x6B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpackssdw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PACKUSDW 4-194 PAGE 1314 LINE 68094
|
|
define pcodeop vpackusdw_avx512vl ;
|
|
:VPACKUSDW XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x2B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpackusdw_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PACKUSDW 4-194 PAGE 1314 LINE 68098
|
|
:VPACKUSDW YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x2B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpackusdw_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PACKUSDW 4-194 PAGE 1314 LINE 68103
|
|
define pcodeop vpackusdw_avx512bw ;
|
|
:VPACKUSDW ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x2B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpackusdw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PACKUSWB 4-199 PAGE 1319 LINE 68374
|
|
define pcodeop vpackuswb_avx512vl ;
|
|
:VPACKUSWB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0x67; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpackuswb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PACKUSWB 4-199 PAGE 1319 LINE 68378
|
|
:VPACKUSWB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0x67; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpackuswb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PACKUSWB 4-199 PAGE 1319 LINE 68382
|
|
define pcodeop vpackuswb_avx512bw ;
|
|
:VPACKUSWB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x67; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpackuswb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68674
|
|
define pcodeop vpaddb_avx512vl ;
|
|
:VPADDB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xFC; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpaddb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68677
|
|
define pcodeop vpaddw_avx512vl ;
|
|
:VPADDW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xFD; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpaddw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68680
|
|
define pcodeop vpaddd_avx512vl ;
|
|
:VPADDD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xFE; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpaddd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68683
|
|
define pcodeop vpaddq_avx512vl ;
|
|
:VPADDQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xD4; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpaddq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68686
|
|
:VPADDB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xFC; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpaddb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68689
|
|
:VPADDW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xFD; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpaddw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68692
|
|
:VPADDD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xFE; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpaddd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PADDB/PADDW/PADDD/PADDQ 4-205 PAGE 1325 LINE 68707
|
|
:VPADDQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xD4; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpaddq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PADDB/PADDW/PADDD/PADDQ 4-205 PAGE 1325 LINE 68710
|
|
define pcodeop vpaddb_avx512bw ;
|
|
:VPADDB ZmmReg1^ZmmOpMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xFC; (ZmmReg1 & ZmmOpMask) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpaddb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PADDB/PADDW/PADDD/PADDQ 4-205 PAGE 1325 LINE 68713
|
|
define pcodeop vpaddw_avx512bw ;
|
|
:VPADDW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xFD; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpaddw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PADDB/PADDW/PADDD/PADDQ 4-205 PAGE 1325 LINE 68716
|
|
define pcodeop vpaddd_avx512f ;
|
|
:VPADDD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xFE; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpaddd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PADDB/PADDW/PADDD/PADDQ 4-205 PAGE 1325 LINE 68719
|
|
define pcodeop vpaddq_avx512f ;
|
|
:VPADDQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xD4; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpaddq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PADDSB/PADDSW 4-211 PAGE 1331 LINE 69051
|
|
define pcodeop vpaddsb_avx512vl ;
|
|
:VPADDSB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xEC; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpaddsb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PADDSB/PADDSW 4-211 PAGE 1331 LINE 69054
|
|
:VPADDSB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xEC; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpaddsb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PADDSB/PADDSW 4-211 PAGE 1331 LINE 69057
|
|
define pcodeop vpaddsb_avx512bw ;
|
|
:VPADDSB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xEC; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpaddsb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PADDSB/PADDSW 4-211 PAGE 1331 LINE 69060
|
|
define pcodeop vpaddsw_avx512vl ;
|
|
:VPADDSW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xED; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpaddsw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PADDSB/PADDSW 4-211 PAGE 1331 LINE 69063
|
|
:VPADDSW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xED; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpaddsw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PADDSB/PADDSW 4-211 PAGE 1331 LINE 69066
|
|
define pcodeop vpaddsw_avx512bw ;
|
|
:VPADDSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xED; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpaddsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69269
|
|
define pcodeop vpaddusb_avx512vl ;
|
|
:VPADDUSB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xDC; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpaddusb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69273
|
|
:VPADDUSB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xDC; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpaddusb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69277
|
|
define pcodeop vpaddusb_avx512bw ;
|
|
:VPADDUSB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xDC; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpaddusb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69281
|
|
define pcodeop vpaddusw_avx512vl ;
|
|
:VPADDUSW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xDD; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpaddusw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69285
|
|
:VPADDUSW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xDD; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpaddusw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PADDUSB/PADDUSW 4-216 PAGE 1336 LINE 69302
|
|
define pcodeop vpaddusw_avx512bw ;
|
|
:VPADDUSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xDD; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpaddusw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PALIGNR 4-219 PAGE 1339 LINE 69495
|
|
define pcodeop vpalignr_avx512vl ;
|
|
:VPALIGNR XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_XmmReg; byte=0x0F; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpalignr_avx512vl( evexV5_XmmReg, XmmReg2_m128, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PALIGNR 4-219 PAGE 1339 LINE 69499
|
|
:VPALIGNR YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_YmmReg; byte=0x0F; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpalignr_avx512vl( evexV5_YmmReg, YmmReg2_m256, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PALIGNR 4-219 PAGE 1339 LINE 69505
|
|
define pcodeop vpalignr_avx512bw ;
|
|
:VPALIGNR ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x0F; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpalignr_avx512bw( evexV5_ZmmReg, ZmmReg2_m512, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
|
|
# PAND 4-223 PAGE 1343 LINE 69684
|
|
define pcodeop vpandd_avx512vl ;
|
|
:VPANDD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xDB; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpandd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PAND 4-223 PAGE 1343 LINE 69687
|
|
:VPANDD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xDB; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpandd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PAND 4-223 PAGE 1343 LINE 69690
|
|
define pcodeop vpandd_avx512f ;
|
|
:VPANDD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xDB; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpandd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PAND 4-223 PAGE 1343 LINE 69693
|
|
define pcodeop vpandq_avx512vl ;
|
|
:VPANDQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xDB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpandq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PAND 4-223 PAGE 1343 LINE 69696
|
|
:VPANDQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xDB; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpandq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PAND 4-223 PAGE 1343 LINE 69699
|
|
define pcodeop vpandq_avx512f ;
|
|
:VPANDQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xDB; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpandq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PANDN 4-226 PAGE 1346 LINE 69859
|
|
define pcodeop vpandnd_avx512vl ;
|
|
:VPANDND XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xDF; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpandnd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PANDN 4-226 PAGE 1346 LINE 69862
|
|
:VPANDND YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xDF; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpandnd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PANDN 4-226 PAGE 1346 LINE 69865
|
|
define pcodeop vpandnd_avx512f ;
|
|
:VPANDND ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xDF; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpandnd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PANDN 4-226 PAGE 1346 LINE 69868
|
|
define pcodeop vpandnq_avx512vl ;
|
|
:VPANDNQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xDF; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpandnq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PANDN 4-226 PAGE 1346 LINE 69871
|
|
:VPANDNQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xDF; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpandnq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PANDN 4-226 PAGE 1346 LINE 69874
|
|
define pcodeop vpandnq_avx512f ;
|
|
:VPANDNQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xDF; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpandnq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PAVGB/PAVGW 4-230 PAGE 1350 LINE 70097
|
|
define pcodeop vpavgb_avx512vl ;
|
|
:VPAVGB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xE0; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpavgb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PAVGB/PAVGW 4-230 PAGE 1350 LINE 70100
|
|
:VPAVGB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xE0; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpavgb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PAVGB/PAVGW 4-230 PAGE 1350 LINE 70103
|
|
define pcodeop vpavgb_avx512bw ;
|
|
:VPAVGB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE0; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpavgb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PAVGB/PAVGW 4-230 PAGE 1350 LINE 70106
|
|
define pcodeop vpavgw_avx512vl ;
|
|
:VPAVGW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xE3; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpavgw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PAVGB/PAVGW 4-230 PAGE 1350 LINE 70109
|
|
:VPAVGW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xE3; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpavgw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PAVGB/PAVGW 4-230 PAGE 1350 LINE 70112
|
|
define pcodeop vpavgw_avx512bw ;
|
|
:VPAVGW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE3; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpavgw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70841
|
|
define pcodeop vpcmpeqd_avx512vl ;
|
|
:VPCMPEQD KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0x76; KReg_reg ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpeqd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
KReg_reg = zext(AVXOpMask[0,4]) & tmp;
|
|
|
|
}
|
|
|
|
# PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70846
|
|
:VPCMPEQD KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & AVXOpMask & evexV5_YmmReg; byte=0x76; KReg_reg ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpeqd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
KReg_reg = zext(AVXOpMask[0,8]) & tmp;
|
|
}
|
|
|
|
# PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70851
|
|
define pcodeop vpcmpeqd_avx512f ;
|
|
:VPCMPEQD KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & AVXOpMask & evexV5_ZmmReg; byte=0x76; KReg_reg ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpeqd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
KReg_reg = zext(AVXOpMask[0,16]) & tmp;
|
|
}
|
|
|
|
# PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70855
|
|
define pcodeop vpcmpeqb_avx512vl ;
|
|
:VPCMPEQB KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_XmmReg; byte=0x74; KReg_reg ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpeqb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
KReg_reg = zext(AVXOpMask[0,16]) & tmp;
|
|
}
|
|
|
|
# PCMPEQB/PCMPEQW/PCMPEQD 4-245 PAGE 1365 LINE 70873
|
|
:VPCMPEQB KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_YmmReg; byte=0x74; KReg_reg ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpeqb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
KReg_reg = zext(AVXOpMask[0,32]) & tmp;
|
|
}
|
|
|
|
# PCMPEQB/PCMPEQW/PCMPEQD 4-245 PAGE 1365 LINE 70878
|
|
define pcodeop vpcmpeqb_avx512bw ;
|
|
:VPCMPEQB KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_ZmmReg; byte=0x74; KReg_reg ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpeqb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
KReg_reg = zext(AVXOpMask[0,64]) & tmp;
|
|
}
|
|
|
|
# PCMPEQB/PCMPEQW/PCMPEQD 4-245 PAGE 1365 LINE 70883
|
|
define pcodeop vpcmpeqw_avx512vl ;
|
|
:VPCMPEQW KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_XmmReg; byte=0x75; KReg_reg ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpeqw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
KReg_reg = zext(AVXOpMask[0,8]) & tmp;
|
|
}
|
|
|
|
# PCMPEQB/PCMPEQW/PCMPEQD 4-245 PAGE 1365 LINE 70888
|
|
:VPCMPEQW KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_YmmReg; byte=0x75; KReg_reg ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpeqw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
KReg_reg = zext(AVXOpMask[0,16]) & tmp;
|
|
}
|
|
|
|
# PCMPEQB/PCMPEQW/PCMPEQD 4-245 PAGE 1365 LINE 70893
|
|
define pcodeop vpcmpeqw_avx512bw ;
|
|
:VPCMPEQW KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_ZmmReg; byte=0x75; KReg_reg ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpeqw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
KReg_reg = zext(AVXOpMask[0,32]) & tmp;
|
|
}
|
|
|
|
# PCMPEQQ 4-250 PAGE 1370 LINE 71174
|
|
define pcodeop vpcmpeqq_avx512vl ;
|
|
:VPCMPEQQ KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0x29; KReg_reg ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpeqq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
KReg_reg = zext(AVXOpMask[0,2]) & tmp;
|
|
}
|
|
|
|
# PCMPEQQ 4-250 PAGE 1370 LINE 71179
|
|
:VPCMPEQQ KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_YmmReg; byte=0x29; KReg_reg ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpeqq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
KReg_reg = zext(AVXOpMask[0,4]) & tmp;
|
|
}
|
|
|
|
# PCMPEQQ 4-250 PAGE 1370 LINE 71184
|
|
define pcodeop vpcmpeqq_avx512f ;
|
|
:VPCMPEQQ KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_ZmmReg; byte=0x29; KReg_reg ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpeqq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
KReg_reg = zext(AVXOpMask[0,8]) & tmp;
|
|
}
|
|
|
|
# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71517
|
|
define pcodeop vpcmpgtd_avx512vl ;
|
|
:VPCMPGTD KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0x66; KReg_reg ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpgtd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
KReg_reg = zext(AVXOpMask[0,4]) & tmp;
|
|
}
|
|
|
|
# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71521
|
|
:VPCMPGTD KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & AVXOpMask & evexV5_YmmReg; byte=0x66; KReg_reg ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpgtd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
KReg_reg = zext(AVXOpMask[0,8]) & tmp;
|
|
}
|
|
|
|
# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71525
|
|
define pcodeop vpcmpgtd_avx512f ;
|
|
:VPCMPGTD KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & AVXOpMask & evexV5_ZmmReg; byte=0x66; KReg_reg ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpgtd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
KReg_reg = zext(AVXOpMask[0,16]) & tmp;
|
|
}
|
|
|
|
# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71529
|
|
define pcodeop vpcmpgtb_avx512vl ;
|
|
:VPCMPGTB KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_XmmReg; byte=0x64; KReg_reg ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpgtb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
KReg_reg = zext(AVXOpMask[0,16]) & tmp;
|
|
}
|
|
|
|
# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71533
|
|
:VPCMPGTB KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_YmmReg; byte=0x64; KReg_reg ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpgtb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
KReg_reg = zext(AVXOpMask[0,32]) & tmp;
|
|
}
|
|
|
|
# PCMPGTB/PCMPGTW/PCMPGTD 4-258 PAGE 1378 LINE 71545
|
|
define pcodeop vpcmpgtb_avx512bw ;
|
|
:VPCMPGTB KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_ZmmReg; byte=0x64; KReg_reg ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpgtb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
KReg_reg = zext(AVXOpMask[0,64]) & tmp;
|
|
}
|
|
|
|
# PCMPGTB/PCMPGTW/PCMPGTD 4-258 PAGE 1378 LINE 71549
|
|
define pcodeop vpcmpgtw_avx512vl ;
|
|
:VPCMPGTW KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_XmmReg; byte=0x65; KReg_reg ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpgtw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
KReg_reg = zext(AVXOpMask[0,8]) & tmp;
|
|
}
|
|
|
|
# PCMPGTB/PCMPGTW/PCMPGTD 4-258 PAGE 1378 LINE 71553
|
|
:VPCMPGTW KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_YmmReg; byte=0x65; KReg_reg ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpgtw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
KReg_reg = zext(AVXOpMask[0,16]) & tmp;
|
|
}
|
|
|
|
# PCMPGTB/PCMPGTW/PCMPGTD 4-258 PAGE 1378 LINE 71557
|
|
define pcodeop vpcmpgtw_avx512bw ;
|
|
:VPCMPGTW KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & AVXOpMask & evexV5_ZmmReg; byte=0x65; KReg_reg ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpgtw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
KReg_reg = zext(AVXOpMask[0,32]) & tmp;
|
|
}
|
|
|
|
# PCMPGTQ 4-263 PAGE 1383 LINE 71837
|
|
define pcodeop vpcmpgtq_avx512vl ;
|
|
:VPCMPGTQ KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0x37; KReg_reg ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpgtq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
KReg_reg = zext(AVXOpMask[0,2]) & tmp;
|
|
}
|
|
|
|
# PCMPGTQ 4-263 PAGE 1383 LINE 71841
|
|
:VPCMPGTQ KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_YmmReg; byte=0x37; KReg_reg ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpgtq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
KReg_reg = zext(AVXOpMask[0,4]) & tmp;
|
|
}
|
|
|
|
# PCMPGTQ 4-263 PAGE 1383 LINE 71849
|
|
define pcodeop vpcmpgtq_avx512f ;
|
|
:VPCMPGTQ KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_ZmmReg; byte=0x37; KReg_reg ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpgtq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
KReg_reg = zext(AVXOpMask[0,8]) & tmp;
|
|
}
|
|
|
|
# PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72334
|
|
:VPEXTRB Rmr32, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x14; XmmReg1 & mod=3 & Rmr32 & check_Rmr32_dest; imm8
|
|
{
|
|
local tmp8:1 = imm8 & 0xf;
|
|
local tmp = XmmReg1 >> (tmp8*8);
|
|
Rmr32 = zext(tmp[0,8]);
|
|
build check_Rmr32_dest;
|
|
}
|
|
|
|
:VPEXTRB m8, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x14; XmmReg1 ... & m8; imm8
|
|
{
|
|
local tmp8:1 = imm8 & 0xf;
|
|
local tmp = XmmReg1 >> (tmp8*8);
|
|
m8 = tmp[0,8];
|
|
}
|
|
|
|
# PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72339
|
|
:VPEXTRD rm32, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x16; XmmReg1 ... & (rm32 & check_rm32_dest); imm8
|
|
{
|
|
local tmp8:1 = imm8 & 0x3;
|
|
local tmp = XmmReg1 >> (tmp8*32);
|
|
rm32 = tmp[0,32];
|
|
build check_rm32_dest;
|
|
}
|
|
|
|
# PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72343
|
|
@ifdef IA64
|
|
:VPEXTRQ rm64, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1); byte=0x16; XmmReg1 ... & rm64; imm8
|
|
{
|
|
local tmp8:1 = imm8 & 0x1;
|
|
local tmp = XmmReg1 >> (tmp8*64);
|
|
rm64 = tmp[0,64];
|
|
}
|
|
@endif
|
|
|
|
# PEXTRW 4-277 PAGE 1397 LINE 72488
|
|
:VPEXTRW Reg32, XmmReg2, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xC5; Reg32 & check_Reg32_dest & (mod=0x3 & XmmReg2); imm8
|
|
{
|
|
local tmp = XmmReg2 >> (imm8*16);
|
|
Reg32 = zext(tmp[0,16]);
|
|
build check_Reg32_dest;
|
|
}
|
|
|
|
|
|
# PEXTRW 4-277 PAGE 1397 LINE 72494
|
|
:VPEXTRW Rmr32, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x15; XmmReg1 & mod=3 & Rmr32 & check_Rmr32_dest; imm8
|
|
{
|
|
local tmp = XmmReg1 >> (imm8*16);
|
|
Rmr32 = zext(tmp[0,16]);
|
|
build check_Rmr32_dest;
|
|
}
|
|
|
|
:VPEXTRW m16, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x15; XmmReg1 ... & m16; imm8
|
|
{
|
|
local tmp = XmmReg1 >> (imm8*16);
|
|
m16 = tmp[0,16];
|
|
}
|
|
|
|
# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73330
|
|
define pcodeop vpinsrb_avx512bw ;
|
|
:VPINSRB XmmReg1, evexV5_XmmReg, Reg32_m8, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_XmmReg; byte=0x20; (XmmReg1 & ZmmReg1) ... & Reg32_m8; imm8
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-RVMI)
|
|
{
|
|
local tmp:16 = vpinsrb_avx512bw( evexV5_XmmReg, Reg32_m8, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73333
|
|
define pcodeop vpinsrd_avx512dq ;
|
|
:VPINSRD XmmReg1, evexV5_XmmReg, rm32, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x22; (XmmReg1 & ZmmReg1) ... & rm32; imm8
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-RVMI)
|
|
{
|
|
local tmp:16 = vpinsrd_avx512dq( evexV5_XmmReg, rm32, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73336
|
|
define pcodeop vpinsrq_avx512dq ;
|
|
@ifdef IA64
|
|
:VPINSRQ XmmReg1, evexV5_XmmReg, rm64, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_XmmReg; byte=0x22; (XmmReg1 & ZmmReg1) ... & rm64; imm8
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-RVMI)
|
|
{
|
|
local tmp:16 = vpinsrq_avx512dq( evexV5_XmmReg, rm64, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
@endif
|
|
|
|
# PINSRW 4-296 PAGE 1416 LINE 73449
|
|
define pcodeop vpinsrw_avx512bw ;
|
|
:VPINSRW XmmReg1, evexV5_XmmReg, Reg32_m16, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xC4; (XmmReg1 & ZmmReg1) ... & Reg32_m16; imm8
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-RVMI)
|
|
{
|
|
local tmp:16 = vpinsrw_avx512bw( evexV5_XmmReg, Reg32_m16, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMADDUBSW 4-298 PAGE 1418 LINE 73558
|
|
define pcodeop vpmaddubsw_avx512vl ;
|
|
:VPMADDUBSW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_XmmReg; byte=0x04; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpmaddubsw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMADDUBSW 4-298 PAGE 1418 LINE 73562
|
|
:VPMADDUBSW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_YmmReg; byte=0x04; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpmaddubsw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMADDUBSW 4-298 PAGE 1418 LINE 73566
|
|
define pcodeop vpmaddubsw_avx512bw ;
|
|
:VPMADDUBSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x04; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpmaddubsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMADDWD 4-301 PAGE 1421 LINE 73708
|
|
define pcodeop vpmaddwd_avx512vl ;
|
|
:VPMADDWD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xF5; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpmaddwd_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMADDWD 4-301 PAGE 1421 LINE 73712
|
|
:VPMADDWD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xF5; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpmaddwd_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMADDWD 4-301 PAGE 1421 LINE 73716
|
|
define pcodeop vpmaddwd_avx512bw ;
|
|
:VPMADDWD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xF5; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpmaddwd_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73900
|
|
define pcodeop vpmaxsb_avx512vl ;
|
|
:VPMAXSB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_XmmReg; byte=0x3C; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpmaxsb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73903
|
|
:VPMAXSB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_YmmReg; byte=0x3C; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpmaxsb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73906
|
|
define pcodeop vpmaxsb_avx512bw ;
|
|
:VPMAXSB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x3C; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpmaxsb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73909
|
|
define pcodeop vpmaxsw_avx512vl ;
|
|
:VPMAXSW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xEE; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpmaxsw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73912
|
|
:VPMAXSW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xEE; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpmaxsw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73915
|
|
define pcodeop vpmaxsw_avx512bw ;
|
|
:VPMAXSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xEE; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpmaxsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73918
|
|
define pcodeop vpmaxsd_avx512vl ;
|
|
:VPMAXSD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x3D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpmaxsd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-305 PAGE 1425 LINE 73933
|
|
:VPMAXSD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x3D; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpmaxsd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-305 PAGE 1425 LINE 73936
|
|
define pcodeop vpmaxsd_avx512f ;
|
|
:VPMAXSD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x3D; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpmaxsd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-305 PAGE 1425 LINE 73939
|
|
define pcodeop vpmaxsq_avx512vl ;
|
|
:VPMAXSQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x3D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpmaxsq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-305 PAGE 1425 LINE 73942
|
|
:VPMAXSQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x3D; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpmaxsq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-305 PAGE 1425 LINE 73945
|
|
define pcodeop vpmaxsq_avx512f ;
|
|
:VPMAXSQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x3D; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpmaxsq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74295
|
|
define pcodeop vpmaxub_avx512vl ;
|
|
:VPMAXUB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xDE; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpmaxub_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74298
|
|
:VPMAXUB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xDE; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpmaxub_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74301
|
|
define pcodeop vpmaxub_avx512bw ;
|
|
:VPMAXUB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xDE; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpmaxub_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74304
|
|
define pcodeop vpmaxuw_avx512vl ;
|
|
:VPMAXUW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_XmmReg; byte=0x3E; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpmaxuw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74307
|
|
:VPMAXUW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_YmmReg; byte=0x3E; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpmaxuw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74310
|
|
define pcodeop vpmaxuw_avx512bw ;
|
|
:VPMAXUW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x3E; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpmaxuw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74540
|
|
define pcodeop vpmaxud_avx512vl ;
|
|
:VPMAXUD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x3F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpmaxud_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74543
|
|
:VPMAXUD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x3F; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpmaxud_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74546
|
|
define pcodeop vpmaxud_avx512f ;
|
|
:VPMAXUD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x3F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpmaxud_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74549
|
|
define pcodeop vpmaxuq_avx512vl ;
|
|
:VPMAXUQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x3F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpmaxuq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74552
|
|
:VPMAXUQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x3F; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpmaxuq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74555
|
|
define pcodeop vpmaxuq_avx512f ;
|
|
:VPMAXUQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x3F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpmaxuq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMINSB/PMINSW 4-320 PAGE 1440 LINE 74748
|
|
define pcodeop vpminsb_avx512vl ;
|
|
:VPMINSB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_XmmReg; byte=0x38; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpminsb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMINSB/PMINSW 4-320 PAGE 1440 LINE 74751
|
|
:VPMINSB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_YmmReg; byte=0x38; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpminsb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMINSB/PMINSW 4-320 PAGE 1440 LINE 74754
|
|
define pcodeop vpminsb_avx512bw ;
|
|
:VPMINSB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x38; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpminsb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMINSB/PMINSW 4-320 PAGE 1440 LINE 74757
|
|
define pcodeop vpminsw_avx512vl ;
|
|
:VPMINSW XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xEA; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpminsw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMINSB/PMINSW 4-320 PAGE 1440 LINE 74760
|
|
:VPMINSW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xEA; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpminsw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMINSB/PMINSW 4-320 PAGE 1440 LINE 74763
|
|
define pcodeop vpminsw_avx512bw ;
|
|
:VPMINSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xEA; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpminsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMINSD/PMINSQ 4-325 PAGE 1445 LINE 74995
|
|
define pcodeop vpminsd_avx512vl ;
|
|
:VPMINSD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x39; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpminsd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMINSD/PMINSQ 4-325 PAGE 1445 LINE 74998
|
|
:VPMINSD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x39; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpminsd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMINSD/PMINSQ 4-325 PAGE 1445 LINE 75001
|
|
define pcodeop vpminsd_avx512f ;
|
|
:VPMINSD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x39; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpminsd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMINSD/PMINSQ 4-325 PAGE 1445 LINE 75004
|
|
define pcodeop vpminsq_avx512vl ;
|
|
:VPMINSQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x39; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpminsq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMINSD/PMINSQ 4-325 PAGE 1445 LINE 75007
|
|
:VPMINSQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x39; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpminsq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMINSD/PMINSQ 4-325 PAGE 1445 LINE 75010
|
|
define pcodeop vpminsq_avx512f ;
|
|
:VPMINSQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x39; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpminsq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMINUB/PMINUW 4-329 PAGE 1449 LINE 75207
|
|
define pcodeop vpminub_avx512vl ;
|
|
:VPMINUB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & evexV5_XmmReg; byte=0xDA; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpminub_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMINUB/PMINUW 4-329 PAGE 1449 LINE 75210
|
|
:VPMINUB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & evexV5_YmmReg; byte=0xDA; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpminub_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMINUB/PMINUW 4-329 PAGE 1449 LINE 75213
|
|
define pcodeop vpminub_avx512bw ;
|
|
:VPMINUB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & evexV5_ZmmReg; byte=0xDA; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpminub_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMINUB/PMINUW 4-329 PAGE 1449 LINE 75216
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define pcodeop vpminuw_avx512vl ;
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:VPMINUW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & evexV5_XmmReg; byte=0x3A; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
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[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
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|
{
|
|
XmmResult = vpminuw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
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|
XmmMask = XmmReg1;
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build XmmOpMask16;
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ZmmReg1 = zext(XmmResult);
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|
}
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|
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# PMINUB/PMINUW 4-329 PAGE 1449 LINE 75219
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:VPMINUW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & evexV5_YmmReg; byte=0x3A; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
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[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
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|
{
|
|
YmmResult = vpminuw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
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YmmMask = YmmReg1;
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build YmmOpMask16;
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ZmmReg1 = zext(YmmResult);
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|
}
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|
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# PMINUB/PMINUW 4-329 PAGE 1449 LINE 75222
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define pcodeop vpminuw_avx512bw ;
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:VPMINUW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & evexV5_ZmmReg; byte=0x3A; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
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[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
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|
{
|
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ZmmResult = vpminuw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
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ZmmMask = ZmmReg1;
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build ZmmOpMask16;
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ZmmReg1 = ZmmResult;
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}
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# PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75451
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define pcodeop vpminud_avx512vl ;
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:VPMINUD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x3B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
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XmmResult = vpminud_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
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XmmMask = XmmReg1;
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build XmmOpMask32;
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ZmmReg1 = zext(XmmResult);
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|
}
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# PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75454
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:VPMINUD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x3B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpminud_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
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YmmMask = YmmReg1;
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build YmmOpMask32;
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ZmmReg1 = zext(YmmResult);
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|
}
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|
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# PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75457
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define pcodeop vpminud_avx512f ;
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:VPMINUD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x3B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpminud_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
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ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
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|
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# PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75460
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define pcodeop vpminuq_avx512vl ;
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:VPMINUQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x3B; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpminuq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75463
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|
:VPMINUQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x3B; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpminuq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75466
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define pcodeop vpminuq_avx512f ;
|
|
:VPMINUQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x3B; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpminuq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMOVSX 4-340 PAGE 1460 LINE 75796
|
|
define pcodeop vpmovsxbw_avx512vl ;
|
|
:VPMOVSXBW XmmReg1^XmmOpMask16, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x20; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
XmmResult = vpmovsxbw_avx512vl( XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMOVSX 4-340 PAGE 1460 LINE 75799
|
|
:VPMOVSXBW YmmReg1^YmmOpMask16, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x20; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
YmmResult = vpmovsxbw_avx512vl( XmmReg2_m128 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMOVSX 4-340 PAGE 1460 LINE 75802
|
|
define pcodeop vpmovsxbw_avx512bw ;
|
|
:VPMOVSXBW ZmmReg1^ZmmOpMask16, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x20; (ZmmReg1 & ZmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
ZmmResult = vpmovsxbw_avx512bw( YmmReg2_m256 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMOVSX 4-340 PAGE 1460 LINE 75805
|
|
define pcodeop vpmovsxbd_avx512vl ;
|
|
:VPMOVSXBD XmmReg1^XmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x21; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
XmmResult = vpmovsxbd_avx512vl( XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMOVSX 4-341 PAGE 1461 LINE 75819
|
|
:VPMOVSXBD YmmReg1^YmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x21; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
YmmResult = vpmovsxbd_avx512vl( XmmReg2_m64 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMOVSX 4-341 PAGE 1461 LINE 75822
|
|
define pcodeop vpmovsxbd_avx512f ;
|
|
:VPMOVSXBD ZmmReg1^ZmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x21; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
ZmmResult = vpmovsxbd_avx512f( XmmReg2_m128 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMOVSX 4-341 PAGE 1461 LINE 75825
|
|
define pcodeop vpmovsxbq_avx512vl ;
|
|
:VPMOVSXBQ XmmReg1^XmmOpMask64, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x22; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m16
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
XmmResult = vpmovsxbq_avx512vl( XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMOVSX 4-341 PAGE 1461 LINE 75828
|
|
:VPMOVSXBQ YmmReg1^YmmOpMask64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x22; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
YmmResult = vpmovsxbq_avx512vl( XmmReg2_m32 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMOVSX 4-341 PAGE 1461 LINE 75831
|
|
define pcodeop vpmovsxbq_avx512f ;
|
|
:VPMOVSXBQ ZmmReg1^ZmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x22; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
ZmmResult = vpmovsxbq_avx512f( XmmReg2_m64 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMOVSX 4-341 PAGE 1461 LINE 75834
|
|
define pcodeop vpmovsxwd_avx512vl ;
|
|
:VPMOVSXWD XmmReg1^XmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x23; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
XmmResult = vpmovsxwd_avx512vl( XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMOVSX 4-341 PAGE 1461 LINE 75837
|
|
:VPMOVSXWD YmmReg1^YmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x23; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
YmmResult = vpmovsxwd_avx512vl( XmmReg2_m128 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMOVSX 4-341 PAGE 1461 LINE 75840
|
|
define pcodeop vpmovsxwd_avx512f ;
|
|
:VPMOVSXWD ZmmReg1^ZmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x23; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
ZmmResult = vpmovsxwd_avx512f( YmmReg2_m256 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMOVSX 4-341 PAGE 1461 LINE 75843
|
|
define pcodeop vpmovsxwq_avx512vl ;
|
|
:VPMOVSXWQ XmmReg1^XmmOpMask64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x24; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
XmmResult = vpmovsxwq_avx512vl( XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMOVSX 4-341 PAGE 1461 LINE 75846
|
|
:VPMOVSXWQ YmmReg1^YmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x24; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
YmmResult = vpmovsxwq_avx512vl( XmmReg2_m64 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMOVSX 4-341 PAGE 1461 LINE 75849
|
|
define pcodeop vpmovsxwq_avx512f ;
|
|
:VPMOVSXWQ ZmmReg1^ZmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x24; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
ZmmResult = vpmovsxwq_avx512f( XmmReg2_m128 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMOVSX 4-341 PAGE 1461 LINE 75852
|
|
define pcodeop vpmovsxdq_avx512vl ;
|
|
:VPMOVSXDQ XmmReg1^XmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x25; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
XmmResult = vpmovsxdq_avx512vl( XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMOVSX 4-341 PAGE 1461 LINE 75855
|
|
:VPMOVSXDQ YmmReg1^YmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x25; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
YmmResult = vpmovsxdq_avx512vl( XmmReg2_m128 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMOVSX 4-341 PAGE 1461 LINE 75858
|
|
define pcodeop vpmovsxdq_avx512f ;
|
|
:VPMOVSXDQ ZmmReg1^ZmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x25; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
ZmmResult = vpmovsxdq_avx512f( YmmReg2_m256 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMOVZX 4-351 PAGE 1471 LINE 76329
|
|
define pcodeop vpmovzxbw_avx512vl ;
|
|
:VPMOVZXBW XmmReg1^XmmOpMask16, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x30; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
XmmResult = vpmovzxbw_avx512vl( XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMOVZX 4-351 PAGE 1471 LINE 76332
|
|
:VPMOVZXBW YmmReg1^YmmOpMask16, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x30; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
YmmResult = vpmovzxbw_avx512vl( XmmReg2_m128 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMOVZX 4-351 PAGE 1471 LINE 76335
|
|
define pcodeop vpmovzxbw_avx512bw ;
|
|
:VPMOVZXBW ZmmReg1^ZmmOpMask16, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x30; (ZmmReg1 & ZmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
ZmmResult = vpmovzxbw_avx512bw( YmmReg2_m256 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMOVZX 4-351 PAGE 1471 LINE 76338
|
|
define pcodeop vpmovzxbd_avx512vl ;
|
|
:VPMOVZXBD XmmReg1^XmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x31; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
XmmResult = vpmovzxbd_avx512vl( XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMOVZX 4-351 PAGE 1471 LINE 76341
|
|
:VPMOVZXBD YmmReg1^YmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x31; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
YmmResult = vpmovzxbd_avx512vl( XmmReg2_m64 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMOVZX 4-351 PAGE 1471 LINE 76344
|
|
define pcodeop vpmovzxbd_avx512f ;
|
|
:VPMOVZXBD ZmmReg1^ZmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x31; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
ZmmResult = vpmovzxbd_avx512f( XmmReg2_m128 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMOVZX 4-351 PAGE 1471 LINE 76347
|
|
define pcodeop vpmovzxbq_avx512vl ;
|
|
:VPMOVZXBQ XmmReg1^XmmOpMask64, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x32; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m16
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
XmmResult = vpmovzxbq_avx512vl( XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMOVZX 4-351 PAGE 1471 LINE 76350
|
|
:VPMOVZXBQ YmmReg1^YmmOpMask64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x32; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
YmmResult = vpmovzxbq_avx512vl( XmmReg2_m32 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMOVZX 4-351 PAGE 1471 LINE 76353
|
|
define pcodeop vpmovzxbq_avx512f ;
|
|
:VPMOVZXBQ ZmmReg1^ZmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x32; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
ZmmResult = vpmovzxbq_avx512f( XmmReg2_m64 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMOVZX 4-351 PAGE 1471 LINE 76356
|
|
define pcodeop vpmovzxwd_avx512vl ;
|
|
:VPMOVZXWD XmmReg1^XmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x33; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
XmmResult = vpmovzxwd_avx512vl( XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMOVZX 4-351 PAGE 1471 LINE 76359
|
|
:VPMOVZXWD YmmReg1^YmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x33; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
YmmResult = vpmovzxwd_avx512vl( XmmReg2_m128 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMOVZX 4-351 PAGE 1471 LINE 76362
|
|
define pcodeop vpmovzxwd_avx512f ;
|
|
:VPMOVZXWD ZmmReg1^ZmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x33; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
ZmmResult = vpmovzxwd_avx512f( YmmReg2_m256 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMOVZX 4-351 PAGE 1471 LINE 76365
|
|
define pcodeop vpmovzxwq_avx512vl ;
|
|
:VPMOVZXWQ XmmReg1^XmmOpMask64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x34; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
XmmResult = vpmovzxwq_avx512vl( XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMOVZX 4-351 PAGE 1471 LINE 76368
|
|
:VPMOVZXWQ YmmReg1^YmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x34; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
YmmResult = vpmovzxwq_avx512vl( XmmReg2_m64 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMOVZX 4-351 PAGE 1471 LINE 76371
|
|
define pcodeop vpmovzxwq_avx512f ;
|
|
:VPMOVZXWQ ZmmReg1^ZmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x34; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
ZmmResult = vpmovzxwq_avx512f( XmmReg2_m128 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMOVZX 4-352 PAGE 1472 LINE 76386
|
|
define pcodeop vpmovzxdq_avx512vl ;
|
|
:VPMOVZXDQ XmmReg1^XmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x35; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
XmmResult = vpmovzxdq_avx512vl( XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMOVZX 4-352 PAGE 1472 LINE 76389
|
|
:VPMOVZXDQ YmmReg1^YmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x35; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
YmmResult = vpmovzxdq_avx512vl( XmmReg2_m128 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMOVZX 4-352 PAGE 1472 LINE 76392
|
|
define pcodeop vpmovzxdq_avx512f ;
|
|
:VPMOVZXDQ ZmmReg1^ZmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x35; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM)
|
|
{
|
|
ZmmResult = vpmovzxdq_avx512f( YmmReg2_m256 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMULDQ 4-359 PAGE 1479 LINE 76794
|
|
define pcodeop vpmuldq_avx512vl ;
|
|
:VPMULDQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x28; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpmuldq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMULDQ 4-359 PAGE 1479 LINE 76798
|
|
:VPMULDQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x28; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpmuldq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMULDQ 4-359 PAGE 1479 LINE 76802
|
|
define pcodeop vpmuldq_avx512f ;
|
|
:VPMULDQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x28; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpmuldq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMULHRSW 4-362 PAGE 1482 LINE 76934
|
|
define pcodeop vpmulhrsw_avx512vl ;
|
|
:VPMULHRSW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_XmmReg; byte=0x0B; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpmulhrsw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMULHRSW 4-362 PAGE 1482 LINE 76937
|
|
:VPMULHRSW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_YmmReg; byte=0x0B; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpmulhrsw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMULHRSW 4-362 PAGE 1482 LINE 76940
|
|
define pcodeop vpmulhrsw_avx512bw ;
|
|
:VPMULHRSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x0B; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpmulhrsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMULHUW 4-366 PAGE 1486 LINE 77147
|
|
define pcodeop vpmulhuw_avx512vl ;
|
|
:VPMULHUW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xE4; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpmulhuw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMULHUW 4-366 PAGE 1486 LINE 77151
|
|
:VPMULHUW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xE4; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpmulhuw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMULHUW 4-366 PAGE 1486 LINE 77155
|
|
define pcodeop vpmulhuw_avx512bw ;
|
|
:VPMULHUW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE4; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpmulhuw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMULHW 4-370 PAGE 1490 LINE 77376
|
|
define pcodeop vpmulhw_avx512vl ;
|
|
:VPMULHW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xE5; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpmulhw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMULHW 4-370 PAGE 1490 LINE 77379
|
|
:VPMULHW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xE5; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpmulhw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMULHW 4-370 PAGE 1490 LINE 77382
|
|
define pcodeop vpmulhw_avx512bw ;
|
|
:VPMULHW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE5; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpmulhw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77582
|
|
define pcodeop vpmulld_avx512vl ;
|
|
:VPMULLD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x40; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpmulld_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77585
|
|
:VPMULLD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x40; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpmulld_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77588
|
|
define pcodeop vpmulld_avx512f ;
|
|
:VPMULLD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x40; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpmulld_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77591
|
|
define pcodeop vpmullq_avx512vl ;
|
|
:VPMULLQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x40; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpmullq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77594
|
|
:VPMULLQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x40; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpmullq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77597
|
|
define pcodeop vpmullq_avx512dq ;
|
|
:VPMULLQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x40; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpmullq_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMULLW 4-378 PAGE 1498 LINE 77781
|
|
define pcodeop vpmullw_avx512vl ;
|
|
:VPMULLW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xD5; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpmullw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMULLW 4-378 PAGE 1498 LINE 77784
|
|
:VPMULLW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xD5; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpmullw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMULLW 4-378 PAGE 1498 LINE 77787
|
|
define pcodeop vpmullw_avx512bw ;
|
|
:VPMULLW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xD5; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpmullw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PMULUDQ 4-382 PAGE 1502 LINE 77977
|
|
define pcodeop vpmuludq_avx512vl ;
|
|
:VPMULUDQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xF4; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpmuludq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PMULUDQ 4-382 PAGE 1502 LINE 77981
|
|
:VPMULUDQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xF4; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpmuludq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PMULUDQ 4-382 PAGE 1502 LINE 77985
|
|
define pcodeop vpmuludq_avx512f ;
|
|
:VPMULUDQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xF4; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpmuludq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# POR 4-399 PAGE 1519 LINE 78854
|
|
define pcodeop vpord_avx512vl ;
|
|
:VPORD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xEB; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpord_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# POR 4-399 PAGE 1519 LINE 78857
|
|
:VPORD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xEB; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpord_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# POR 4-399 PAGE 1519 LINE 78860
|
|
define pcodeop vpord_avx512f ;
|
|
:VPORD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xEB; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpord_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# POR 4-399 PAGE 1519 LINE 78863
|
|
define pcodeop vporq_avx512vl ;
|
|
:VPORQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xEB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vporq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# POR 4-399 PAGE 1519 LINE 78866
|
|
:VPORQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xEB; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vporq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# POR 4-399 PAGE 1519 LINE 78869
|
|
define pcodeop vporq_avx512f ;
|
|
:VPORQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xEB; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vporq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PSADBW 4-408 PAGE 1528 LINE 79250
|
|
define pcodeop vpsadbw_avx512vl ;
|
|
:VPSADBW XmmReg1, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xF6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp:16 = vpsadbw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSADBW 4-408 PAGE 1528 LINE 79255
|
|
:VPSADBW YmmReg1, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xF6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpsadbw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PSADBW 4-408 PAGE 1528 LINE 79260
|
|
define pcodeop vpsadbw_avx512bw ;
|
|
:VPSADBW ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xF6; ZmmReg1 ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpsadbw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PSHUFB 4-412 PAGE 1532 LINE 79466
|
|
define pcodeop vpshufb_avx512vl ;
|
|
:VPSHUFB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_XmmReg; byte=0x00; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpshufb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PSHUFB 4-412 PAGE 1532 LINE 79468
|
|
:VPSHUFB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_YmmReg; byte=0x00; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpshufb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PSHUFB 4-412 PAGE 1532 LINE 79470
|
|
define pcodeop vpshufb_avx512bw ;
|
|
:VPSHUFB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x00; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpshufb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PSHUFD 4-416 PAGE 1536 LINE 79656
|
|
define pcodeop vpshufd_avx512vl ;
|
|
:VPSHUFD XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x70; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpshufd_avx512vl( XmmReg2_m128_m32bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PSHUFD 4-416 PAGE 1536 LINE 79659
|
|
:VPSHUFD YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x70; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpshufd_avx512vl( YmmReg2_m256_m32bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PSHUFD 4-416 PAGE 1536 LINE 79662
|
|
define pcodeop vpshufd_avx512f ;
|
|
:VPSHUFD ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x70; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpshufd_avx512f( ZmmReg2_m512_m32bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PSHUFHW 4-420 PAGE 1540 LINE 79863
|
|
define pcodeop vpshufhw_avx512vl ;
|
|
:VPSHUFHW XmmReg1^XmmOpMask16, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpshufhw_avx512vl( XmmReg2_m128, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PSHUFHW 4-420 PAGE 1540 LINE 79866
|
|
:VPSHUFHW YmmReg1^YmmOpMask16, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpshufhw_avx512vl( YmmReg2_m256, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PSHUFHW 4-420 PAGE 1540 LINE 79869
|
|
define pcodeop vpshufhw_avx512bw ;
|
|
:VPSHUFHW ZmmReg1^ZmmOpMask16, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpshufhw_avx512bw( ZmmReg2_m512, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PSHUFLW 4-423 PAGE 1543 LINE 80038
|
|
define pcodeop vpshuflw_avx512vl ;
|
|
:VPSHUFLW XmmReg1^XmmOpMask16, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpshuflw_avx512vl( XmmReg2_m128, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PSHUFLW 4-423 PAGE 1543 LINE 80041
|
|
:VPSHUFLW YmmReg1^YmmOpMask16, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpshuflw_avx512vl( YmmReg2_m256, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PSHUFLW 4-423 PAGE 1543 LINE 80044
|
|
define pcodeop vpshuflw_avx512bw ;
|
|
:VPSHUFLW ZmmReg1^ZmmOpMask16, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpshuflw_avx512bw( ZmmReg2_m512, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PSLLDQ 4-431 PAGE 1551 LINE 80491
|
|
define pcodeop vpslldq_avx512vl ;
|
|
:VPSLLDQ evexV5_XmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (evexV5_XmmReg & evexV5_ZmmReg); byte=0x73; reg_opcode=7 ... & XmmReg2_m128; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI)
|
|
{
|
|
local tmp:64 = vpslldq_avx512vl( XmmReg2_m128, imm8:1 );
|
|
evexV5_ZmmReg = zext(tmp);
|
|
}
|
|
|
|
# PSLLDQ 4-431 PAGE 1551 LINE 80493
|
|
:VPSLLDQ evexV5_YmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (evexV5_YmmReg & evexV5_ZmmReg); byte=0x73; reg_opcode=7 ... & YmmReg2_m256; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI)
|
|
{
|
|
local tmp:64 = vpslldq_avx512vl( YmmReg2_m256, imm8:1 );
|
|
evexV5_ZmmReg = zext(tmp);
|
|
}
|
|
|
|
# PSLLDQ 4-431 PAGE 1551 LINE 80495
|
|
define pcodeop vpslldq_avx512bw ;
|
|
:VPSLLDQ evexV5_ZmmReg, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x73; reg_opcode=7 ... & ZmmReg2_m512; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI)
|
|
{
|
|
evexV5_ZmmReg = vpslldq_avx512bw( ZmmReg2_m512, imm8:1 );
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80667
|
|
define pcodeop vpsllw_avx512vl ;
|
|
:VPSLLW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xF1; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
XmmResult = vpsllw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80670
|
|
:VPSLLW YmmReg1^YmmOpMask16, evexV5_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xF1; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
YmmResult = vpsllw_avx512vl( evexV5_YmmReg, XmmReg2_m128 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80673
|
|
define pcodeop vpsllw_avx512bw ;
|
|
:VPSLLW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xF1; (ZmmReg1 & ZmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
ZmmResult = vpsllw_avx512bw( evexV5_ZmmReg, XmmReg2_m128 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80676
|
|
:VPSLLW evexV5_XmmReg^XmmOpMask16, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask16; byte=0x71; reg_opcode=6 ... & XmmReg2_m128; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI)
|
|
{
|
|
XmmResult = vpsllw_avx512vl( XmmReg2_m128, imm8:1 );
|
|
XmmMask = evexV5_XmmReg;
|
|
build XmmOpMask16;
|
|
evexV5_ZmmReg = zext(XmmResult);
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80678
|
|
:VPSLLW evexV5_YmmReg^YmmOpMask16, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask16; byte=0x71; reg_opcode=6 ... & YmmReg2_m256; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI)
|
|
{
|
|
YmmResult = vpsllw_avx512vl( YmmReg2_m256, imm8:1 );
|
|
YmmMask = evexV5_YmmReg;
|
|
build YmmOpMask16;
|
|
evexV5_ZmmReg = zext(YmmResult);
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80680
|
|
:VPSLLW evexV5_ZmmReg^ZmmOpMask16, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg & ZmmOpMask16; byte=0x71; reg_opcode=6 ... & ZmmReg2_m512; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI)
|
|
{
|
|
ZmmResult = vpsllw_avx512bw( ZmmReg2_m512, imm8:1 );
|
|
ZmmMask = evexV5_ZmmReg;
|
|
build ZmmOpMask16;
|
|
evexV5_ZmmReg = ZmmResult;
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80682
|
|
define pcodeop vpslld_avx512vl ;
|
|
:VPSLLD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xF2; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
XmmResult = vpslld_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80685
|
|
:VPSLLD YmmReg1^YmmOpMask32, evexV5_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xF2; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
YmmResult = vpslld_avx512vl( evexV5_YmmReg, XmmReg2_m128 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80688
|
|
define pcodeop vpslld_avx512f ;
|
|
:VPSLLD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xF2; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
ZmmResult = vpslld_avx512f( evexV5_ZmmReg, XmmReg2_m128 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80691
|
|
:VPSLLD evexV5_XmmReg^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask32; byte=0x72; reg_opcode=6 ... & XmmReg2_m128_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
XmmResult = vpslld_avx512vl( XmmReg2_m128_m32bcst, imm8:1 );
|
|
XmmMask = evexV5_XmmReg;
|
|
build XmmOpMask32;
|
|
evexV5_ZmmReg = zext(XmmResult);
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80694
|
|
:VPSLLD evexV5_YmmReg^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask32; byte=0x72; reg_opcode=6 ... & YmmReg2_m256_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
YmmResult = vpslld_avx512vl( YmmReg2_m256_m32bcst, imm8:1 );
|
|
YmmMask = evexV5_YmmReg;
|
|
build YmmOpMask32;
|
|
evexV5_ZmmReg = zext(YmmResult);
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80697
|
|
:VPSLLD evexV5_ZmmReg^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & ZmmOpMask32; byte=0x72; reg_opcode=6 ... & ZmmReg2_m512_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
ZmmResult = vpslld_avx512f( ZmmReg2_m512_m32bcst, imm8:1 );
|
|
ZmmMask = evexV5_ZmmReg;
|
|
build ZmmOpMask32;
|
|
evexV5_ZmmReg = ZmmResult;
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80700
|
|
define pcodeop vpsllq_avx512vl ;
|
|
:VPSLLQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xF3; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
XmmResult = vpsllq_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80703
|
|
:VPSLLQ YmmReg1^YmmOpMask64, evexV5_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xF3; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
YmmResult = vpsllq_avx512vl( evexV5_YmmReg, XmmReg2_m128 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80706
|
|
define pcodeop vpsllq_avx512f ;
|
|
:VPSLLQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xF3; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
ZmmResult = vpsllq_avx512f( evexV5_ZmmReg, XmmReg2_m128 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-435 PAGE 1555 LINE 80721
|
|
:VPSLLQ evexV5_XmmReg^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask64; byte=0x73; reg_opcode=6 ... & XmmReg2_m128_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
XmmResult = vpsllq_avx512vl( XmmReg2_m128_m64bcst, imm8:1 );
|
|
XmmMask = evexV5_XmmReg;
|
|
build XmmOpMask64;
|
|
evexV5_ZmmReg = zext(XmmResult);
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-435 PAGE 1555 LINE 80724
|
|
:VPSLLQ evexV5_YmmReg^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask64; byte=0x73; reg_opcode=6 ... & YmmReg2_m256_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
YmmResult = vpsllq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 );
|
|
YmmMask = evexV5_YmmReg;
|
|
build YmmOpMask64;
|
|
evexV5_ZmmReg = zext(YmmResult);
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-435 PAGE 1555 LINE 80727
|
|
:VPSLLQ evexV5_ZmmReg^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & ZmmOpMask64; byte=0x73; reg_opcode=6 ... & ZmmReg2_m512_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
ZmmResult = vpsllq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 );
|
|
ZmmMask = evexV5_ZmmReg;
|
|
build ZmmOpMask64;
|
|
evexV5_ZmmReg = ZmmResult;
|
|
}
|
|
|
|
# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81329
|
|
define pcodeop vpsraw_avx512vl ;
|
|
:VPSRAW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xE1; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
XmmResult = vpsraw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81332
|
|
:VPSRAW YmmReg1^YmmOpMask16, evexV5_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xE1; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
YmmResult = vpsraw_avx512vl( evexV5_YmmReg, XmmReg2_m128 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81335
|
|
define pcodeop vpsraw_avx512bw ;
|
|
:VPSRAW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE1; (ZmmReg1 & ZmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
ZmmResult = vpsraw_avx512bw( evexV5_ZmmReg, XmmReg2_m128 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81350
|
|
:VPSRAW evexV5_XmmReg^XmmOpMask16, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask16; byte=0x71; reg_opcode=4 ... & XmmReg2_m128; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI)
|
|
{
|
|
XmmResult = vpsraw_avx512vl( XmmReg2_m128, imm8:1 );
|
|
XmmMask = evexV5_XmmReg;
|
|
build XmmOpMask16;
|
|
evexV5_ZmmReg = zext(XmmResult);
|
|
}
|
|
|
|
# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81352
|
|
:VPSRAW evexV5_YmmReg^YmmOpMask16, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask16; byte=0x71; reg_opcode=4 ... & YmmReg2_m256; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI)
|
|
{
|
|
YmmResult = vpsraw_avx512vl( YmmReg2_m256, imm8:1 );
|
|
YmmMask = evexV5_YmmReg;
|
|
build YmmOpMask16;
|
|
evexV5_ZmmReg = zext(YmmResult);
|
|
}
|
|
|
|
# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81354
|
|
:VPSRAW evexV5_ZmmReg^ZmmOpMask16, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg & ZmmOpMask16; byte=0x71; reg_opcode=4 ... & ZmmReg2_m512; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI)
|
|
{
|
|
ZmmResult = vpsraw_avx512bw( ZmmReg2_m512, imm8:1 );
|
|
ZmmMask = evexV5_ZmmReg;
|
|
build ZmmOpMask16;
|
|
evexV5_ZmmReg = ZmmResult;
|
|
}
|
|
|
|
# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81356
|
|
define pcodeop vpsrad_avx512vl ;
|
|
:VPSRAD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xE2; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
XmmResult = vpsrad_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81359
|
|
:VPSRAD YmmReg1^YmmOpMask32, evexV5_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xE2; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
YmmResult = vpsrad_avx512vl( evexV5_YmmReg, XmmReg2_m128 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81362
|
|
define pcodeop vpsrad_avx512f ;
|
|
:VPSRAD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xE2; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
ZmmResult = vpsrad_avx512f( evexV5_ZmmReg, XmmReg2_m128 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81365
|
|
:VPSRAD evexV5_XmmReg^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask32; byte=0x72; reg_opcode=4 ... & XmmReg2_m128_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
XmmResult = vpsrad_avx512vl( XmmReg2_m128_m32bcst, imm8:1 );
|
|
XmmMask = evexV5_XmmReg;
|
|
build XmmOpMask32;
|
|
evexV5_ZmmReg = zext(XmmResult);
|
|
}
|
|
|
|
# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81368
|
|
:VPSRAD evexV5_YmmReg^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask32; byte=0x72; reg_opcode=4 ... & YmmReg2_m256_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
YmmResult = vpsrad_avx512vl( YmmReg2_m256_m32bcst, imm8:1 );
|
|
YmmMask = evexV5_YmmReg;
|
|
build YmmOpMask32;
|
|
evexV5_ZmmReg = zext(YmmResult);
|
|
|
|
}
|
|
|
|
# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81371
|
|
:VPSRAD evexV5_ZmmReg^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & ZmmOpMask32; byte=0x72; reg_opcode=4 ... & ZmmReg2_m512_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
ZmmResult = vpsrad_avx512f( ZmmReg2_m512_m32bcst, imm8:1 );
|
|
ZmmMask = evexV5_ZmmReg;
|
|
build ZmmOpMask32;
|
|
evexV5_ZmmReg = ZmmResult;
|
|
}
|
|
|
|
# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81374
|
|
define pcodeop vpsraq_avx512vl ;
|
|
:VPSRAQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xE2; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
XmmResult = vpsraq_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81377
|
|
:VPSRAQ YmmReg1^YmmOpMask64, evexV5_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xE2; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
YmmResult = vpsraq_avx512vl( evexV5_YmmReg, XmmReg2_m128 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81380
|
|
define pcodeop vpsraq_avx512f ;
|
|
:VPSRAQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xE2; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
ZmmResult = vpsraq_avx512f( evexV5_ZmmReg, XmmReg2_m128 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81383
|
|
:VPSRAQ evexV5_XmmReg^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask64; byte=0x72; reg_opcode=4 ... & XmmReg2_m128_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
XmmResult = vpsraq_avx512vl( XmmReg2_m128_m64bcst, imm8:1 );
|
|
XmmMask = evexV5_XmmReg;
|
|
build XmmOpMask64;
|
|
evexV5_ZmmReg = zext(XmmResult);
|
|
}
|
|
|
|
# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81386
|
|
:VPSRAQ evexV5_YmmReg^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask64; byte=0x72; reg_opcode=4 ... & YmmReg2_m256_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
YmmResult = vpsraq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 );
|
|
YmmMask = evexV5_YmmReg;
|
|
build YmmOpMask64;
|
|
evexV5_ZmmReg = zext(YmmResult);
|
|
}
|
|
|
|
# PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81389
|
|
:VPSRAQ evexV5_ZmmReg^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & ZmmOpMask64; byte=0x72; reg_opcode=4 ... & ZmmReg2_m512_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
ZmmResult = vpsraq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 );
|
|
ZmmMask = evexV5_ZmmReg;
|
|
build ZmmOpMask64;
|
|
evexV5_ZmmReg = ZmmResult;
|
|
}
|
|
|
|
# PSRLDQ 4-455 PAGE 1575 LINE 81879
|
|
define pcodeop vpsrldq_avx512vl ;
|
|
:VPSRLDQ evexV5_XmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (evexV5_XmmReg & evexV5_ZmmReg); byte=0x73; reg_opcode=3 ... & XmmReg2_m128; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp:64 = vpsrldq_avx512vl( XmmReg2_m128, imm8:1 );
|
|
evexV5_ZmmReg = zext(tmp);
|
|
}
|
|
|
|
# PSRLDQ 4-455 PAGE 1575 LINE 81881
|
|
:VPSRLDQ evexV5_YmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (evexV5_YmmReg & evexV5_ZmmReg); byte=0x73; reg_opcode=3 ... & YmmReg2_m256; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp:64 = vpsrldq_avx512vl( YmmReg2_m256, imm8:1 );
|
|
evexV5_ZmmReg = zext(tmp);
|
|
}
|
|
|
|
# PSRLDQ 4-455 PAGE 1575 LINE 81883
|
|
define pcodeop vpsrldq_avx512bw ;
|
|
:VPSRLDQ evexV5_ZmmReg, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x73; reg_opcode=3 ... & ZmmReg2_m512; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
evexV5_ZmmReg = vpsrldq_avx512bw( ZmmReg2_m512, imm8:1 );
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82059
|
|
define pcodeop vpsrlw_avx512vl ;
|
|
:VPSRLW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xD1; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
XmmResult = vpsrlw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82062
|
|
:VPSRLW YmmReg1^YmmOpMask16, evexV5_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xD1; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
YmmResult = vpsrlw_avx512vl( evexV5_YmmReg, XmmReg2_m128 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82065
|
|
define pcodeop vpsrlw_avx512bw ;
|
|
:VPSRLW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xD1; (ZmmReg1 & ZmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
ZmmResult = vpsrlw_avx512bw( evexV5_ZmmReg, XmmReg2_m128 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82068
|
|
:VPSRLW evexV5_XmmReg^XmmOpMask16, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask16; byte=0x71; reg_opcode=2 ... & XmmReg2_m128; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpsrlw_avx512vl( XmmReg2_m128, imm8:1 );
|
|
XmmMask = evexV5_XmmReg;
|
|
build XmmOpMask16;
|
|
evexV5_ZmmReg = zext(XmmResult);
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82070
|
|
:VPSRLW evexV5_YmmReg^YmmOpMask16, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask16; byte=0x71; reg_opcode=2 ... & YmmReg2_m256; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpsrlw_avx512vl( YmmReg2_m256, imm8:1 );
|
|
YmmMask = evexV5_YmmReg;
|
|
build YmmOpMask16;
|
|
evexV5_ZmmReg = zext(YmmResult);
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82072
|
|
:VPSRLW evexV5_ZmmReg^ZmmOpMask16, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg & ZmmOpMask16; byte=0x71; reg_opcode=2 ... & ZmmReg2_m512; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpsrlw_avx512bw( ZmmReg2_m512, imm8:1 );
|
|
ZmmMask = evexV5_ZmmReg;
|
|
build ZmmOpMask16;
|
|
evexV5_ZmmReg = ZmmResult;
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82074
|
|
define pcodeop vpsrld_avx512vl ;
|
|
:VPSRLD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xD2; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
XmmResult = vpsrld_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82077
|
|
:VPSRLD YmmReg1^YmmOpMask32, evexV5_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xD2; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
YmmResult = vpsrld_avx512vl( evexV5_YmmReg, XmmReg2_m128 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82080
|
|
define pcodeop vpsrld_avx512f ;
|
|
:VPSRLD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xD2; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
ZmmResult = vpsrld_avx512f( evexV5_ZmmReg, XmmReg2_m128 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82084
|
|
:VPSRLD evexV5_XmmReg^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask32; byte=0x72; reg_opcode=2 ... & XmmReg2_m128_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
XmmResult = vpsrld_avx512vl( XmmReg2_m128_m32bcst, imm8:1 );
|
|
XmmMask = evexV5_XmmReg;
|
|
build XmmOpMask32;
|
|
evexV5_ZmmReg = zext(XmmResult);
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82088
|
|
:VPSRLD evexV5_YmmReg^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask32; byte=0x72; reg_opcode=2 ... & YmmReg2_m256_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
YmmResult = vpsrld_avx512vl( YmmReg2_m256_m32bcst, imm8:1 );
|
|
YmmMask = evexV5_YmmReg;
|
|
build YmmOpMask32;
|
|
evexV5_ZmmReg = zext(YmmResult);
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82091
|
|
:VPSRLD evexV5_ZmmReg^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & ZmmOpMask32; byte=0x72; reg_opcode=2 ... & ZmmReg2_m512_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
ZmmResult = vpsrld_avx512f( ZmmReg2_m512_m32bcst, imm8:1 );
|
|
ZmmMask = evexV5_ZmmReg;
|
|
build ZmmOpMask32;
|
|
evexV5_ZmmReg = ZmmResult;
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82094
|
|
define pcodeop vpsrlq_avx512vl ;
|
|
:VPSRLQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xD3; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
XmmResult = vpsrlq_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82097
|
|
:VPSRLQ YmmReg1^YmmOpMask64, evexV5_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xD3; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
YmmResult = vpsrlq_avx512vl( evexV5_YmmReg, XmmReg2_m128 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82100
|
|
define pcodeop vpsrlq_avx512f ;
|
|
:VPSRLQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xD3; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 12; ] # (TupleType M128)
|
|
{
|
|
ZmmResult = vpsrlq_avx512f( evexV5_ZmmReg, XmmReg2_m128 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-459 PAGE 1579 LINE 82115
|
|
:VPSRLQ evexV5_XmmReg^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask64; byte=0x73; reg_opcode=2 ... & XmmReg2_m128_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
XmmResult = vpsrlq_avx512vl( XmmReg2_m128_m64bcst, imm8:1 );
|
|
XmmMask = evexV5_XmmReg;
|
|
build XmmOpMask64;
|
|
evexV5_ZmmReg = zext(XmmResult);
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-459 PAGE 1579 LINE 82119
|
|
:VPSRLQ evexV5_YmmReg^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask64; byte=0x73; reg_opcode=2 ... & YmmReg2_m256_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
YmmResult = vpsrlq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 );
|
|
YmmMask = evexV5_YmmReg;
|
|
build YmmOpMask64;
|
|
evexV5_ZmmReg = zext(YmmResult);
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-459 PAGE 1579 LINE 82122
|
|
:VPSRLQ evexV5_ZmmReg^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & ZmmOpMask64; byte=0x73; reg_opcode=2 ... & ZmmReg2_m512_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
ZmmResult = vpsrlq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 );
|
|
ZmmMask = evexV5_ZmmReg;
|
|
build ZmmOpMask64;
|
|
evexV5_ZmmReg = ZmmResult;
|
|
}
|
|
|
|
# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82702
|
|
define pcodeop vpsubb_avx512vl ;
|
|
:VPSUBB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xF8; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpsubb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82705
|
|
:VPSUBB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xF8; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpsubb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82708
|
|
define pcodeop vpsubb_avx512bw ;
|
|
:VPSUBB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xF8; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpsubb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82711
|
|
define pcodeop vpsubw_avx512vl ;
|
|
:VPSUBW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xF9; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpsubw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82714
|
|
:VPSUBW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xF9; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpsubw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82717
|
|
define pcodeop vpsubw_avx512bw ;
|
|
:VPSUBW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xF9; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpsubw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PSUBB/PSUBW/PSUBD 4-470 PAGE 1590 LINE 82733
|
|
define pcodeop vpsubd_avx512vl ;
|
|
:VPSUBD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xFA; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpsubd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PSUBB/PSUBW/PSUBD 4-470 PAGE 1590 LINE 82736
|
|
:VPSUBD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xFA; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpsubd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PSUBB/PSUBW/PSUBD 4-470 PAGE 1590 LINE 82743
|
|
define pcodeop vpsubd_avx512f ;
|
|
:VPSUBD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xFA; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpsubd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PSUBQ 4-476 PAGE 1596 LINE 83111
|
|
define pcodeop vpsubq_avx512vl ;
|
|
:VPSUBQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xFB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpsubq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PSUBQ 4-476 PAGE 1596 LINE 83114
|
|
:VPSUBQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xFB; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpsubq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PSUBQ 4-476 PAGE 1596 LINE 83117
|
|
define pcodeop vpsubq_avx512f ;
|
|
:VPSUBQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xFB; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpsubq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83270
|
|
define pcodeop vpsubsb_avx512vl ;
|
|
:VPSUBSB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xE8; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpsubsb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83274
|
|
:VPSUBSB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xE8; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpsubsb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83278
|
|
define pcodeop vpsubsb_avx512bw ;
|
|
:VPSUBSB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE8; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpsubsb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83282
|
|
define pcodeop vpsubsw_avx512vl ;
|
|
:VPSUBSW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xE9; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpsubsw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83286
|
|
:VPSUBSW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xE9; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpsubsw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PSUBSB/PSUBSW 4-480 PAGE 1600 LINE 83302
|
|
define pcodeop vpsubsw_avx512bw ;
|
|
:VPSUBSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE9; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
{
|
|
ZmmResult = vpsubsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83510
|
|
define pcodeop vpsubusb_avx512vl ;
|
|
:VPSUBUSB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xD8; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpsubusb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83514
|
|
:VPSUBUSB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xD8; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpsubusb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83518
|
|
define pcodeop vpsubusb_avx512bw ;
|
|
:VPSUBUSB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xD8; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpsubusb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83522
|
|
define pcodeop vpsubusw_avx512vl ;
|
|
:VPSUBUSW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0xD9; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpsubusw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83526
|
|
:VPSUBUSW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0xD9; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpsubusw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PSUBUSB/PSUBUSW 4-484 PAGE 1604 LINE 83543
|
|
define pcodeop vpsubusw_avx512bw ;
|
|
:VPSUBUSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xD9; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpsubusw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83948
|
|
define pcodeop vpunpckhbw_avx512vl ;
|
|
:VPUNPCKHBW XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0x68; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpunpckhbw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83952
|
|
define pcodeop vpunpckhwd_avx512vl ;
|
|
:VPUNPCKHWD XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0x69; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpunpckhwd_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83955
|
|
define pcodeop vpunpckhdq_avx512vl ;
|
|
:VPUNPCKHDQ XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x6A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpunpckhdq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83958
|
|
define pcodeop vpunpckhqdq_avx512vl ;
|
|
:VPUNPCKHQDQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x6D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpunpckhqdq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83974
|
|
:VPUNPCKHBW YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0x68; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpunpckhbw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83977
|
|
:VPUNPCKHWD YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0x69; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpunpckhwd_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83980
|
|
:VPUNPCKHDQ YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x6A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpunpckhdq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83984
|
|
:VPUNPCKHQDQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x6D; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpunpckhqdq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83988
|
|
define pcodeop vpunpckhbw_avx512bw ;
|
|
:VPUNPCKHBW ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x68; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpunpckhbw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83991
|
|
define pcodeop vpunpckhwd_avx512bw ;
|
|
:VPUNPCKHWD ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x69; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpunpckhwd_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83994
|
|
define pcodeop vpunpckhdq_avx512f ;
|
|
:VPUNPCKHDQ ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x6A; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpunpckhdq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83997
|
|
define pcodeop vpunpckhqdq_avx512f ;
|
|
:VPUNPCKHQDQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x6D; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpunpckhqdq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84553
|
|
define pcodeop vpunpcklbw_avx512vl ;
|
|
:VPUNPCKLBW XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0x60; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpunpcklbw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84556
|
|
define pcodeop vpunpcklwd_avx512vl ;
|
|
:VPUNPCKLWD XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_XmmReg; byte=0x61; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpunpcklwd_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84559
|
|
define pcodeop vpunpckldq_avx512vl ;
|
|
:VPUNPCKLDQ XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x62; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpunpckldq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84562
|
|
define pcodeop vpunpcklqdq_avx512vl ;
|
|
:VPUNPCKLQDQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x6C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpunpcklqdq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84578
|
|
:VPUNPCKLBW YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0x60; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpunpcklbw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84581
|
|
:VPUNPCKLWD YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_YmmReg; byte=0x61; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpunpcklwd_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84584
|
|
:VPUNPCKLDQ YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x62; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpunpckldq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84587
|
|
:VPUNPCKLQDQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x6C; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpunpcklqdq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84590
|
|
define pcodeop vpunpcklbw_avx512bw ;
|
|
:VPUNPCKLBW ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x60; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpunpcklbw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84593
|
|
define pcodeop vpunpcklwd_avx512bw ;
|
|
:VPUNPCKLWD ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x61; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpunpcklwd_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84596
|
|
define pcodeop vpunpckldq_avx512f ;
|
|
:VPUNPCKLDQ ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x62; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpunpckldq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84599
|
|
define pcodeop vpunpcklqdq_avx512f ;
|
|
:VPUNPCKLQDQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x6C; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpunpcklqdq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# SHUFPD 4-617 PAGE 1737 LINE 90231
|
|
define pcodeop vshufpd_avx512vl ;
|
|
:VSHUFPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xC6; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vshufpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# SHUFPD 4-617 PAGE 1737 LINE 90235
|
|
:VSHUFPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xC6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vshufpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# SHUFPD 4-617 PAGE 1737 LINE 90239
|
|
define pcodeop vshufpd_avx512f ;
|
|
:VSHUFPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xC6; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vshufpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# SHUFPS 4-622 PAGE 1742 LINE 90489
|
|
define pcodeop vshufps_avx512vl ;
|
|
:VSHUFPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xC6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vshufps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# SHUFPS 4-622 PAGE 1742 LINE 90493
|
|
:VSHUFPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xC6; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vshufps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# SHUFPS 4-622 PAGE 1742 LINE 90497
|
|
define pcodeop vshufps_avx512f ;
|
|
:VSHUFPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xC6; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vshufps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# SQRTPD 4-632 PAGE 1752 LINE 91007
|
|
define pcodeop vsqrtpd_avx512vl ;
|
|
:VSQRTPD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vsqrtpd_avx512vl( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# SQRTPD 4-632 PAGE 1752 LINE 91010
|
|
:VSQRTPD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x51; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vsqrtpd_avx512vl( YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# SQRTPD 4-632 PAGE 1752 LINE 91013
|
|
define pcodeop vsqrtpd_avx512f ;
|
|
:VSQRTPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x51; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vsqrtpd_avx512f( ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# SQRTPS 4-635 PAGE 1755 LINE 91139
|
|
define pcodeop vsqrtps_avx512vl ;
|
|
:VSQRTPS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vsqrtps_avx512vl( XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# SQRTPS 4-635 PAGE 1755 LINE 91142
|
|
:VSQRTPS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x51; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vsqrtps_avx512vl( YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# SQRTPS 4-635 PAGE 1755 LINE 91145
|
|
define pcodeop vsqrtps_avx512f ;
|
|
:VSQRTPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x51; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vsqrtps_avx512f( ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# SQRTSD 4-638 PAGE 1758 LINE 91276
|
|
:VSQRTSD XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult[0,64] = sqrt(XmmReg2_m64[0,64]);
|
|
XmmMask = XmmReg1;
|
|
conditionalAssign(XmmResult[0,64], XmmOpMask[0,1], XmmResult[0,64], XmmMask[0,64]);
|
|
XmmReg1[0,64] = XmmResult[0,64];
|
|
XmmReg1[64,64]= evexV5_XmmReg[64,64];
|
|
ZmmReg1 = zext(XmmReg1);
|
|
}
|
|
|
|
# SQRTSS 4-640 PAGE 1760 LINE 91371
|
|
:VSQRTSS XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult[0,32] = sqrt(XmmReg2_m32[0,32]);
|
|
XmmMask = XmmReg1;
|
|
conditionalAssign(XmmResult[0,32], XmmOpMask[0,1], XmmResult[0,32], XmmMask[0,32]);
|
|
XmmReg1[0,32] = XmmResult[0,32];
|
|
XmmReg1[32,96]=evexV5_XmmReg[32,96];
|
|
ZmmReg1 = zext(XmmReg1);
|
|
}
|
|
|
|
# SUBPD 4-656 PAGE 1776 LINE 92120
|
|
define pcodeop vsubpd_avx512vl ;
|
|
:VSUBPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vsubpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# SUBPD 4-656 PAGE 1776 LINE 92123
|
|
:VSUBPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x5C; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vsubpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# SUBPD 4-656 PAGE 1776 LINE 92126
|
|
define pcodeop vsubpd_avx512f ;
|
|
:VSUBPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x5C; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vsubpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# SUBPS 4-659 PAGE 1779 LINE 92269
|
|
define pcodeop vsubps_avx512vl ;
|
|
:VSUBPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vsubps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# SUBPS 4-659 PAGE 1779 LINE 92272
|
|
:VSUBPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x5C; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vsubps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# SUBPS 4-659 PAGE 1779 LINE 92275
|
|
define pcodeop vsubps_avx512f ;
|
|
:VSUBPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x5C; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vsubps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# SUBSD 4-662 PAGE 1782 LINE 92421
|
|
define pcodeop vsubsd_avx512f ;
|
|
:VSUBSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vsubsd_avx512f( evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# SUBSS 4-664 PAGE 1784 LINE 92514
|
|
define pcodeop vsubss_avx512f ;
|
|
:VSUBSS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vsubss_avx512f( evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# UCOMISD 4-683 PAGE 1803 LINE 93424
|
|
define pcodeop vucomisd_avx512f ;
|
|
:VUCOMISD XmmReg1, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x2E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
fucompe(XmmReg1[0,64], XmmReg2_m64[0,64]);
|
|
}
|
|
|
|
# UCOMISS 4-685 PAGE 1805 LINE 93507
|
|
define pcodeop vucomiss_avx512f ;
|
|
:VUCOMISS XmmReg1, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x2E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
fucompe(XmmReg1[0,32], XmmReg2_m32[0,32]);
|
|
}
|
|
|
|
# UNPCKHPD 4-688 PAGE 1808 LINE 93629
|
|
define pcodeop vunpckhpd_avx512vl ;
|
|
:VUNPCKHPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vunpckhpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# UNPCKHPD 4-688 PAGE 1808 LINE 93632
|
|
:VUNPCKHPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vunpckhpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# UNPCKHPD 4-688 PAGE 1808 LINE 93635
|
|
define pcodeop vunpckhpd_avx512f ;
|
|
:VUNPCKHPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x15; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vunpckhpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# UNPCKHPS 4-692 PAGE 1812 LINE 93813
|
|
define pcodeop vunpckhps_avx512vl ;
|
|
:VUNPCKHPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vunpckhps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# UNPCKHPS 4-692 PAGE 1812 LINE 93817
|
|
:VUNPCKHPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vunpckhps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# UNPCKHPS 4-692 PAGE 1812 LINE 93821
|
|
define pcodeop vunpckhps_avx512f ;
|
|
:VUNPCKHPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x15; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vunpckhps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# UNPCKLPD 4-696 PAGE 1816 LINE 94045
|
|
define pcodeop vunpcklpd_avx512vl ;
|
|
:VUNPCKLPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vunpcklpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# UNPCKLPD 4-696 PAGE 1816 LINE 94048
|
|
:VUNPCKLPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vunpcklpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# UNPCKLPD 4-696 PAGE 1816 LINE 94051
|
|
define pcodeop vunpcklpd_avx512f ;
|
|
:VUNPCKLPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x14; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vunpcklpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# UNPCKLPS 4-700 PAGE 1820 LINE 94231
|
|
define pcodeop vunpcklps_avx512vl ;
|
|
:VUNPCKLPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vunpcklps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# UNPCKLPS 4-700 PAGE 1820 LINE 94234
|
|
:VUNPCKLPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vunpcklps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# UNPCKLPS 4-700 PAGE 1820 LINE 94237
|
|
define pcodeop vunpcklps_avx512f ;
|
|
:VUNPCKLPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x14; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vunpcklps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94615
|
|
define pcodeop valignd_avx512vl ;
|
|
:VALIGND XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x03; ((XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst); imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = valignd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94619
|
|
define pcodeop valignq_avx512vl ;
|
|
:VALIGNQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_XmmReg; byte=0x03; ((XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst); imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = valignq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94623
|
|
:VALIGND YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_YmmReg; byte=0x03; ((YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst); imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = valignd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94627
|
|
:VALIGNQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_YmmReg; byte=0x03; ((YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst); imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = valignq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94631
|
|
define pcodeop valignd_avx512f ;
|
|
:VALIGND ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x03; ((ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst); imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = valignd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94635
|
|
define pcodeop valignq_avx512f ;
|
|
:VALIGNQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x03; ((ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst); imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = valignq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94787
|
|
define pcodeop vblendmpd_avx512vl ;
|
|
:VBLENDMPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x65; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vblendmpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94790
|
|
:VBLENDMPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x65; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vblendmpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94793
|
|
define pcodeop vblendmpd_avx512f ;
|
|
:VBLENDMPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x65; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vblendmpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94796
|
|
define pcodeop vblendmps_avx512vl ;
|
|
:VBLENDMPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x65; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vblendmps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94799
|
|
:VBLENDMPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x65; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vblendmps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94802
|
|
define pcodeop vblendmps_avx512f ;
|
|
:VBLENDMPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x65; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vblendmps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VBROADCAST 5-12 PAGE 1836 LINE 94917
|
|
define pcodeop vbroadcastsd_avx512vl ;
|
|
:VBROADCASTSD YmmReg1^YmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x19; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
YmmResult = vbroadcastsd_avx512vl( XmmReg2_m64 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VBROADCAST 5-12 PAGE 1836 LINE 94920
|
|
define pcodeop vbroadcastsd_avx512f ;
|
|
:VBROADCASTSD ZmmReg1^ZmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x19; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
ZmmResult = vbroadcastsd_avx512f( XmmReg2_m64 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VBROADCAST 5-12 PAGE 1836 LINE 94923
|
|
define pcodeop vbroadcastf32x2_avx512vl ;
|
|
:VBROADCASTF32X2 YmmReg1^YmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x19; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
YmmResult = vbroadcastf32x2_avx512vl( XmmReg2_m64 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VBROADCAST 5-12 PAGE 1836 LINE 94926
|
|
define pcodeop vbroadcastf32x2_avx512dq ;
|
|
:VBROADCASTF32X2 ZmmReg1^ZmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x19; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
ZmmResult = vbroadcastf32x2_avx512dq( XmmReg2_m64 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VBROADCAST 5-12 PAGE 1836 LINE 94929
|
|
define pcodeop vbroadcastss_avx512vl ;
|
|
:VBROADCASTSS XmmReg1^XmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x18; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
XmmResult = vbroadcastss_avx512vl( XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VBROADCAST 5-12 PAGE 1836 LINE 94932
|
|
:VBROADCASTSS YmmReg1^YmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x18; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
YmmResult = vbroadcastss_avx512vl( XmmReg2_m32 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VBROADCAST 5-12 PAGE 1836 LINE 94935
|
|
define pcodeop vbroadcastss_avx512f ;
|
|
:VBROADCASTSS ZmmReg1^ZmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x18; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
ZmmResult = vbroadcastss_avx512f( XmmReg2_m32 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VBROADCAST 5-12 PAGE 1836 LINE 94938
|
|
define pcodeop vbroadcastf32x4_avx512vl ;
|
|
:VBROADCASTF32X4 YmmReg1^YmmOpMask32, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & m128
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
YmmResult = vbroadcastf32x4_avx512vl( m128 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VBROADCAST 5-12 PAGE 1836 LINE 94941
|
|
define pcodeop vbroadcastf32x4_avx512f ;
|
|
:VBROADCASTF32X4 ZmmReg1^ZmmOpMask32, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1A; (ZmmReg1 & ZmmOpMask32) ... & m128
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
ZmmResult = vbroadcastf32x4_avx512f( m128 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VBROADCAST 5-12 PAGE 1836 LINE 94944
|
|
define pcodeop vbroadcastf64x2_avx512vl ;
|
|
:VBROADCASTF64X2 YmmReg1^YmmOpMask64, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m128
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
YmmResult = vbroadcastf64x2_avx512vl( m128 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VBROADCAST 5-12 PAGE 1836 LINE 94947
|
|
define pcodeop vbroadcastf64x2_avx512dq ;
|
|
:VBROADCASTF64X2 ZmmReg1^ZmmOpMask64, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1A; (ZmmReg1 & ZmmOpMask64) ... & m128
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
ZmmResult = vbroadcastf64x2_avx512dq( m128 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VBROADCAST 5-12 PAGE 1836 LINE 94950
|
|
define pcodeop vbroadcastf32x8_avx512dq ;
|
|
:VBROADCASTF32X8 ZmmReg1^ZmmOpMask32, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1B; (ZmmReg1 & ZmmOpMask32) ... & m256
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
ZmmResult = vbroadcastf32x8_avx512dq( m256 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VBROADCAST 5-12 PAGE 1836 LINE 94953
|
|
define pcodeop vbroadcastf64x4_avx512f ;
|
|
:VBROADCASTF64X4 ZmmReg1^ZmmOpMask64, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1B; (ZmmReg1 & ZmmOpMask64) ... & m256
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
ZmmResult = vbroadcastf64x4_avx512f( m256 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPBROADCASTM 5-19 PAGE 1843 LINE 95303
|
|
define pcodeop vpbroadcastmb2q_avx512vl ;
|
|
:VPBROADCASTMB2Q XmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x2A; (XmmReg1 & ZmmReg1) & KReg_rm
|
|
{
|
|
local tmp:16 = vpbroadcastmb2q_avx512vl( KReg_rm );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VPBROADCASTM 5-19 PAGE 1843 LINE 95305
|
|
:VPBROADCASTMB2Q YmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x2A; (YmmReg1 & ZmmReg1) & KReg_rm
|
|
{
|
|
local tmp:32 = vpbroadcastmb2q_avx512vl( KReg_rm );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VPBROADCASTM 5-19 PAGE 1843 LINE 95307
|
|
define pcodeop vpbroadcastmb2q_avx512cd ;
|
|
:VPBROADCASTMB2Q ZmmReg1, KReg_rm is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x2A; ZmmReg1 & KReg_rm
|
|
{
|
|
ZmmReg1 = vpbroadcastmb2q_avx512cd( KReg_rm );
|
|
}
|
|
|
|
# VPBROADCASTM 5-19 PAGE 1843 LINE 95309
|
|
define pcodeop vpbroadcastmw2d_avx512vl ;
|
|
:VPBROADCASTMW2D XmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x3A; (XmmReg1 & ZmmReg1) & KReg_rm
|
|
{
|
|
local tmp:16 = vpbroadcastmw2d_avx512vl( KReg_rm );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VPBROADCASTM 5-19 PAGE 1843 LINE 95311
|
|
:VPBROADCASTMW2D YmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x3A; (YmmReg1 & ZmmReg1) & KReg_rm
|
|
{
|
|
local tmp:32 = vpbroadcastmw2d_avx512vl( KReg_rm );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VPBROADCASTM 5-19 PAGE 1843 LINE 95313
|
|
define pcodeop vpbroadcastmw2d_avx512cd ;
|
|
:VPBROADCASTMW2D ZmmReg1, KReg_rm is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x3A; ZmmReg1 & KReg_rm
|
|
{
|
|
ZmmReg1 = vpbroadcastmw2d_avx512cd( KReg_rm );
|
|
}
|
|
|
|
# VCOMPRESSPD 5-21 PAGE 1845 LINE 95380
|
|
define pcodeop vcompresspd_avx512vl ;
|
|
:VCOMPRESSPD XmmReg2^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0x8A; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmMask = XmmReg2;
|
|
build XmmOpMask;
|
|
XmmResult = vcompresspd_avx512vl( XmmReg1, XmmOpMask );
|
|
ZmmReg2 = zext(XmmResult);
|
|
}
|
|
|
|
:VCOMPRESSPD m128^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0x8A; XmmReg1 ... & m128
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmMask = m128;
|
|
build XmmOpMask;
|
|
XmmResult = vcompresspd_avx512vl( XmmReg1, XmmOpMask );
|
|
m128 = XmmResult;
|
|
}
|
|
|
|
# VCOMPRESSPD 5-21 PAGE 1845 LINE 95383
|
|
:VCOMPRESSPD YmmReg2^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0x8A; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmMask = YmmReg2;
|
|
build YmmOpMask;
|
|
YmmResult = vcompresspd_avx512vl( YmmReg1, YmmOpMask );
|
|
ZmmReg2 = zext(YmmResult);
|
|
}
|
|
|
|
:VCOMPRESSPD m256^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0x8A; YmmReg1 ... & m256
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmMask = m256;
|
|
build YmmOpMask;
|
|
YmmResult = vcompresspd_avx512vl( YmmReg1, YmmOpMask );
|
|
m256 = YmmResult;
|
|
}
|
|
|
|
# VCOMPRESSPD 5-21 PAGE 1845 LINE 95386
|
|
define pcodeop vcompresspd_avx512f ;
|
|
:VCOMPRESSPD ZmmReg2^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0x8A; ZmmReg1 & mod=3 & ZmmReg2
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
ZmmMask = ZmmReg2;
|
|
build ZmmOpMask;
|
|
ZmmResult = vcompresspd_avx512f( ZmmReg1, ZmmOpMask );
|
|
ZmmReg2 = ZmmResult;
|
|
}
|
|
|
|
:VCOMPRESSPD m512^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0x8A; ZmmReg1 ... & m512
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
ZmmMask = m512;
|
|
build ZmmOpMask;
|
|
ZmmResult = vcompresspd_avx512f( ZmmReg1, ZmmOpMask );
|
|
m512 = ZmmResult;
|
|
}
|
|
|
|
# VCOMPRESSPS 5-23 PAGE 1847 LINE 95481
|
|
define pcodeop vcompressps_avx512vl ;
|
|
:VCOMPRESSPS XmmReg2^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0x8A; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmMask = XmmReg2;
|
|
build XmmOpMask;
|
|
XmmResult = vcompressps_avx512vl( XmmReg1, XmmOpMask );
|
|
ZmmReg2 = zext(XmmResult);
|
|
}
|
|
|
|
:VCOMPRESSPS m128^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0x8A; XmmReg1 ... & m128
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmMask = m128;
|
|
build XmmOpMask;
|
|
XmmResult = vcompressps_avx512vl( XmmReg1, XmmOpMask );
|
|
m128 = XmmResult;
|
|
}
|
|
|
|
# VCOMPRESSPS 5-23 PAGE 1847 LINE 95484
|
|
:VCOMPRESSPS YmmReg2^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0x8A; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmMask = YmmReg2;
|
|
build YmmOpMask;
|
|
YmmResult = vcompressps_avx512vl( YmmReg1, YmmOpMask );
|
|
ZmmReg2 = zext(YmmResult);
|
|
}
|
|
|
|
:VCOMPRESSPS m256^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0x8A; YmmReg1 ... & m256
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmMask = m256;
|
|
build YmmOpMask;
|
|
YmmResult = vcompressps_avx512vl( YmmReg1, YmmOpMask );
|
|
m256 = YmmResult;
|
|
}
|
|
|
|
# VCOMPRESSPS 5-23 PAGE 1847 LINE 95487
|
|
define pcodeop vcompressps_avx512f ;
|
|
:VCOMPRESSPS ZmmReg2^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0x8A; ZmmReg1 & mod=3 & ZmmReg2
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
ZmmMask = ZmmReg2;
|
|
build ZmmOpMask;
|
|
ZmmResult = vcompressps_avx512f( ZmmReg1, ZmmOpMask );
|
|
ZmmReg2 = ZmmResult;
|
|
}
|
|
|
|
:VCOMPRESSPS m512^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0x8A; ZmmReg1 ... & m512
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
ZmmMask = m512;
|
|
build ZmmOpMask;
|
|
ZmmResult = vcompressps_avx512f( ZmmReg1, ZmmOpMask );
|
|
m512 = ZmmResult;
|
|
}
|
|
|
|
# VCVTPD2QQ 5-25 PAGE 1849 LINE 95583
|
|
define pcodeop vcvtpd2qq_avx512vl ;
|
|
:VCVTPD2QQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7B; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvtpd2qq_avx512vl( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTPD2QQ 5-25 PAGE 1849 LINE 95586
|
|
:VCVTPD2QQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7B; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vcvtpd2qq_avx512vl( YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTPD2QQ 5-25 PAGE 1849 LINE 95589
|
|
define pcodeop vcvtpd2qq_avx512dq ;
|
|
:VCVTPD2QQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7B; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vcvtpd2qq_avx512dq( ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTPD2UDQ 5-28 PAGE 1852 LINE 95706
|
|
define pcodeop vcvtpd2udq_avx512vl ;
|
|
:VCVTPD2UDQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvtpd2udq_avx512vl( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTPD2UDQ 5-28 PAGE 1852 LINE 95709
|
|
:VCVTPD2UDQ XmmReg1^XmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvtpd2udq_avx512vl( YmmReg2_m256_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTPD2UDQ 5-28 PAGE 1852 LINE 95712
|
|
define pcodeop vcvtpd2udq_avx512f ;
|
|
:VCVTPD2UDQ YmmReg1^YmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vcvtpd2udq_avx512f( ZmmReg2_m512_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTPD2UQQ 5-31 PAGE 1855 LINE 95833
|
|
define pcodeop vcvtpd2uqq_avx512vl ;
|
|
:VCVTPD2UQQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvtpd2uqq_avx512vl( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTPD2UQQ 5-31 PAGE 1855 LINE 95836
|
|
:VCVTPD2UQQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vcvtpd2uqq_avx512vl( YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTPD2UQQ 5-31 PAGE 1855 LINE 95839
|
|
define pcodeop vcvtpd2uqq_avx512dq ;
|
|
:VCVTPD2UQQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vcvtpd2uqq_avx512dq( ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTPH2PS 5-34 PAGE 1858 LINE 95963
|
|
define pcodeop vcvtph2ps_avx512vl ;
|
|
:VCVTPH2PS XmmReg1^XmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x13; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
|
|
{
|
|
XmmResult = vcvtph2ps_avx512vl( XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTPH2PS 5-34 PAGE 1858 LINE 95966
|
|
:VCVTPH2PS YmmReg1^YmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x13; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
|
|
{
|
|
YmmResult = vcvtph2ps_avx512vl( XmmReg2_m128 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTPH2PS 5-34 PAGE 1858 LINE 95969
|
|
define pcodeop vcvtph2ps_avx512f ;
|
|
:VCVTPH2PS ZmmReg1^ZmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x13; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
|
|
{
|
|
ZmmResult = vcvtph2ps_avx512f( YmmReg2_m256 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTPS2PH 5-37 PAGE 1861 LINE 96116
|
|
# INFO mnemonic VCVTPS2PH was found in ../../../../../../../ghidra/Ghidra/Processors/x86/data/languages/avx512_manual.sinc
|
|
|
|
# VCVTPS2PH 5-37 PAGE 1861 LINE 96119
|
|
# INFO mnemonic VCVTPS2PH was found in ../../../../../../../ghidra/Ghidra/Processors/x86/data/languages/avx512_manual.sinc
|
|
|
|
# VCVTPS2PH 5-37 PAGE 1861 LINE 96122
|
|
# INFO mnemonic VCVTPS2PH was found in ../../../../../../../ghidra/Ghidra/Processors/x86/data/languages/avx512_manual.sinc
|
|
|
|
# VCVTPS2UDQ 5-41 PAGE 1865 LINE 96305
|
|
define pcodeop vcvtps2udq_avx512vl ;
|
|
:VCVTPS2UDQ XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvtps2udq_avx512vl( XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTPS2UDQ 5-41 PAGE 1865 LINE 96309
|
|
:VCVTPS2UDQ YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x79; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vcvtps2udq_avx512vl( YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTPS2UDQ 5-41 PAGE 1865 LINE 96313
|
|
define pcodeop vcvtps2udq_avx512f ;
|
|
:VCVTPS2UDQ ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x79; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vcvtps2udq_avx512f( ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTPS2QQ 5-44 PAGE 1868 LINE 96434
|
|
define pcodeop vcvtps2qq_avx512vl ;
|
|
:VCVTPS2QQ XmmReg1^XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7B; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)
|
|
{
|
|
XmmResult = vcvtps2qq_avx512vl( XmmReg2_m64_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTPS2QQ 5-44 PAGE 1868 LINE 96437
|
|
:VCVTPS2QQ YmmReg1^YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7B; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)
|
|
{
|
|
YmmResult = vcvtps2qq_avx512vl( XmmReg2_m128_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTPS2QQ 5-44 PAGE 1868 LINE 96440
|
|
define pcodeop vcvtps2qq_avx512dq ;
|
|
:VCVTPS2QQ ZmmReg1^ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7B; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)
|
|
{
|
|
ZmmResult = vcvtps2qq_avx512dq( YmmReg2_m256_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTPS2UQQ 5-47 PAGE 1871 LINE 96560
|
|
define pcodeop vcvtps2uqq_avx512vl ;
|
|
:VCVTPS2UQQ XmmReg1^XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)
|
|
{
|
|
XmmResult = vcvtps2uqq_avx512vl( XmmReg2_m64_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTPS2UQQ 5-47 PAGE 1871 LINE 96563
|
|
:VCVTPS2UQQ YmmReg1^YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x79; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)
|
|
{
|
|
YmmResult = vcvtps2uqq_avx512vl( XmmReg2_m128_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTPS2UQQ 5-47 PAGE 1871 LINE 96566
|
|
define pcodeop vcvtps2uqq_avx512dq ;
|
|
:VCVTPS2UQQ ZmmReg1^ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x79; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)
|
|
{
|
|
ZmmResult = vcvtps2uqq_avx512dq( YmmReg2_m256_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTQQ2PD 5-50 PAGE 1874 LINE 96686
|
|
define pcodeop vcvtqq2pd_avx512vl ;
|
|
:VCVTQQ2PD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvtqq2pd_avx512vl( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTQQ2PD 5-50 PAGE 1874 LINE 96689
|
|
:VCVTQQ2PD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vcvtqq2pd_avx512vl( YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTQQ2PD 5-50 PAGE 1874 LINE 96692
|
|
define pcodeop vcvtqq2pd_avx512dq ;
|
|
:VCVTQQ2PD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vcvtqq2pd_avx512dq( ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTQQ2PS 5-52 PAGE 1876 LINE 96797
|
|
define pcodeop vcvtqq2ps_avx512vl ;
|
|
:VCVTQQ2PS XmmReg1^XmmOpMask32, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x5B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvtqq2ps_avx512vl( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTQQ2PS 5-52 PAGE 1876 LINE 96800
|
|
:VCVTQQ2PS XmmReg1^XmmOpMask32, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x5B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvtqq2ps_avx512vl( YmmReg2_m256_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTQQ2PS 5-52 PAGE 1876 LINE 96803
|
|
define pcodeop vcvtqq2ps_avx512dq ;
|
|
:VCVTQQ2PS YmmReg1^YmmOpMask32, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x5B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vcvtqq2ps_avx512dq( ZmmReg2_m512_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTSD2USI 5-54 PAGE 1878 LINE 96907
|
|
define pcodeop vcvtsd2usi_avx512f ;
|
|
:VCVTSD2USI Reg32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x79; (Reg32 & check_Reg32_dest) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)
|
|
{
|
|
Reg32 = vcvtsd2usi_avx512f( XmmReg2_m64 );
|
|
build check_Reg32_dest;
|
|
}
|
|
|
|
# VCVTSD2USI 5-54 PAGE 1878 LINE 96909
|
|
@ifdef IA64
|
|
:VCVTSD2USI Reg64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x79; Reg64 ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)
|
|
{
|
|
Reg64 = vcvtsd2usi_avx512f( XmmReg2_m64 );
|
|
}
|
|
@endif
|
|
|
|
# VCVTSS2USI 5-55 PAGE 1879 LINE 96967
|
|
define pcodeop vcvtss2usi_avx512f ;
|
|
:VCVTSS2USI Reg32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x79; (Reg32 & check_Reg32_dest) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)
|
|
{
|
|
Reg32 = vcvtss2usi_avx512f( XmmReg2_m32 );
|
|
build check_Reg32_dest;
|
|
}
|
|
|
|
# VCVTSS2USI 5-55 PAGE 1879 LINE 96969
|
|
@ifdef IA64
|
|
:VCVTSS2USI Reg64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x79; Reg64 ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)
|
|
{
|
|
Reg64 = vcvtss2usi_avx512f( XmmReg2_m32 );
|
|
}
|
|
@endif
|
|
|
|
# VCVTTPD2QQ 5-57 PAGE 1881 LINE 97040
|
|
define pcodeop vcvttpd2qq_avx512vl ;
|
|
:VCVTTPD2QQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvttpd2qq_avx512vl( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTTPD2QQ 5-57 PAGE 1881 LINE 97043
|
|
:VCVTTPD2QQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vcvttpd2qq_avx512vl( YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTTPD2QQ 5-57 PAGE 1881 LINE 97046
|
|
define pcodeop vcvttpd2qq_avx512dq ;
|
|
:VCVTTPD2QQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vcvttpd2qq_avx512dq( ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTTPD2UDQ 5-59 PAGE 1883 LINE 97147
|
|
define pcodeop vcvttpd2udq_avx512vl ;
|
|
:VCVTTPD2UDQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvttpd2udq_avx512vl( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTTPD2UDQ 5-59 PAGE 1883 LINE 97152
|
|
:VCVTTPD2UDQ XmmReg1^XmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvttpd2udq_avx512vl( YmmReg2_m256_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTTPD2UDQ 5-59 PAGE 1883 LINE 97156
|
|
define pcodeop vcvttpd2udq_avx512f ;
|
|
:VCVTTPD2UDQ YmmReg1^YmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vcvttpd2udq_avx512f( ZmmReg2_m512_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTTPD2UQQ 5-62 PAGE 1886 LINE 97272
|
|
define pcodeop vcvttpd2uqq_avx512vl ;
|
|
:VCVTTPD2UQQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvttpd2uqq_avx512vl( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTTPD2UQQ 5-62 PAGE 1886 LINE 97276
|
|
:VCVTTPD2UQQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vcvttpd2uqq_avx512vl( YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTTPD2UQQ 5-62 PAGE 1886 LINE 97280
|
|
define pcodeop vcvttpd2uqq_avx512dq ;
|
|
:VCVTTPD2UQQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vcvttpd2uqq_avx512dq( ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTTPS2UDQ 5-64 PAGE 1888 LINE 97385
|
|
define pcodeop vcvttps2udq_avx512vl ;
|
|
:VCVTTPS2UDQ XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvttps2udq_avx512vl( XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTTPS2UDQ 5-64 PAGE 1888 LINE 97389
|
|
:VCVTTPS2UDQ YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x78; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vcvttps2udq_avx512vl( YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTTPS2UDQ 5-64 PAGE 1888 LINE 97393
|
|
define pcodeop vcvttps2udq_avx512f ;
|
|
:VCVTTPS2UDQ ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x78; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vcvttps2udq_avx512f( ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTTPS2QQ 5-66 PAGE 1890 LINE 97497
|
|
define pcodeop vcvttps2qq_avx512vl ;
|
|
:VCVTTPS2QQ XmmReg1^XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)
|
|
{
|
|
XmmResult = vcvttps2qq_avx512vl( XmmReg2_m64_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTTPS2QQ 5-66 PAGE 1890 LINE 97500
|
|
:VCVTTPS2QQ YmmReg1^YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)
|
|
{
|
|
YmmResult = vcvttps2qq_avx512vl( XmmReg2_m128_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTTPS2QQ 5-66 PAGE 1890 LINE 97503
|
|
define pcodeop vcvttps2qq_avx512dq ;
|
|
:VCVTTPS2QQ ZmmReg1^ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)
|
|
{
|
|
ZmmResult = vcvttps2qq_avx512dq( YmmReg2_m256_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTTPS2UQQ 5-68 PAGE 1892 LINE 97608
|
|
define pcodeop vcvttps2uqq_avx512vl ;
|
|
:VCVTTPS2UQQ XmmReg1^XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)
|
|
{
|
|
XmmResult = vcvttps2uqq_avx512vl( XmmReg2_m64_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTTPS2UQQ 5-68 PAGE 1892 LINE 97611
|
|
:VCVTTPS2UQQ YmmReg1^YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x78; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)
|
|
{
|
|
YmmResult = vcvttps2uqq_avx512vl( XmmReg2_m128_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTTPS2UQQ 5-68 PAGE 1892 LINE 97615
|
|
define pcodeop vcvttps2uqq_avx512dq ;
|
|
:VCVTTPS2UQQ ZmmReg1^ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x78; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)
|
|
{
|
|
ZmmResult = vcvttps2uqq_avx512dq( YmmReg2_m256_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTTSD2USI 5-70 PAGE 1894 LINE 97722
|
|
define pcodeop vcvttsd2usi_avx512f ;
|
|
:VCVTTSD2USI Reg32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x78; (Reg32 & check_Reg32_dest) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)
|
|
{
|
|
Reg32 = vcvttsd2usi_avx512f( XmmReg2_m64 );
|
|
build check_Reg32_dest;
|
|
}
|
|
|
|
# VCVTTSD2USI 5-70 PAGE 1894 LINE 97725
|
|
@ifdef IA64
|
|
:VCVTTSD2USI Reg64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x78; Reg64 ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)
|
|
{
|
|
Reg64 = vcvttsd2usi_avx512f( XmmReg2_m64 );
|
|
}
|
|
@endif
|
|
|
|
# VCVTTSS2USI 5-71 PAGE 1895 LINE 97782
|
|
define pcodeop vcvttss2usi_avx512f ;
|
|
:VCVTTSS2USI Reg32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x78; (Reg32 & check_Reg32_dest) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)
|
|
{
|
|
Reg32 = vcvttss2usi_avx512f( XmmReg2_m32 );
|
|
build check_Reg32_dest;
|
|
}
|
|
|
|
# VCVTTSS2USI 5-71 PAGE 1895 LINE 97785
|
|
@ifdef IA64
|
|
:VCVTTSS2USI Reg64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x78; Reg64 ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 5; ] # (TupleType T1F)
|
|
{
|
|
Reg64 = vcvttss2usi_avx512f( XmmReg2_m32 );
|
|
}
|
|
@endif
|
|
|
|
# VCVTUDQ2PD 5-73 PAGE 1897 LINE 97852
|
|
define pcodeop vcvtudq2pd_avx512vl ;
|
|
:VCVTUDQ2PD XmmReg1^XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)
|
|
{
|
|
XmmResult = vcvtudq2pd_avx512vl( XmmReg2_m64_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTUDQ2PD 5-73 PAGE 1897 LINE 97855
|
|
:VCVTUDQ2PD YmmReg1^YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)
|
|
{
|
|
YmmResult = vcvtudq2pd_avx512vl( XmmReg2_m128_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTUDQ2PD 5-73 PAGE 1897 LINE 97859
|
|
define pcodeop vcvtudq2pd_avx512f ;
|
|
:VCVTUDQ2PD ZmmReg1^ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType HV)
|
|
{
|
|
ZmmResult = vcvtudq2pd_avx512f( YmmReg2_m256_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTUDQ2PS 5-75 PAGE 1899 LINE 97962
|
|
define pcodeop vcvtudq2ps_avx512vl ;
|
|
:VCVTUDQ2PS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvtudq2ps_avx512vl( XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTUDQ2PS 5-75 PAGE 1899 LINE 97965
|
|
:VCVTUDQ2PS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vcvtudq2ps_avx512vl( YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTUDQ2PS 5-75 PAGE 1899 LINE 97968
|
|
define pcodeop vcvtudq2ps_avx512f ;
|
|
:VCVTUDQ2PS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vcvtudq2ps_avx512f( ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTUQQ2PD 5-77 PAGE 1901 LINE 98078
|
|
define pcodeop vcvtuqq2pd_avx512vl ;
|
|
:VCVTUQQ2PD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvtuqq2pd_avx512vl( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTUQQ2PD 5-77 PAGE 1901 LINE 98081
|
|
:VCVTUQQ2PD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vcvtuqq2pd_avx512vl( YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTUQQ2PD 5-77 PAGE 1901 LINE 98084
|
|
define pcodeop vcvtuqq2pd_avx512dq ;
|
|
:VCVTUQQ2PD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vcvtuqq2pd_avx512dq( ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTUQQ2PS 5-79 PAGE 1903 LINE 98193
|
|
define pcodeop vcvtuqq2ps_avx512vl ;
|
|
:VCVTUQQ2PS XmmReg1^XmmOpMask32, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvtuqq2ps_avx512vl( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTUQQ2PS 5-79 PAGE 1903 LINE 98196
|
|
:VCVTUQQ2PS XmmReg1^XmmOpMask32, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vcvtuqq2ps_avx512vl( YmmReg2_m256_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTUQQ2PS 5-79 PAGE 1903 LINE 98199
|
|
define pcodeop vcvtuqq2ps_avx512dq ;
|
|
:VCVTUQQ2PS YmmReg1^YmmOpMask32, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vcvtuqq2ps_avx512dq( ZmmReg2_m512_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTUSI2SD 5-81 PAGE 1905 LINE 98308
|
|
define pcodeop vcvtusi2sd_avx512f ;
|
|
:VCVTUSI2SD XmmReg1, evexV5_XmmReg, rm32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x7B; (XmmReg1 & ZmmReg1) ... & rm32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
local tmp:16 = vcvtusi2sd_avx512f( evexV5_XmmReg, rm32 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VCVTUSI2SD 5-81 PAGE 1905 LINE 98311
|
|
@ifdef IA64
|
|
:VCVTUSI2SD XmmReg1, evexV5_XmmReg, rm64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x7B; (XmmReg1 & ZmmReg1) ... & rm64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
local tmp:16 = vcvtusi2sd_avx512f( evexV5_XmmReg, rm64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
@endif
|
|
|
|
# VCVTUSI2SS 5-83 PAGE 1907 LINE 98381
|
|
define pcodeop vcvtusi2ss_avx512f ;
|
|
:VCVTUSI2SS XmmReg1, evexV5_XmmReg, rm32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x7B; (XmmReg1 & ZmmReg1) ... & rm32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
local tmp:16 = vcvtusi2ss_avx512f( evexV5_XmmReg, rm32 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VCVTUSI2SS 5-83 PAGE 1907 LINE 98383
|
|
@ifdef IA64
|
|
:VCVTUSI2SS XmmReg1, evexV5_XmmReg, rm64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x7B; (XmmReg1 & ZmmReg1) ... & rm64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
local tmp:16 = vcvtusi2ss_avx512f( evexV5_XmmReg, rm64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
@endif
|
|
|
|
# VDBPSADBW 5-85 PAGE 1909 LINE 98455
|
|
define pcodeop vdbpsadbw_avx512vl ;
|
|
:VDBPSADBW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x42; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vdbpsadbw_avx512vl( evexV5_XmmReg, XmmReg2_m128, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VDBPSADBW 5-85 PAGE 1909 LINE 98460
|
|
:VDBPSADBW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_YmmReg; byte=0x42; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vdbpsadbw_avx512vl( evexV5_YmmReg, YmmReg2_m256, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VDBPSADBW 5-85 PAGE 1909 LINE 98465
|
|
define pcodeop vdbpsadbw_avx512bw ;
|
|
:VDBPSADBW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x42; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vdbpsadbw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VEXPANDPD 5-89 PAGE 1913 LINE 98660
|
|
define pcodeop vexpandpd_avx512vl ;
|
|
:VEXPANDPD XmmReg1^XmmOpMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x88; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
XmmResult = vexpandpd_avx512vl( XmmReg2_m128, XmmOpMask );
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VEXPANDPD 5-89 PAGE 1913 LINE 98663
|
|
:VEXPANDPD YmmReg1^YmmOpMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x88; (YmmReg1 & ZmmReg1 & YmmOpMask) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask;
|
|
YmmResult = vexpandpd_avx512vl( YmmReg2_m256, YmmOpMask );
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VEXPANDPD 5-89 PAGE 1913 LINE 98665
|
|
define pcodeop vexpandpd_avx512f ;
|
|
:VEXPANDPD ZmmReg1^ZmmOpMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x88; (ZmmReg1 & ZmmOpMask) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask;
|
|
ZmmResult = vexpandpd_avx512f( ZmmReg2_m512, ZmmOpMask );
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VEXPANDPS 5-91 PAGE 1915 LINE 98748
|
|
define pcodeop vexpandps_avx512vl ;
|
|
:VEXPANDPS XmmReg1^XmmOpMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x88; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
XmmResult = vexpandps_avx512vl( XmmReg2_m128, XmmOpMask );
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VEXPANDPS 5-91 PAGE 1915 LINE 98750
|
|
:VEXPANDPS YmmReg1^YmmOpMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x88; (YmmReg1 & ZmmReg1 & YmmOpMask) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask;
|
|
YmmResult = vexpandps_avx512vl( YmmReg2_m256 );
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VEXPANDPS 5-91 PAGE 1915 LINE 98752
|
|
define pcodeop vexpandps_avx512f ;
|
|
:VEXPANDPS ZmmReg1^ZmmOpMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x88; (ZmmReg1 & ZmmOpMask) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask;
|
|
ZmmResult = vexpandps_avx512f( ZmmReg2_m512, ZmmOpMask );
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VEXP2PD 5-95 PAGE 1919 LINE 98936
|
|
define pcodeop vexp2pd_avx512er ;
|
|
:VEXP2PD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xC8; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vexp2pd_avx512er( ZmmReg1, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VEXP2PS 5-97 PAGE 1921 LINE 99019
|
|
define pcodeop vexp2ps_avx512er ;
|
|
:VEXP2PS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xC8; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vexp2ps_avx512er( ZmmReg1, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99105
|
|
define pcodeop vextractf32x4_avx512vl ;
|
|
:VEXTRACTF32X4 XmmReg2^XmmOpMask32, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x19; YmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
XmmResult = vextractf32x4_avx512vl( YmmReg1, imm8:1 );
|
|
XmmMask = XmmReg2;
|
|
build XmmOpMask32;
|
|
ZmmReg2 = zext(XmmResult);
|
|
}
|
|
|
|
:VEXTRACTF32X4 m128^XmmOpMask32, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x19; YmmReg1 ... & m128; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
XmmResult = vextractf32x4_avx512vl( YmmReg1, imm8:1 );
|
|
XmmMask = m128;
|
|
build XmmOpMask32;
|
|
m128 = XmmResult;
|
|
}
|
|
|
|
|
|
# VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99108
|
|
define pcodeop vextractf32x4_avx512f ;
|
|
:VEXTRACTF32x4 XmmReg2^XmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x19; ZmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
XmmResult = vextractf32x4_avx512f( ZmmReg1, imm8:1 );
|
|
XmmMask = XmmReg2;
|
|
build XmmOpMask32;
|
|
ZmmReg2 = zext(XmmResult);
|
|
}
|
|
|
|
:VEXTRACTF32x4 m128^XmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x19; ZmmReg1 ... & m128; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
XmmResult = vextractf32x4_avx512f( ZmmReg1, imm8:1 );
|
|
XmmMask = m128;
|
|
build XmmOpMask32;
|
|
m128 = XmmResult;
|
|
}
|
|
|
|
# VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99111
|
|
define pcodeop vextractf64x2_avx512vl ;
|
|
:VEXTRACTF64X2 XmmReg2^XmmOpMask64, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x19; YmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
XmmResult = vextractf64x2_avx512vl( YmmReg1, imm8:1 );
|
|
XmmMask = XmmReg2;
|
|
build XmmOpMask64;
|
|
ZmmReg2 = zext(XmmResult);
|
|
}
|
|
|
|
:VEXTRACTF64X2 m128^XmmOpMask64, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x19; YmmReg1 ... & m128; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
XmmResult = vextractf64x2_avx512vl( YmmReg1, imm8:1 );
|
|
XmmMask = m128;
|
|
build XmmOpMask64;
|
|
m128 = XmmResult;
|
|
}
|
|
|
|
|
|
# VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99114
|
|
define pcodeop vextractf64x2_avx512dq ;
|
|
:VEXTRACTF64X2 XmmReg2^XmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x19; ZmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
XmmResult = vextractf64x2_avx512dq( ZmmReg1, imm8:1 );
|
|
XmmMask = XmmReg2;
|
|
build XmmOpMask64;
|
|
ZmmReg2 = zext(XmmResult);
|
|
}
|
|
|
|
:VEXTRACTF64X2 m128^XmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x19; ZmmReg1 ... & m128; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
XmmResult = vextractf64x2_avx512dq( ZmmReg1, imm8:1 );
|
|
XmmMask = m128;
|
|
build XmmOpMask64;
|
|
m128 = XmmResult;
|
|
}
|
|
|
|
# VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99117
|
|
define pcodeop vextractf32x8_avx512dq ;
|
|
:VEXTRACTF32X8 YmmReg2^YmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask32; byte=0x1B; ZmmReg1 & mod=3 & YmmReg2 & ZmmReg2; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
YmmResult = vextractf32x8_avx512dq( ZmmReg1, imm8:1 );
|
|
YmmMask = YmmReg2;
|
|
build YmmOpMask32;
|
|
ZmmReg2 = zext(YmmResult);
|
|
}
|
|
|
|
:VEXTRACTF32X8 m256^YmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask32; byte=0x1B; ZmmReg1 ... & m256; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
YmmResult = vextractf32x8_avx512dq( ZmmReg1, imm8:1 );
|
|
YmmMask = m256;
|
|
build YmmOpMask32;
|
|
m256 = YmmResult;
|
|
}
|
|
|
|
# VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99120
|
|
define pcodeop vextractf64x4_avx512f ;
|
|
:VEXTRACTF64x4 YmmReg2^YmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask64; byte=0x1B; ZmmReg1 & mod=3 & YmmReg2 & ZmmReg2; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
YmmResult = vextractf64x4_avx512f( ZmmReg1, imm8:1 );
|
|
YmmMask = YmmReg2;
|
|
build YmmOpMask64;
|
|
ZmmReg2 = zext(YmmResult);
|
|
}
|
|
|
|
:VEXTRACTF64x4 m256^YmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask64; byte=0x1B; ZmmReg1 ... & m256; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
YmmResult = vextractf64x4_avx512f( ZmmReg1, imm8:1 );
|
|
YmmMask = m256;
|
|
build YmmOpMask64;
|
|
m256 = YmmResult;
|
|
}
|
|
|
|
# VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99435
|
|
define pcodeop vextracti32x4_avx512vl ;
|
|
:VEXTRACTI32X4 XmmReg2^XmmOpMask32, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x39; YmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
XmmResult = vextracti32x4_avx512vl( YmmReg1, imm8:1 );
|
|
XmmMask = XmmReg2;
|
|
build XmmOpMask32;
|
|
ZmmReg2 = zext(XmmResult);
|
|
}
|
|
|
|
:VEXTRACTI32X4 m128^XmmOpMask32, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x39; YmmReg1 ... & m128; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
XmmResult = vextracti32x4_avx512vl( YmmReg1, imm8:1 );
|
|
XmmMask = m128;
|
|
build XmmOpMask32;
|
|
m128 = XmmResult;
|
|
}
|
|
|
|
# VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99438
|
|
define pcodeop vextracti32x4_avx512f ;
|
|
:VEXTRACTI32x4 XmmReg2^XmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x39; ZmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
XmmResult = vextracti32x4_avx512f( ZmmReg1, imm8:1 );
|
|
XmmMask = XmmReg2;
|
|
build XmmOpMask32;
|
|
ZmmReg2 = zext(XmmResult);
|
|
}
|
|
|
|
:VEXTRACTI32x4 m128^XmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x39; ZmmReg1 ... & m128; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
XmmResult = vextracti32x4_avx512f( ZmmReg1, imm8:1 );
|
|
XmmMask = m128;
|
|
build XmmOpMask32;
|
|
m128 = XmmResult;
|
|
}
|
|
|
|
# VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99441
|
|
define pcodeop vextracti64x2_avx512vl ;
|
|
:VEXTRACTI64X2 XmmReg2^XmmOpMask64, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x39; YmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
XmmResult = vextracti64x2_avx512vl( YmmReg1, imm8:1 );
|
|
XmmMask = XmmReg2;
|
|
build XmmOpMask64;
|
|
ZmmReg2 = zext(XmmResult);
|
|
}
|
|
|
|
:VEXTRACTI64X2 m128^XmmOpMask64, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x39; YmmReg1 ... & m128; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
XmmResult = vextracti64x2_avx512vl( YmmReg1, imm8:1 );
|
|
XmmMask = m128;
|
|
build XmmOpMask64;
|
|
m128 = XmmResult;
|
|
}
|
|
|
|
# VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99444
|
|
define pcodeop vextracti64x2_avx512dq ;
|
|
:VEXTRACTI64X2 XmmReg2^XmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x39; ZmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
XmmResult = vextracti64x2_avx512dq( ZmmReg1, imm8:1 );
|
|
XmmMask = XmmReg2;
|
|
build XmmOpMask64;
|
|
ZmmReg2 = zext(XmmResult);
|
|
}
|
|
|
|
:VEXTRACTI64X2 m128^XmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x39; ZmmReg1 ... & m128; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
XmmResult = vextracti64x2_avx512dq( ZmmReg1, imm8:1 );
|
|
XmmMask = m128;
|
|
build XmmOpMask64;
|
|
m128 = XmmResult;
|
|
}
|
|
|
|
# VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99447
|
|
define pcodeop vextracti32x8_avx512dq ;
|
|
:VEXTRACTI32X8 YmmReg2^YmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask32; byte=0x3B; ZmmReg1 & mod=3 & YmmReg2 & ZmmReg2; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
YmmResult = vextracti32x8_avx512dq( ZmmReg1, imm8:1 );
|
|
YmmMask = YmmReg2;
|
|
build YmmOpMask32;
|
|
ZmmReg2 = zext(YmmResult);
|
|
}
|
|
|
|
:VEXTRACTI32X8 m256^YmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask32; byte=0x3B; ZmmReg1 ... & m256; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
YmmResult = vextracti32x8_avx512dq( ZmmReg1, imm8:1 );
|
|
YmmMask = m256;
|
|
build YmmOpMask32;
|
|
m256 = YmmResult;
|
|
}
|
|
|
|
# VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99450
|
|
define pcodeop vextracti64x4_avx512f ;
|
|
:VEXTRACTI64x4 YmmReg2^YmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask64; byte=0x3B; ZmmReg1 & mod=3 & YmmReg2 & ZmmReg2; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
YmmResult = vextracti64x4_avx512f( ZmmReg1, imm8:1 );
|
|
YmmMask = YmmReg2;
|
|
build YmmOpMask64;
|
|
ZmmReg2 = zext(YmmResult);
|
|
}
|
|
|
|
:VEXTRACTI64x4 m256^YmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask64; byte=0x3B; ZmmReg1 ... & m256; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
YmmResult = vextracti64x4_avx512f( ZmmReg1, imm8:1 );
|
|
YmmMask = m256;
|
|
build YmmOpMask64;
|
|
m256 = YmmResult;
|
|
}
|
|
# VFIXUPIMMPD 5-112 PAGE 1936 LINE 99754
|
|
define pcodeop vfixupimmpd_avx512vl ;
|
|
:VFIXUPIMMPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfixupimmpd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFIXUPIMMPD 5-112 PAGE 1936 LINE 99757
|
|
:VFIXUPIMMPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfixupimmpd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFIXUPIMMPD 5-112 PAGE 1936 LINE 99760
|
|
define pcodeop vfixupimmpd_avx512f ;
|
|
:VFIXUPIMMPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x54; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfixupimmpd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFIXUPIMMPS 5-116 PAGE 1940 LINE 99957
|
|
define pcodeop vfixupimmps_avx512vl ;
|
|
:VFIXUPIMMPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfixupimmps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFIXUPIMMPS 5-116 PAGE 1940 LINE 99960
|
|
:VFIXUPIMMPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfixupimmps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFIXUPIMMPS 5-116 PAGE 1940 LINE 99963
|
|
define pcodeop vfixupimmps_avx512f ;
|
|
:VFIXUPIMMPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x54; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfixupimmps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFIXUPIMMSD 5-120 PAGE 1944 LINE 100159
|
|
define pcodeop vfixupimmsd_avx512f ;
|
|
:VFIXUPIMMSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64; imm8
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vfixupimmsd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFIXUPIMMSS 5-123 PAGE 1947 LINE 100331
|
|
define pcodeop vfixupimmss_avx512f ;
|
|
:VFIXUPIMMSS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32; imm8
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vfixupimmss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100523
|
|
define pcodeop vfmadd132pd_avx512vl ;
|
|
:VFMADD132PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x98; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
{
|
|
XmmResult = vfmadd132pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100526
|
|
define pcodeop vfmadd213pd_avx512vl ;
|
|
:VFMADD213PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xA8; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfmadd213pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100529
|
|
define pcodeop vfmadd231pd_avx512vl ;
|
|
:VFMADD231PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xB8; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfmadd231pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100532
|
|
:VFMADD132PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x98; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmadd132pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100535
|
|
:VFMADD213PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xA8; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmadd213pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100538
|
|
:VFMADD231PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xB8; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmadd231pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100541
|
|
define pcodeop vfmadd132pd_avx512f ;
|
|
:VFMADD132PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x98; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmadd132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100544
|
|
define pcodeop vfmadd213pd_avx512f ;
|
|
:VFMADD213PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xA8; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmadd213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100547
|
|
define pcodeop vfmadd231pd_avx512f ;
|
|
:VFMADD231PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xB8; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmadd231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100884
|
|
define pcodeop vfmadd132ps_avx512vl ;
|
|
:VFMADD132PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x98; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfmadd132ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100887
|
|
define pcodeop vfmadd213ps_avx512vl ;
|
|
:VFMADD213PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xA8; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfmadd213ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100890
|
|
define pcodeop vfmadd231ps_avx512vl ;
|
|
:VFMADD231PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xB8; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfmadd231ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100893
|
|
:VFMADD132PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x98; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmadd132ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100896
|
|
:VFMADD213PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xA8; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmadd213ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100899
|
|
:VFMADD231PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xB8; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmadd231ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100902
|
|
define pcodeop vfmadd132ps_avx512f ;
|
|
:VFMADD132PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x98; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmadd132ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100905
|
|
define pcodeop vfmadd213ps_avx512f ;
|
|
:VFMADD213PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xA8; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmadd213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100908
|
|
define pcodeop vfmadd231ps_avx512f ;
|
|
:VFMADD231PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xB8; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmadd231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMADD132SD/VFMADD213SD/VFMADD231SD 5-140 PAGE 1964 LINE 101235
|
|
define pcodeop vfmadd132sd_avx512f ;
|
|
:VFMADD132SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x99; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vfmadd132sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMADD132SD/VFMADD213SD/VFMADD231SD 5-140 PAGE 1964 LINE 101238
|
|
define pcodeop vfmadd213sd_avx512f ;
|
|
:VFMADD213SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xA9; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vfmadd213sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMADD132SD/VFMADD213SD/VFMADD231SD 5-140 PAGE 1964 LINE 101241
|
|
define pcodeop vfmadd231sd_avx512f ;
|
|
:VFMADD231SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xB9; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vfmadd231sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-143 PAGE 1967 LINE 101403
|
|
define pcodeop vfmadd132ss_avx512f ;
|
|
:VFMADD132SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x99; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vfmadd132ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-143 PAGE 1967 LINE 101406
|
|
define pcodeop vfmadd213ss_avx512f ;
|
|
:VFMADD213SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xA9; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vfmadd213ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMADD132SS/VFMADD213SS/VFMADD231SS 5-143 PAGE 1967 LINE 101409
|
|
define pcodeop vfmadd231ss_avx512f ;
|
|
:VFMADD231SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xB9; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vfmadd231ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101585
|
|
define pcodeop vfmaddsub213pd_avx512vl ;
|
|
:VFMADDSUB213PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xA6; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfmaddsub213pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101589
|
|
define pcodeop vfmaddsub231pd_avx512vl ;
|
|
:VFMADDSUB231PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xB6; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfmaddsub231pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101593
|
|
define pcodeop vfmaddsub132pd_avx512vl ;
|
|
:VFMADDSUB132PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x96; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfmaddsub132pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101597
|
|
:VFMADDSUB213PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xA6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmaddsub213pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101601
|
|
:VFMADDSUB231PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xB6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmaddsub231pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101605
|
|
:VFMADDSUB132PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x96; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmaddsub132pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-147 PAGE 1971 LINE 101621
|
|
define pcodeop vfmaddsub213pd_avx512f ;
|
|
:VFMADDSUB213PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xA6; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmaddsub213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-147 PAGE 1971 LINE 101625
|
|
define pcodeop vfmaddsub231pd_avx512f ;
|
|
:VFMADDSUB231PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xB6; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmaddsub231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-147 PAGE 1971 LINE 101629
|
|
define pcodeop vfmaddsub132pd_avx512f ;
|
|
:VFMADDSUB132PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x96; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmaddsub132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102024
|
|
define pcodeop vfmaddsub213ps_avx512vl ;
|
|
:VFMADDSUB213PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xA6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfmaddsub213ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102028
|
|
define pcodeop vfmaddsub231ps_avx512vl ;
|
|
:VFMADDSUB231PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xB6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfmaddsub231ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102031
|
|
define pcodeop vfmaddsub132ps_avx512vl ;
|
|
:VFMADDSUB132PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x96; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfmaddsub132ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102034
|
|
:VFMADDSUB213PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xA6; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmaddsub213ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102038
|
|
:VFMADDSUB231PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xB6; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmaddsub231ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102041
|
|
:VFMADDSUB132PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x96; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmaddsub132ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102044
|
|
define pcodeop vfmaddsub213ps_avx512f ;
|
|
:VFMADDSUB213PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xA6; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmaddsub213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102048
|
|
define pcodeop vfmaddsub231ps_avx512f ;
|
|
:VFMADDSUB231PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xB6; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmaddsub231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102051
|
|
define pcodeop vfmaddsub132ps_avx512f ;
|
|
:VFMADDSUB132PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x96; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmaddsub132ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102454
|
|
define pcodeop vfmsubadd132pd_avx512vl ;
|
|
:VFMSUBADD132PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfmsubadd132pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102458
|
|
define pcodeop vfmsubadd213pd_avx512vl ;
|
|
:VFMSUBADD213PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfmsubadd213pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102462
|
|
define pcodeop vfmsubadd231pd_avx512vl ;
|
|
:VFMSUBADD231PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfmsubadd231pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102466
|
|
:VFMSUBADD132PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmsubadd132pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102470
|
|
:VFMSUBADD213PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmsubadd213pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102474
|
|
:VFMSUBADD231PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmsubadd231pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-166 PAGE 1990 LINE 102490
|
|
define pcodeop vfmsubadd132pd_avx512f ;
|
|
:VFMSUBADD132PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x97; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmsubadd132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-166 PAGE 1990 LINE 102494
|
|
define pcodeop vfmsubadd213pd_avx512f ;
|
|
:VFMSUBADD213PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xA7; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmsubadd213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-166 PAGE 1990 LINE 102498
|
|
define pcodeop vfmsubadd231pd_avx512f ;
|
|
:VFMSUBADD231PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xB7; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmsubadd231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102894
|
|
define pcodeop vfmsubadd132ps_avx512vl ;
|
|
:VFMSUBADD132PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfmsubadd132ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102897
|
|
define pcodeop vfmsubadd213ps_avx512vl ;
|
|
:VFMSUBADD213PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfmsubadd213ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102901
|
|
define pcodeop vfmsubadd231ps_avx512vl ;
|
|
:VFMSUBADD231PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfmsubadd231ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102904
|
|
:VFMSUBADD132PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmsubadd132ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102907
|
|
:VFMSUBADD213PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmsubadd213ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102911
|
|
:VFMSUBADD231PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmsubadd231ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102914
|
|
define pcodeop vfmsubadd132ps_avx512f ;
|
|
:VFMSUBADD132PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x97; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmsubadd132ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102917
|
|
define pcodeop vfmsubadd213ps_avx512f ;
|
|
:VFMSUBADD213PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xA7; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmsubadd213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102921
|
|
define pcodeop vfmsubadd231ps_avx512f ;
|
|
:VFMSUBADD231PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xB7; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmsubadd231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103332
|
|
define pcodeop vfmsub132pd_avx512vl ;
|
|
:VFMSUB132PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x9A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfmsub132pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103335
|
|
define pcodeop vfmsub213pd_avx512vl ;
|
|
:VFMSUB213PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xAA; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfmsub213pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103338
|
|
define pcodeop vfmsub231pd_avx512vl ;
|
|
:VFMSUB231PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xBA; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfmsub231pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103341
|
|
:VFMSUB132PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x9A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmsub132pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103344
|
|
:VFMSUB213PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xAA; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmsub213pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103347
|
|
:VFMSUB231PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmsub231pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103350
|
|
define pcodeop vfmsub132pd_avx512f ;
|
|
:VFMSUB132PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x9A; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmsub132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103353
|
|
define pcodeop vfmsub213pd_avx512f ;
|
|
:VFMSUB213PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xAA; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmsub213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103356
|
|
define pcodeop vfmsub231pd_avx512f ;
|
|
:VFMSUB231PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xBA; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmsub231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103692
|
|
define pcodeop vfmsub132ps_avx512vl ;
|
|
:VFMSUB132PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x9A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfmsub132ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103695
|
|
define pcodeop vfmsub213ps_avx512vl ;
|
|
:VFMSUB213PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xAA; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfmsub213ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103698
|
|
define pcodeop vfmsub231ps_avx512vl ;
|
|
:VFMSUB231PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xBA; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfmsub231ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103701
|
|
:VFMSUB132PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x9A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmsub132ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103704
|
|
:VFMSUB213PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xAA; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmsub213ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103707
|
|
:VFMSUB231PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfmsub231ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103710
|
|
define pcodeop vfmsub132ps_avx512f ;
|
|
:VFMSUB132PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x9A; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmsub132ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103713
|
|
define pcodeop vfmsub213ps_avx512f ;
|
|
:VFMSUB213PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xAA; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmsub213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103716
|
|
define pcodeop vfmsub231ps_avx512f ;
|
|
:VFMSUB231PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xBA; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfmsub231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-199 PAGE 2023 LINE 104042
|
|
define pcodeop vfmsub132sd_avx512f ;
|
|
:VFMSUB132SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x9B; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vfmsub132sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-199 PAGE 2023 LINE 104045
|
|
define pcodeop vfmsub213sd_avx512f ;
|
|
:VFMSUB213SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xAB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vfmsub213sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-199 PAGE 2023 LINE 104048
|
|
define pcodeop vfmsub231sd_avx512f ;
|
|
:VFMSUB231SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xBB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vfmsub231sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-202 PAGE 2026 LINE 104217
|
|
define pcodeop vfmsub132ss_avx512f ;
|
|
:VFMSUB132SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x9B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vfmsub132ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-202 PAGE 2026 LINE 104220
|
|
define pcodeop vfmsub213ss_avx512f ;
|
|
:VFMSUB213SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xAB; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vfmsub213ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-202 PAGE 2026 LINE 104223
|
|
define pcodeop vfmsub231ss_avx512f ;
|
|
:VFMSUB231SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xBB; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vfmsub231ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104401
|
|
define pcodeop vfnmadd132pd_avx512vl ;
|
|
:VFNMADD132PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x9C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfnmadd132pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104405
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define pcodeop vfnmadd213pd_avx512vl ;
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:VFNMADD213PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xAC; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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XmmResult = vfnmadd213pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
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XmmMask = XmmReg1;
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build XmmOpMask64;
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ZmmReg1 = zext(XmmResult);
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}
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# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104408
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define pcodeop vfnmadd231pd_avx512vl ;
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:VFNMADD231PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xBC; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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XmmResult = vfnmadd231pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
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XmmMask = XmmReg1;
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build XmmOpMask64;
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ZmmReg1 = zext(XmmResult);
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}
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# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104412
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:VFNMADD132PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x9C; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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YmmResult = vfnmadd132pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
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YmmMask = YmmReg1;
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build YmmOpMask64;
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ZmmReg1 = zext(YmmResult);
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}
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# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104416
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:VFNMADD213PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xAC; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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YmmResult = vfnmadd213pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
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YmmMask = YmmReg1;
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build YmmOpMask64;
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ZmmReg1 = zext(YmmResult);
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}
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# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104419
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:VFNMADD231PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xBC; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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YmmResult = vfnmadd231pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
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YmmMask = YmmReg1;
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build YmmOpMask64;
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ZmmReg1 = zext(YmmResult);
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}
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# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104423
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define pcodeop vfnmadd132pd_avx512f ;
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:VFNMADD132PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x9C; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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ZmmResult = vfnmadd132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
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ZmmMask = ZmmReg1;
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build ZmmOpMask64;
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ZmmReg1 = ZmmResult;
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}
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# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104426
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define pcodeop vfnmadd213pd_avx512f ;
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:VFNMADD213PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xAC; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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ZmmResult = vfnmadd213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
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ZmmMask = ZmmReg1;
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build ZmmOpMask64;
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ZmmReg1 = ZmmResult;
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}
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# VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104429
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define pcodeop vfnmadd231pd_avx512f ;
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:VFNMADD231PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xBC; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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ZmmResult = vfnmadd231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
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ZmmMask = ZmmReg1;
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build ZmmOpMask64;
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ZmmReg1 = ZmmResult;
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}
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# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104760
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define pcodeop vfnmadd132ps_avx512vl ;
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:VFNMADD132PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x9C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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XmmResult = vfnmadd132ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
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XmmMask = XmmReg1;
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build XmmOpMask32;
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ZmmReg1 = zext(XmmResult);
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}
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# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104763
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define pcodeop vfnmadd213ps_avx512vl ;
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:VFNMADD213PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xAC; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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XmmResult = vfnmadd213ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
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XmmMask = XmmReg1;
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build XmmOpMask32;
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ZmmReg1 = zext(XmmResult);
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}
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# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104766
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define pcodeop vfnmadd231ps_avx512vl ;
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:VFNMADD231PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xBC; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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XmmResult = vfnmadd231ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
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XmmMask = XmmReg1;
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build XmmOpMask32;
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ZmmReg1 = zext(XmmResult);
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}
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# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104769
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:VFNMADD132PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x9C; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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YmmResult = vfnmadd132ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
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YmmMask = YmmReg1;
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build YmmOpMask32;
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ZmmReg1 = zext(YmmResult);
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}
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# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104772
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:VFNMADD213PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xAC; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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YmmResult = vfnmadd213ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
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YmmMask = YmmReg1;
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build YmmOpMask32;
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ZmmReg1 = zext(YmmResult);
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}
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# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104775
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:VFNMADD231PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xBC; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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YmmResult = vfnmadd231ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
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YmmMask = YmmReg1;
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build YmmOpMask32;
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ZmmReg1 = zext(YmmResult);
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}
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# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104778
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:VFNMADD132PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x9C; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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ZmmResult = vfnmadd132ps_avx512vl( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
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ZmmMask = ZmmReg1;
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build ZmmOpMask32;
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ZmmReg1 = ZmmResult;
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}
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# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104781
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define pcodeop vfnmadd213ps_avx512f ;
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:VFNMADD213PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xAC; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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ZmmResult = vfnmadd213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
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ZmmMask = ZmmReg1;
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build ZmmOpMask32;
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ZmmReg1 = ZmmResult;
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}
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# VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104784
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define pcodeop vfnmadd231ps_avx512f ;
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:VFNMADD231PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xBC; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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ZmmResult = vfnmadd231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
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ZmmMask = ZmmReg1;
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build ZmmOpMask32;
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ZmmReg1 = ZmmResult;
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}
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# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-218 PAGE 2042 LINE 105098
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define pcodeop vfnmadd132sd_avx512f ;
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:VFNMADD132SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x9D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
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[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
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{
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XmmResult = vfnmadd132sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );
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XmmMask = XmmReg1;
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build XmmOpMask64;
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ZmmReg1 = zext(XmmResult);
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}
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# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-218 PAGE 2042 LINE 105101
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define pcodeop vfnmadd213sd_avx512f ;
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:VFNMADD213SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xAD; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
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[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
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{
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XmmResult = vfnmadd213sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );
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XmmMask = XmmReg1;
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build XmmOpMask64;
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ZmmReg1 = zext(XmmResult);
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}
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# VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-218 PAGE 2042 LINE 105104
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define pcodeop vfnmadd231sd_avx512f ;
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:VFNMADD231SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xBD; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
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[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
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{
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XmmResult = vfnmadd231sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );
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XmmMask = XmmReg1;
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build XmmOpMask64;
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ZmmReg1 = zext(XmmResult);
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}
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# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-221 PAGE 2045 LINE 105270
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define pcodeop vfnmadd132ss_avx512f ;
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:VFNMADD132SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x9D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
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[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
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{
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XmmResult = vfnmadd132ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );
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XmmMask = XmmReg1;
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build XmmOpMask32;
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ZmmReg1 = zext(XmmResult);
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}
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# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-221 PAGE 2045 LINE 105273
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define pcodeop vfnmadd213ss_avx512f ;
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:VFNMADD213SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xAD; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
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[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
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{
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XmmResult = vfnmadd213ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );
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XmmMask = XmmReg1;
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build XmmOpMask32;
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ZmmReg1 = zext(XmmResult);
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}
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# VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-221 PAGE 2045 LINE 105276
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define pcodeop vfnmadd231ss_avx512f ;
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:VFNMADD231SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xBD; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
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[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
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{
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XmmResult = vfnmadd231ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );
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XmmMask = XmmReg1;
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build XmmOpMask32;
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ZmmReg1 = zext(XmmResult);
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}
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# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105451
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define pcodeop vfnmsub132pd_avx512vl ;
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:VFNMSUB132PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x9E; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
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{
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XmmResult = vfnmsub132pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
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XmmMask = XmmReg1;
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build XmmOpMask64;
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ZmmReg1 = zext(XmmResult);
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}
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|
|
|
# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105455
|
|
define pcodeop vfnmsub213pd_avx512vl ;
|
|
:VFNMSUB213PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xAE; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfnmsub213pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105458
|
|
define pcodeop vfnmsub231pd_avx512vl ;
|
|
:VFNMSUB231PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xBE; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfnmsub231pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105462
|
|
:VFNMSUB132PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x9E; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfnmsub132pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105466
|
|
:VFNMSUB213PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xAE; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfnmsub213pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105469
|
|
:VFNMSUB231PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0xBE; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfnmsub231pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105473
|
|
define pcodeop vfnmsub132pd_avx512f ;
|
|
:VFNMSUB132PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x9E; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfnmsub132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105476
|
|
define pcodeop vfnmsub213pd_avx512f ;
|
|
:VFNMSUB213PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xAE; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfnmsub213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105479
|
|
define pcodeop vfnmsub231pd_avx512f ;
|
|
:VFNMSUB231PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xBE; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfnmsub231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105800
|
|
define pcodeop vfnmsub132ps_avx512vl ;
|
|
:VFNMSUB132PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x9E; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfnmsub132ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105803
|
|
define pcodeop vfnmsub213ps_avx512vl ;
|
|
:VFNMSUB213PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xAE; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfnmsub213ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105806
|
|
define pcodeop vfnmsub231ps_avx512vl ;
|
|
:VFNMSUB231PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xBE; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vfnmsub231ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105809
|
|
:VFNMSUB132PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x9E; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfnmsub132ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105812
|
|
:VFNMSUB213PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xAE; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfnmsub213ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105815
|
|
:VFNMSUB231PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0xBE; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vfnmsub231ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105818
|
|
define pcodeop vfnmsub132ps_avx512f ;
|
|
:VFNMSUB132PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x9E; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfnmsub132ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105821
|
|
define pcodeop vfnmsub213ps_avx512f ;
|
|
:VFNMSUB213PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xAE; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfnmsub213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105824
|
|
define pcodeop vfnmsub231ps_avx512f ;
|
|
:VFNMSUB231PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xBE; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vfnmsub231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-236 PAGE 2060 LINE 106135
|
|
define pcodeop vfnmsub132sd_avx512f ;
|
|
:VFNMSUB132SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x9F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vfnmsub132sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-236 PAGE 2060 LINE 106138
|
|
define pcodeop vfnmsub213sd_avx512f ;
|
|
:VFNMSUB213SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xAF; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vfnmsub213sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-236 PAGE 2060 LINE 106141
|
|
define pcodeop vfnmsub231sd_avx512f ;
|
|
:VFNMSUB231SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xBF; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vfnmsub231sd_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-239 PAGE 2063 LINE 106307
|
|
define pcodeop vfnmsub132ss_avx512f ;
|
|
:VFNMSUB132SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x9F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vfnmsub132ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-239 PAGE 2063 LINE 106310
|
|
define pcodeop vfnmsub213ss_avx512f ;
|
|
:VFNMSUB213SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xAF; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vfnmsub213ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-239 PAGE 2063 LINE 106313
|
|
define pcodeop vfnmsub231ss_avx512f ;
|
|
:VFNMSUB231SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xBF; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vfnmsub231ss_avx512f( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFPCLASSPD 5-242 PAGE 2066 LINE 106466
|
|
# There is an error in the manual where the immediate byte is not specified in the operand encoding, but it is present
|
|
define pcodeop vfpclasspd_avx512vl ;
|
|
:VFPCLASSPD KReg_reg AVXOpMask, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask; byte=0x66; KReg_reg ... & XmmReg2_m128_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
KReg_reg = vfpclasspd_avx512vl( XmmReg2_m128_m64bcst, AVXOpMask, imm8:1 );
|
|
}
|
|
|
|
# VFPCLASSPD 5-242 PAGE 2066 LINE 106470
|
|
:VFPCLASSPD KReg_reg AVXOpMask, YmmReg2_m256_m64bcst,imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask; byte=0x66; KReg_reg ... & YmmReg2_m256_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
KReg_reg = vfpclasspd_avx512vl( YmmReg2_m256_m64bcst, AVXOpMask, imm8:1 );
|
|
}
|
|
|
|
# VFPCLASSPD 5-242 PAGE 2066 LINE 106474
|
|
define pcodeop vfpclasspd_avx512dq ;
|
|
:VFPCLASSPD KReg_reg AVXOpMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask; byte=0x66; KReg_reg ... & ZmmReg2_m512_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
KReg_reg = vfpclasspd_avx512dq( ZmmReg2_m512_m64bcst, AVXOpMask, imm8:1 );
|
|
}
|
|
|
|
# VFPCLASSPS 5-245 PAGE 2069 LINE 106608
|
|
# There is an error in the manual where the immediate byte is not specified in the operand encoding, but it is present
|
|
define pcodeop vfpclassps_avx512vl ;
|
|
:VFPCLASSPS KReg_reg AVXOpMask, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask; byte=0x66; KReg_reg ... & XmmReg2_m128_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
KReg_reg = vfpclassps_avx512vl( XmmReg2_m128_m32bcst, AVXOpMask, imm8:1 );
|
|
}
|
|
|
|
# VFPCLASSPS 5-245 PAGE 2069 LINE 106612
|
|
:VFPCLASSPS KReg_reg AVXOpMask, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask; byte=0x66; KReg_reg ... & YmmReg2_m256_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
KReg_reg = vfpclassps_avx512vl( YmmReg2_m256_m32bcst, AVXOpMask,imm8:1 );
|
|
}
|
|
|
|
# VFPCLASSPS 5-245 PAGE 2069 LINE 106616
|
|
define pcodeop vfpclassps_avx512dq ;
|
|
:VFPCLASSPS KReg_reg AVXOpMask, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask; byte=0x66; KReg_reg ... & ZmmReg2_m512_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
KReg_reg = vfpclassps_avx512dq( ZmmReg2_m512_m32bcst, AVXOpMask, imm8:1 );
|
|
}
|
|
|
|
# VFPCLASSSD 5-247 PAGE 2071 LINE 106722
|
|
define pcodeop vfpclasssd_avx512dq ;
|
|
:VFPCLASSSD KReg_reg AVXOpMask, XmmReg2_m64, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask; byte=0x67; KReg_reg ... & XmmReg2_m64; imm8
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
KReg_reg = vfpclasssd_avx512dq( XmmReg2_m64, AVXOpMask, imm8:1 );
|
|
}
|
|
|
|
# VFPCLASSSS 5-249 PAGE 2073 LINE 106810
|
|
define pcodeop vfpclassss_avx512dq ;
|
|
:VFPCLASSSS KReg_reg AVXOpMask, XmmReg2_m32, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask; byte=0x67; KReg_reg ... & XmmReg2_m32; imm8
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
KReg_reg = vfpclassss_avx512dq( XmmReg2_m32, AVXOpMask, imm8:1 );
|
|
}
|
|
|
|
# VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107357
|
|
# WARNING: did not recognize qualifier /vsib for "VGATHERDPS xmm1 {k1}, vm32x"
|
|
define pcodeop vgatherdps_avx512vl ;
|
|
:VGATHERDPS XmmReg1^XmmOpMask32, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x92; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vgatherdps_avx512vl( m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107359
|
|
# WARNING: did not recognize qualifier /vsib for "VGATHERDPS ymm1 {k1}, vm32y"
|
|
:VGATHERDPS YmmReg1^YmmOpMask32, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x92; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmResult = vgatherdps_avx512vl( m32 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107361
|
|
# WARNING: did not recognize qualifier /vsib for "VGATHERDPS zmm1 {k1}, vm32z"
|
|
define pcodeop vgatherdps_avx512f ;
|
|
:VGATHERDPS ZmmReg1^ZmmOpMask32, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x92; (ZmmReg1 & ZmmOpMask32) ... & m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
ZmmResult = vgatherdps_avx512f( m32 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107363
|
|
# WARNING: did not recognize qualifier /vsib for "VGATHERDPD xmm1 {k1}, vm32x"
|
|
define pcodeop vgatherdpd_avx512vl ;
|
|
:VGATHERDPD XmmReg1^XmmOpMask64, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x92; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vgatherdpd_avx512vl( m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107366
|
|
# WARNING: did not recognize qualifier /vsib for "VGATHERDPD ymm1 {k1}, vm32x"
|
|
:VGATHERDPD YmmReg1^YmmOpMask64, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x92; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmResult = vgatherdpd_avx512vl( m32 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107369
|
|
# WARNING: did not recognize qualifier /vsib for "VGATHERDPD zmm1 {k1}, vm32y"
|
|
define pcodeop vgatherdpd_avx512f ;
|
|
:VGATHERDPD ZmmReg1^ZmmOpMask64, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x92; (ZmmReg1 & ZmmOpMask64) ... & m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
ZmmResult = vgatherdpd_avx512f( m32 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD 5-264 PAGE 2088 LINE 107497
|
|
# WARNING: did not recognize qualifier /vsib for "VGATHERPF0DPS vm32z {k1}"
|
|
define pcodeop vgatherpf0dps_avx512pf ;
|
|
:VGATHERPF0DPS m32^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xC6; reg_opcode=1 ... & m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vgatherpf0dps_avx512pf( m32, XmmOpMask );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD 5-264 PAGE 2088 LINE 107500
|
|
# WARNING: did not recognize qualifier /vsib for "VGATHERPF0QPS vm64z {k1}"
|
|
define pcodeop vgatherpf0qps_avx512pf ;
|
|
:VGATHERPF0QPS m64^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xC7; reg_opcode=1 ... & m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vgatherpf0qps_avx512pf( m64, XmmOpMask );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD 5-264 PAGE 2088 LINE 107503
|
|
# WARNING: did not recognize qualifier /vsib for "VGATHERPF0DPD vm32y {k1}"
|
|
define pcodeop vgatherpf0dpd_avx512pf ;
|
|
:VGATHERPF0DPD m32^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xC6; reg_opcode=1 ... & m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vgatherpf0dpd_avx512pf( m32, XmmOpMask );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD 5-264 PAGE 2088 LINE 107506
|
|
# WARNING: did not recognize qualifier /vsib for "VGATHERPF0QPD vm64z {k1}"
|
|
define pcodeop vgatherpf0qpd_avx512pf ;
|
|
:VGATHERPF0QPD m64^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xC7; reg_opcode=1 ... & m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vgatherpf0qpd_avx512pf( m64, XmmOpMask );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD 5-267 PAGE 2091 LINE 107620
|
|
# WARNING: did not recognize qualifier /vsib for "VGATHERPF1DPS vm32z {k1}"
|
|
define pcodeop vgatherpf1dps_avx512pf ;
|
|
:VGATHERPF1DPS m32^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xC6; reg_opcode=2 ... & m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vgatherpf1dps_avx512pf( m32 , XmmOpMask);
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD 5-267 PAGE 2091 LINE 107623
|
|
# WARNING: did not recognize qualifier /vsib for "VGATHERPF1QPS vm64z {k1}"
|
|
define pcodeop vgatherpf1qps_avx512pf ;
|
|
:VGATHERPF1QPS m64^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xC7; reg_opcode=2 ... & m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vgatherpf1qps_avx512pf( m64, XmmOpMask );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD 5-267 PAGE 2091 LINE 107626
|
|
# WARNING: did not recognize qualifier /vsib for "VGATHERPF1DPD vm32y {k1}"
|
|
define pcodeop vgatherpf1dpd_avx512pf ;
|
|
:VGATHERPF1DPD m32^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xC6; reg_opcode=2 ... & m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vgatherpf1dpd_avx512pf( m32, XmmOpMask );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD 5-267 PAGE 2091 LINE 107629
|
|
# WARNING: did not recognize qualifier /vsib for "VGATHERPF1QPD vm64z {k1}"
|
|
define pcodeop vgatherpf1qpd_avx512pf ;
|
|
:VGATHERPF1QPD m64^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xC7; reg_opcode=2 ... & m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vgatherpf1qpd_avx512pf( m64, XmmOpMask );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107742
|
|
# WARNING: did not recognize qualifier /vsib for "VGATHERQPS xmm1 {k1}, vm64x"
|
|
define pcodeop vgatherqps_avx512vl ;
|
|
:VGATHERQPS XmmReg1^XmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x93; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vgatherqps_avx512vl( m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107745
|
|
# WARNING: did not recognize qualifier /vsib for "VGATHERQPS xmm1 {k1}, vm64y"
|
|
:VGATHERQPS XmmReg1^XmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x93; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vgatherqps_avx512vl( m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107748
|
|
# WARNING: did not recognize qualifier /vsib for "VGATHERQPS ymm1 {k1}, vm64z"
|
|
define pcodeop vgatherqps_avx512f ;
|
|
:VGATHERQPS YmmReg1^YmmOpMask64, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x93; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmResult = vgatherqps_avx512f( m64 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107751
|
|
# WARNING: did not recognize qualifier /vsib for "VGATHERQPD xmm1 {k1}, vm64x"
|
|
define pcodeop vgatherqpd_avx512vl ;
|
|
:VGATHERQPD XmmReg1^XmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x93; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vgatherqpd_avx512vl( m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107753
|
|
# WARNING: did not recognize qualifier /vsib for "VGATHERQPD ymm1 {k1}, vm64y"
|
|
:VGATHERQPD YmmReg1^YmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x93; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmResult = vgatherqpd_avx512vl( m64 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107755
|
|
# WARNING: did not recognize qualifier /vsib for "VGATHERQPD zmm1 {k1}, vm64z"
|
|
define pcodeop vgatherqpd_avx512f ;
|
|
:VGATHERQPD ZmmReg1^ZmmOpMask64, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x93; (ZmmReg1 & ZmmOpMask64) ... & m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
ZmmResult = vgatherqpd_avx512f( m64 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108099
|
|
# WARNING: did not recognize qualifier /vsib for "VPGATHERDD xmm1 {k1}, vm32x"
|
|
define pcodeop vpgatherdd_avx512vl ;
|
|
:VPGATHERDD XmmReg1^XmmOpMask32, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x90; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vpgatherdd_avx512vl( m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108101
|
|
# WARNING: did not recognize qualifier /vsib for "VPGATHERDD ymm1 {k1}, vm32y"
|
|
:VPGATHERDD YmmReg1^YmmOpMask32, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x90; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmResult = vpgatherdd_avx512vl( m32 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108103
|
|
# WARNING: did not recognize qualifier /vsib for "VPGATHERDD zmm1 {k1}, vm32z"
|
|
define pcodeop vpgatherdd_avx512f ;
|
|
:VPGATHERDD ZmmReg1^ZmmOpMask32, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x90; (ZmmReg1 & ZmmOpMask32) ... & m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
ZmmResult = vpgatherdd_avx512f( m32 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108105
|
|
# WARNING: did not recognize qualifier /vsib for "VPGATHERDQ xmm1 {k1}, vm32x"
|
|
define pcodeop vpgatherdq_avx512vl ;
|
|
:VPGATHERDQ XmmReg1^XmmOpMask64, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x90; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vpgatherdq_avx512vl( m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108107
|
|
# WARNING: did not recognize qualifier /vsib for "VPGATHERDQ ymm1 {k1}, vm32x"
|
|
:VPGATHERDQ YmmReg1^YmmOpMask64, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x90; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmResult = vpgatherdq_avx512vl( m32 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108109
|
|
# WARNING: did not recognize qualifier /vsib for "VPGATHERDQ zmm1 {k1}, vm32y"
|
|
define pcodeop vpgatherdq_avx512f ;
|
|
:VPGATHERDQ ZmmReg1^ZmmOpMask64, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x90; (ZmmReg1 & ZmmOpMask64) ... & m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
ZmmResult = vpgatherdq_avx512f( m32 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108457
|
|
# WARNING: did not recognize qualifier /vsib for "VPGATHERQD xmm1 {k1}, vm64x"
|
|
define pcodeop vpgatherqd_avx512vl ;
|
|
:VPGATHERQD XmmReg1^XmmOpMask32, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x91; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vpgatherqd_avx512vl( m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108459
|
|
# WARNING: did not recognize qualifier /vsib for "VPGATHERQD xmm1 {k1}, vm64y"
|
|
:VPGATHERQD XmmReg1^XmmOpMask32, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x91; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vpgatherqd_avx512vl( m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108461
|
|
# WARNING: did not recognize qualifier /vsib for "VPGATHERQD ymm1 {k1}, vm64z"
|
|
define pcodeop vpgatherqd_avx512f ;
|
|
:VPGATHERQD YmmReg1^YmmOpMask32, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x91; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmResult = vpgatherqd_avx512f( m64 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108463
|
|
# WARNING: did not recognize qualifier /vsib for "VPGATHERQQ xmm1 {k1}, vm64x"
|
|
define pcodeop vpgatherqq_avx512vl ;
|
|
:VPGATHERQQ XmmReg1^XmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x91; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vpgatherqq_avx512vl( m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108465
|
|
# WARNING: did not recognize qualifier /vsib for "VPGATHERQQ ymm1 {k1}, vm64y"
|
|
:VPGATHERQQ YmmReg1^YmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x91; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmResult = vpgatherqq_avx512vl( m64 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108467
|
|
# WARNING: did not recognize qualifier /vsib for "VPGATHERQQ zmm1 {k1}, vm64z"
|
|
define pcodeop vpgatherqq_avx512f ;
|
|
:VPGATHERQQ ZmmReg1^ZmmOpMask64, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x91; (ZmmReg1 & ZmmOpMask64) ... & m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
ZmmResult = vpgatherqq_avx512f( m64 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VGETEXPPD 5-288 PAGE 2112 LINE 108594
|
|
define pcodeop vgetexppd_avx512vl ;
|
|
:VGETEXPPD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x42; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vgetexppd_avx512vl( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VGETEXPPD 5-288 PAGE 2112 LINE 108598
|
|
:VGETEXPPD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x42; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vgetexppd_avx512vl( YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VGETEXPPD 5-288 PAGE 2112 LINE 108602
|
|
define pcodeop vgetexppd_avx512f ;
|
|
:VGETEXPPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x42; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vgetexppd_avx512f( ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VGETEXPPS 5-291 PAGE 2115 LINE 108760
|
|
define pcodeop vgetexpps_avx512vl ;
|
|
:VGETEXPPS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x42; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vgetexpps_avx512vl( XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VGETEXPPS 5-291 PAGE 2115 LINE 108764
|
|
:VGETEXPPS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x42; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vgetexpps_avx512vl( YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VGETEXPPS 5-291 PAGE 2115 LINE 108768
|
|
define pcodeop vgetexpps_avx512f ;
|
|
:VGETEXPPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x42; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vgetexpps_avx512f( ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VGETEXPSD 5-295 PAGE 2119 LINE 108959
|
|
define pcodeop vgetexpsd_avx512f ;
|
|
:VGETEXPSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x43; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vgetexpsd_avx512f( evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VGETEXPSS 5-297 PAGE 2121 LINE 109037
|
|
define pcodeop vgetexpss_avx512f ;
|
|
:VGETEXPSS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x43; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vgetexpss_avx512f( evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VGETMANTPD 5-299 PAGE 2123 LINE 109120
|
|
define pcodeop vgetmantpd_avx512vl ;
|
|
:VGETMANTPD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x26; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
XmmResult = vgetmantpd_avx512vl( XmmReg2_m128_m64bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VGETMANTPD 5-299 PAGE 2123 LINE 109125
|
|
:VGETMANTPD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x26; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
YmmResult = vgetmantpd_avx512vl( YmmReg2_m256_m64bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VGETMANTPD 5-299 PAGE 2123 LINE 109130
|
|
define pcodeop vgetmantpd_avx512f ;
|
|
:VGETMANTPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x26; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
ZmmResult = vgetmantpd_avx512f( ZmmReg2_m512_m64bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VGETMANTPS 5-303 PAGE 2127 LINE 109339
|
|
define pcodeop vgetmantps_avx512vl ;
|
|
:VGETMANTPS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x26; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
XmmResult = vgetmantps_avx512vl( XmmReg2_m128_m32bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VGETMANTPS 5-303 PAGE 2127 LINE 109344
|
|
:VGETMANTPS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x26; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
YmmResult = vgetmantps_avx512vl( YmmReg2_m256_m32bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VGETMANTPS 5-303 PAGE 2127 LINE 109349
|
|
define pcodeop vgetmantps_avx512f ;
|
|
:VGETMANTPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x26; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI)
|
|
{
|
|
ZmmResult = vgetmantps_avx512f( ZmmReg2_m512_m32bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VGETMANTSD 5-306 PAGE 2130 LINE 109519
|
|
define pcodeop vgetmantsd_avx512f ;
|
|
:VGETMANTSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_XmmReg; byte=0x27; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vgetmantsd_avx512f( evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VGETMANTSS 5-308 PAGE 2132 LINE 109610
|
|
define pcodeop vgetmantss_avx512f ;
|
|
:VGETMANTSS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x27; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vgetmantss_avx512f( evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109706
|
|
define pcodeop vinsertf32x4_avx512vl ;
|
|
:VINSERTF32X4 YmmReg1^YmmOpMask32, evexV5_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_YmmReg; byte=0x18; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
YmmResult = vinsertf32x4_avx512vl( evexV5_YmmReg, XmmReg2_m128, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109709
|
|
define pcodeop vinsertf32x4_avx512f ;
|
|
:VINSERTF32X4 ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x18; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
ZmmResult = vinsertf32x4_avx512f( evexV5_ZmmReg, XmmReg2_m128, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109712
|
|
define pcodeop vinsertf64x2_avx512vl ;
|
|
:VINSERTF64X2 YmmReg1^YmmOpMask64, evexV5_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_YmmReg; byte=0x18; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
YmmResult = vinsertf64x2_avx512vl( evexV5_YmmReg, XmmReg2_m128, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109715
|
|
define pcodeop vinsertf64x2_avx512dq ;
|
|
:VINSERTF64X2 ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x18; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
ZmmResult = vinsertf64x2_avx512dq( evexV5_ZmmReg, XmmReg2_m128, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109718
|
|
define pcodeop vinsertf32x8_avx512dq ;
|
|
:VINSERTF32X8 ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x1A; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
ZmmResult = vinsertf32x8_avx512dq( evexV5_ZmmReg, YmmReg2_m256, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109721
|
|
define pcodeop vinsertf64x4_avx512f ;
|
|
:VINSERTF64X4 ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x1A; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
ZmmResult = vinsertf64x4_avx512f( evexV5_ZmmReg, YmmReg2_m256, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109930
|
|
define pcodeop vinserti32x4_avx512vl ;
|
|
:VINSERTI32X4 YmmReg1^YmmOpMask32, evexV5_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_YmmReg; byte=0x38; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
YmmResult = vinserti32x4_avx512vl( evexV5_YmmReg, XmmReg2_m128, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109933
|
|
define pcodeop vinserti32x4_avx512f ;
|
|
:VINSERTI32X4 ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x38; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
ZmmResult = vinserti32x4_avx512f( evexV5_ZmmReg, XmmReg2_m128, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109936
|
|
define pcodeop vinserti64x2_avx512vl ;
|
|
:VINSERTI64X2 YmmReg1^YmmOpMask64, evexV5_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_YmmReg; byte=0x38; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
YmmResult = vinserti64x2_avx512vl( evexV5_YmmReg, XmmReg2_m128, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109939
|
|
define pcodeop vinserti64x2_avx512dq ;
|
|
:VINSERTI64X2 ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x38; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
ZmmResult = vinserti64x2_avx512dq( evexV5_ZmmReg, XmmReg2_m128, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109942
|
|
define pcodeop vinserti32x8_avx512dq ;
|
|
:VINSERTI32X8 ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x3A; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
ZmmResult = vinserti32x8_avx512dq( evexV5_ZmmReg, YmmReg2_m256, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109945
|
|
define pcodeop vinserti64x4_avx512f ;
|
|
:VINSERTI64X4 ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x3A; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256; imm8
|
|
[ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8)
|
|
{
|
|
ZmmResult = vinserti64x4_avx512f( evexV5_ZmmReg, YmmReg2_m256, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110393
|
|
define pcodeop vpblendmb_avx512vl ;
|
|
:VPBLENDMB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x66; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpblendmb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110396
|
|
:VPBLENDMB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x66; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpblendmb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110399
|
|
define pcodeop vpblendmb_avx512bw ;
|
|
:VPBLENDMB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x66; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpblendmb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110402
|
|
define pcodeop vpblendmw_avx512vl ;
|
|
:VPBLENDMW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x66; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpblendmw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110405
|
|
:VPBLENDMW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x66; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpblendmw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110408
|
|
define pcodeop vpblendmw_avx512bw ;
|
|
:VPBLENDMW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x66; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpblendmw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110495
|
|
define pcodeop vpblendmd_avx512vl ;
|
|
:VPBLENDMD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x64; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpblendmd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110498
|
|
:VPBLENDMD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x64; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpblendmd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110501
|
|
define pcodeop vpblendmd_avx512f ;
|
|
:VPBLENDMD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x64; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpblendmd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110504
|
|
define pcodeop vpblendmq_avx512vl ;
|
|
:VPBLENDMQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x64; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpblendmq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110507
|
|
:VPBLENDMQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x64; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpblendmq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110510
|
|
define pcodeop vpblendmq_avx512f ;
|
|
:VPBLENDMQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x64; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpblendmq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110617
|
|
# WARNING: did not recognize operand "reg" (encoding ModRM:r/m (r)) for "VPBROADCASTB xmm1 {k1}{z}, reg"
|
|
#TODO: fix
|
|
define pcodeop vpbroadcastb_avx512vl ;
|
|
:VPBROADCASTB XmmReg1^XmmOpMask8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask8)
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
local tmp:16 = vpbroadcastb_avx512vl( );
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110619
|
|
# WARNING: did not recognize operand "reg" (encoding ModRM:r/m (r)) for "VPBROADCASTB ymm1 {k1}{z}, reg"
|
|
:VPBROADCASTB YmmReg1^YmmOpMask8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask8)
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmResult = vpbroadcastb_avx512vl( );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110621
|
|
# WARNING: did not recognize operand "reg" (encoding ModRM:r/m (r)) for "VPBROADCASTB zmm1 {k1}{z}, reg"
|
|
define pcodeop vpbroadcastb_avx512bw ;
|
|
:VPBROADCASTB ZmmReg1^ZmmOpMask8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7A; ZmmReg1 & ZmmOpMask8
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
ZmmResult = vpbroadcastb_avx512bw( );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110623
|
|
# WARNING: did not recognize operand "reg" (encoding ModRM:r/m (r)) for "VPBROADCASTW xmm1 {k1}{z}, reg"
|
|
define pcodeop vpbroadcastw_avx512vl ;
|
|
:VPBROADCASTW XmmReg1^XmmOpMask16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7B; (XmmReg1 & ZmmReg1 & XmmOpMask16)
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vpbroadcastw_avx512vl( );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110625
|
|
# WARNING: did not recognize operand "reg" (encoding ModRM:r/m (r)) for "VPBROADCASTW ymm1 {k1}{z}, reg"
|
|
:VPBROADCASTW YmmReg1^YmmOpMask16 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7B; (YmmReg1 & ZmmReg1 & YmmOpMask16)
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmResult = vpbroadcastw_avx512vl( );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110627
|
|
# WARNING: did not recognize operand "reg" (encoding ModRM:r/m (r)) for "VPBROADCASTW zmm1 {k1}{z}, reg"
|
|
define pcodeop vpbroadcastw_avx512bw ;
|
|
:VPBROADCASTW ZmmReg1^ZmmOpMask16 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7B; ZmmReg1 & ZmmOpMask16
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
ZmmResult = vpbroadcastw_avx512bw( );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110629
|
|
# WARNING: did not recognize operand "r32" (encoding ModRM:r/m (r)) for "VPBROADCASTD xmm1 {k1}{z}, r32"
|
|
define pcodeop vpbroadcastd_avx512vl ;
|
|
:VPBROADCASTD XmmReg1^XmmOpMask32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7C; (XmmReg1 & ZmmReg1 & XmmOpMask32)
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vpbroadcastd_avx512vl( );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110631
|
|
# WARNING: did not recognize operand "r32" (encoding ModRM:r/m (r)) for "VPBROADCASTD ymm1 {k1}{z}, r32"
|
|
:VPBROADCASTD YmmReg1^YmmOpMask32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7C; (YmmReg1 & ZmmReg1 & YmmOpMask32)
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmResult = vpbroadcastd_avx512vl( );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110633
|
|
# WARNING: did not recognize operand "r32" (encoding ModRM:r/m (r)) for "VPBROADCASTD zmm1 {k1}{z}, r32"
|
|
define pcodeop vpbroadcastd_avx512f ;
|
|
:VPBROADCASTD ZmmReg1^ZmmOpMask32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7C; ZmmReg1 & ZmmOpMask32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
ZmmResult = vpbroadcastd_avx512f( );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110635
|
|
# WARNING: did not recognize operand "r64" (encoding ModRM:r/m (r)) for "VPBROADCASTQ xmm1 {k1}{z}, r64"
|
|
define pcodeop vpbroadcastq_avx512vl ;
|
|
@ifdef IA64
|
|
:VPBROADCASTQ XmmReg1^XmmOpMask64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1); byte=0x7C; (XmmReg1 & ZmmReg1 & XmmOpMask64)
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vpbroadcastq_avx512vl( );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
@endif
|
|
|
|
# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110637
|
|
# WARNING: did not recognize operand "r64" (encoding ModRM:r/m (r)) for "VPBROADCASTQ ymm1 {k1}{z}, r64"
|
|
@ifdef IA64
|
|
:VPBROADCASTQ YmmReg1^YmmOpMask64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1); byte=0x7C; (YmmReg1 & ZmmReg1 & YmmOpMask64)
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmResult = vpbroadcastq_avx512vl( );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
@endif
|
|
|
|
# VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110639
|
|
# WARNING: did not recognize operand "r64" (encoding ModRM:r/m (r)) for "VPBROADCASTQ zmm1 {k1}{z}, r64"
|
|
define pcodeop vpbroadcastq_avx512f ;
|
|
@ifdef IA64
|
|
:VPBROADCASTQ ZmmReg1^ZmmOpMask64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1); byte=0x7C; ZmmReg1 & ZmmOpMask64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
ZmmResult = vpbroadcastq_avx512f( );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
@endif
|
|
|
|
# VPBROADCAST 5-331 PAGE 2155 LINE 110780
|
|
:VPBROADCASTB XmmReg1^XmmOpMask8, XmmReg2_m8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m8
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
XmmResult = vpbroadcastb_avx512vl( XmmReg2_m8 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPBROADCAST 5-331 PAGE 2155 LINE 110782
|
|
:VPBROADCASTB YmmReg1^YmmOpMask8, XmmReg2_m8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x78; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & XmmReg2_m8
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
YmmResult = vpbroadcastb_avx512vl( XmmReg2_m8 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPBROADCAST 5-331 PAGE 2155 LINE 110784
|
|
:VPBROADCASTB ZmmReg1^ZmmOpMask8, XmmReg2_m8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x78; (ZmmReg1 & ZmmOpMask8) ... & XmmReg2_m8
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
ZmmResult = vpbroadcastb_avx512bw( XmmReg2_m8 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPBROADCAST 5-331 PAGE 2155 LINE 110791
|
|
:VPBROADCASTW XmmReg1^XmmOpMask16, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m16
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
XmmResult = vpbroadcastw_avx512vl( XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPBROADCAST 5-331 PAGE 2155 LINE 110794
|
|
:VPBROADCASTW YmmReg1^YmmOpMask16, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x79; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m16
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
YmmResult = vpbroadcastw_avx512vl( XmmReg2_m16 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPBROADCAST 5-331 PAGE 2155 LINE 110797
|
|
:VPBROADCASTW ZmmReg1^ZmmOpMask16, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x79; (ZmmReg1 & ZmmOpMask16) ... & XmmReg2_m16
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
ZmmResult = vpbroadcastw_avx512bw( XmmReg2_m16 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPBROADCAST 5-331 PAGE 2155 LINE 110804
|
|
:VPBROADCASTD XmmReg1^XmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x58; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
XmmResult = vpbroadcastd_avx512vl( XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPBROADCAST 5-331 PAGE 2155 LINE 110807
|
|
:VPBROADCASTD YmmReg1^YmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x58; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
YmmResult = vpbroadcastd_avx512vl( XmmReg2_m32 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPBROADCAST 5-331 PAGE 2155 LINE 110810
|
|
:VPBROADCASTD ZmmReg1^ZmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x58; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
ZmmResult = vpbroadcastd_avx512f( XmmReg2_m32 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPBROADCAST 5-331 PAGE 2155 LINE 110817
|
|
:VPBROADCASTQ XmmReg1^XmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
XmmResult = vpbroadcastq_avx512vl( XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPBROADCAST 5-331 PAGE 2155 LINE 110819
|
|
:VPBROADCASTQ YmmReg1^YmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x59; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
YmmResult = vpbroadcastq_avx512vl( XmmReg2_m64 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPBROADCAST 5-331 PAGE 2155 LINE 110821
|
|
:VPBROADCASTQ ZmmReg1^ZmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x59; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
ZmmResult = vpbroadcastq_avx512f( XmmReg2_m64 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPBROADCAST 5-331 PAGE 2155 LINE 110823
|
|
define pcodeop vbroadcasti32x2_avx512vl ;
|
|
:VBROADCASTI32x2 XmmReg1^XmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
XmmResult = vbroadcasti32x2_avx512vl( XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPBROADCAST 5-332 PAGE 2156 LINE 110837
|
|
:VBROADCASTI32x2 YmmReg1^YmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x59; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
YmmResult = vbroadcasti32x2_avx512vl( XmmReg2_m64 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPBROADCAST 5-332 PAGE 2156 LINE 110840
|
|
define pcodeop vbroadcasti32x2_avx512dq ;
|
|
:VBROADCASTI32x2 ZmmReg1^ZmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x59; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
ZmmResult = vbroadcasti32x2_avx512dq( XmmReg2_m64 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPBROADCAST 5-332 PAGE 2156 LINE 110845
|
|
define pcodeop vbroadcasti32x4_avx512vl ;
|
|
:VBROADCASTI32X4 YmmReg1^YmmOpMask32, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x5A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & m128
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
YmmResult = vbroadcasti32x4_avx512vl( m128 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPBROADCAST 5-332 PAGE 2156 LINE 110848
|
|
define pcodeop vbroadcasti32x4_avx512f ;
|
|
:VBROADCASTI32X4 ZmmReg1^ZmmOpMask32, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x5A; (ZmmReg1 & ZmmOpMask32) ... & m128
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
ZmmResult = vbroadcasti32x4_avx512f( m128 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPBROADCAST 5-332 PAGE 2156 LINE 110851
|
|
define pcodeop vbroadcasti64x2_avx512vl ;
|
|
:VBROADCASTI64X2 YmmReg1^YmmOpMask64, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x5A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m128
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
YmmResult = vbroadcasti64x2_avx512vl( m128 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPBROADCAST 5-332 PAGE 2156 LINE 110854
|
|
define pcodeop vbroadcasti64x2_avx512dq ;
|
|
:VBROADCASTI64X2 ZmmReg1^ZmmOpMask64, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x5A; (ZmmReg1 & ZmmOpMask64) ... & m128
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
ZmmResult = vbroadcasti64x2_avx512dq( m128 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPBROADCAST 5-332 PAGE 2156 LINE 110857
|
|
define pcodeop vbroadcasti32x8_avx512dq ;
|
|
:VBROADCASTI32X8 ZmmReg1^ZmmOpMask32, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x5B; (ZmmReg1 & ZmmOpMask32) ... & m256
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
ZmmResult = vbroadcasti32x8_avx512dq( m256 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPBROADCAST 5-332 PAGE 2156 LINE 110860
|
|
define pcodeop vbroadcasti64x4_avx512f ;
|
|
:VBROADCASTI64X4 ZmmReg1^ZmmOpMask64, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x5B; (ZmmReg1 & ZmmOpMask64) ... & m256
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8)
|
|
{
|
|
ZmmResult = vbroadcasti64x4_avx512f( m256 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPCMPB/VPCMPUB 5-339 PAGE 2163 LINE 111259
|
|
VPCMPB_mon: "VPCMPEQB" is imm8=0x0 { }
|
|
VPCMPB_mon: "VPCMPLTB" is imm8=0x1 { }
|
|
VPCMPB_mon: "VPCMPLEB" is imm8=0x2 { }
|
|
VPCMPB_mon: "VPCMPEQB" is imm8=0x4 { }
|
|
VPCMPB_mon: "VPCMPNLTB" is imm8=0x5 { }
|
|
VPCMPB_mon: "VPCMPNLEB" is imm8=0x6 { }
|
|
VPCMPB_op: "" is imm8=0 { local tmp:1 = 0; export *[const]:1 tmp; }
|
|
VPCMPB_op: "" is imm8=1 { local tmp:1 = 1; export *[const]:1 tmp; }
|
|
VPCMPB_op: "" is imm8=2 { local tmp:1 = 2; export *[const]:1 tmp; }
|
|
VPCMPB_op: "" is imm8=4 { local tmp:1 = 4; export *[const]:1 tmp; }
|
|
VPCMPB_op: "" is imm8=5 { local tmp:1 = 5; export *[const]:1 tmp; }
|
|
VPCMPB_op: "" is imm8=6 { local tmp:1 = 6; export *[const]:1 tmp; }
|
|
|
|
VPCMPB_mon: "VPCMPB" is imm8 { }
|
|
VPCMPB_op: ", "^imm8 is imm8 { export *[const]:1 imm8; }
|
|
|
|
define pcodeop vpcmpb_avx512vl ;
|
|
:^VPCMPB_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128^VPCMPB_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0x3F; KReg_reg ... & XmmReg2_m128; VPCMPB_mon & VPCMPB_op
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpb_avx512vl( evexV5_XmmReg, XmmReg2_m128, VPCMPB_op );
|
|
KReg_reg = zext(AVXOpMask[0,16]) & tmp;
|
|
}
|
|
|
|
# VPCMPB/VPCMPUB 5-339 PAGE 2163 LINE 111263
|
|
:^VPCMPB_mon KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256^VPCMPB_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_YmmReg; byte=0x3F; KReg_reg ... & YmmReg2_m256; VPCMPB_mon & VPCMPB_op
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpb_avx512vl( evexV5_YmmReg, YmmReg2_m256, VPCMPB_op );
|
|
KReg_reg = zext(AVXOpMask[0,32]) & tmp;
|
|
}
|
|
|
|
# VPCMPB/VPCMPUB 5-339 PAGE 2163 LINE 111267
|
|
define pcodeop vpcmpb_avx512bw ;
|
|
:^VPCMPB_mon KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512^VPCMPB_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_ZmmReg; byte=0x3F; KReg_reg ... & ZmmReg2_m512; VPCMPB_mon & VPCMPB_op
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512, VPCMPB_op );
|
|
KReg_reg = zext(AVXOpMask[0,64]) & tmp;
|
|
}
|
|
|
|
|
|
|
|
# VPCMPB/VPCMPUB 5-339 PAGE 2163 LINE 111271
|
|
VPCMPUB_mon: "VPCMPEQUB" is imm8=0x0 { }
|
|
VPCMPUB_mon: "VPCMPLTUB" is imm8=0x1 { }
|
|
VPCMPUB_mon: "VPCMPLEUB" is imm8=0x2 { }
|
|
VPCMPUB_mon: "VPCMPEQUB" is imm8=0x4 { }
|
|
VPCMPUB_mon: "VPCMPNLTUB" is imm8=0x5 { }
|
|
VPCMPUB_mon: "VPCMPNLEUB" is imm8=0x6 { }
|
|
VPCMPUB_op: "" is imm8=0 { local tmp:1 = 0; export *[const]:1 tmp; }
|
|
VPCMPUB_op: "" is imm8=1 { local tmp:1 = 1; export *[const]:1 tmp; }
|
|
VPCMPUB_op: "" is imm8=2 { local tmp:1 = 2; export *[const]:1 tmp; }
|
|
VPCMPUB_op: "" is imm8=4 { local tmp:1 = 4; export *[const]:1 tmp; }
|
|
VPCMPUB_op: "" is imm8=5 { local tmp:1 = 5; export *[const]:1 tmp; }
|
|
VPCMPUB_op: "" is imm8=6 { local tmp:1 = 6; export *[const]:1 tmp; }
|
|
|
|
VPCMPUB_mon: "VPCMPUB" is imm8 { }
|
|
VPCMPUB_op: ", "^imm8 is imm8 { export *[const]:1 imm8; }
|
|
|
|
define pcodeop vpcmpub_avx512vl ;
|
|
:^VPCMPUB_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128^VPCMPUB_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0x3E; KReg_reg ... & XmmReg2_m128; VPCMPUB_mon & VPCMPUB_op
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpub_avx512vl( evexV5_XmmReg, XmmReg2_m128, VPCMPUB_op );
|
|
KReg_reg = zext(AVXOpMask[0,16]) & tmp;
|
|
}
|
|
|
|
# VPCMPB/VPCMPUB 5-339 PAGE 2163 LINE 111275
|
|
:^VPCMPUB_mon KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256^VPCMPUB_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_YmmReg; byte=0x3E; KReg_reg ... & YmmReg2_m256; VPCMPUB_mon & VPCMPUB_op
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpub_avx512vl( evexV5_YmmReg, YmmReg2_m256, VPCMPUB_op );
|
|
KReg_reg = zext(AVXOpMask[0,32]) & tmp;
|
|
}
|
|
|
|
# VPCMPB/VPCMPUB 5-339 PAGE 2163 LINE 111279
|
|
define pcodeop vpcmpub_avx512bw ;
|
|
:^VPCMPUB_mon KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512^VPCMPUB_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_ZmmReg; byte=0x3E; KReg_reg ... & ZmmReg2_m512; VPCMPUB_mon & VPCMPUB_op
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpub_avx512bw( evexV5_ZmmReg, ZmmReg2_m512, VPCMPUB_op );
|
|
KReg_reg = zext(AVXOpMask[0,64]) & tmp;
|
|
|
|
}
|
|
|
|
|
|
# VPCMPD/VPCMPUD 5-342 PAGE 2166 LINE 111422
|
|
VPCMPD_mon: "VPCMPEQD" is imm8=0x0 { }
|
|
VPCMPD_mon: "VPCMPLTD" is imm8=0x1 { }
|
|
VPCMPD_mon: "VPCMPLED" is imm8=0x2 { }
|
|
VPCMPD_mon: "VPCMPEQD" is imm8=0x4 { }
|
|
VPCMPD_mon: "VPCMPNLTD" is imm8=0x5 { }
|
|
VPCMPD_mon: "VPCMPNLED" is imm8=0x6 { }
|
|
VPCMPD_op: "" is imm8=0 { local tmp:1 = 0; export *[const]:1 tmp; }
|
|
VPCMPD_op: "" is imm8=1 { local tmp:1 = 1; export *[const]:1 tmp; }
|
|
VPCMPD_op: "" is imm8=2 { local tmp:1 = 2; export *[const]:1 tmp; }
|
|
VPCMPD_op: "" is imm8=4 { local tmp:1 = 4; export *[const]:1 tmp; }
|
|
VPCMPD_op: "" is imm8=5 { local tmp:1 = 5; export *[const]:1 tmp; }
|
|
VPCMPD_op: "" is imm8=6 { local tmp:1 = 6; export *[const]:1 tmp; }
|
|
|
|
VPCMPD_mon: "VPCMPD" is imm8 { }
|
|
VPCMPD_op: ", "^imm8 is imm8 { export *[const]:1 imm8; }
|
|
|
|
define pcodeop vpcmpd_avx512vl ;
|
|
:^VPCMPD_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m32bcst^VPCMPD_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0x1F; KReg_reg ... & XmmReg2_m128_m32bcst; VPCMPD_mon & VPCMPD_op
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst, VPCMPD_op );
|
|
KReg_reg = zext(AVXOpMask[0,4]) & tmp;
|
|
}
|
|
|
|
# VPCMPD/VPCMPUD 5-342 PAGE 2166 LINE 111426
|
|
:^VPCMPD_mon KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m32bcst^VPCMPD_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_YmmReg; byte=0x1F; KReg_reg ... & YmmReg2_m256_m32bcst; VPCMPD_mon & VPCMPD_op
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst, VPCMPD_op );
|
|
KReg_reg = zext(AVXOpMask[0,8]) & tmp;
|
|
}
|
|
|
|
# VPCMPD/VPCMPUD 5-342 PAGE 2166 LINE 111430
|
|
define pcodeop vpcmpd_avx512f ;
|
|
:^VPCMPD_mon KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst^VPCMPD_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_ZmmReg; byte=0x1F; KReg_reg ... & ZmmReg2_m512_m32bcst; VPCMPD_mon & VPCMPD_op
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, VPCMPD_op );
|
|
KReg_reg = zext(AVXOpMask[0,16]) & tmp;
|
|
}
|
|
|
|
|
|
# VPCMPD/VPCMPUD 5-342 PAGE 2166 LINE 111434
|
|
VPCMPUD_mon: "VPCMPEQUD" is imm8=0x0 { }
|
|
VPCMPUD_mon: "VPCMPLTUD" is imm8=0x1 { }
|
|
VPCMPUD_mon: "VPCMPLEUD" is imm8=0x2 { }
|
|
VPCMPUD_mon: "VPCMPEQUD" is imm8=0x4 { }
|
|
VPCMPUD_mon: "VPCMPNLTUD" is imm8=0x5 { }
|
|
VPCMPUD_mon: "VPCMPNLEUD" is imm8=0x6 { }
|
|
VPCMPUD_op: "" is imm8=0 { local tmp:1 = 0; export *[const]:1 tmp; }
|
|
VPCMPUD_op: "" is imm8=1 { local tmp:1 = 1; export *[const]:1 tmp; }
|
|
VPCMPUD_op: "" is imm8=2 { local tmp:1 = 2; export *[const]:1 tmp; }
|
|
VPCMPUD_op: "" is imm8=4 { local tmp:1 = 4; export *[const]:1 tmp; }
|
|
VPCMPUD_op: "" is imm8=5 { local tmp:1 = 5; export *[const]:1 tmp; }
|
|
VPCMPUD_op: "" is imm8=6 { local tmp:1 = 6; export *[const]:1 tmp; }
|
|
|
|
VPCMPUD_mon: "VPCMPUD" is imm8 { }
|
|
VPCMPUD_op: ", "^imm8 is imm8 { export *[const]:1 imm8; }
|
|
|
|
define pcodeop vpcmpud_avx512vl ;
|
|
:^VPCMPUD_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m32bcst^VPCMPUD_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0x1E; KReg_reg ... & XmmReg2_m128_m32bcst; VPCMPUD_mon & VPCMPUD_op
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpud_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst, VPCMPUD_op );
|
|
KReg_reg = zext(AVXOpMask[0,4]) & tmp;
|
|
}
|
|
|
|
# VPCMPD/VPCMPUD 5-342 PAGE 2166 LINE 111438
|
|
:^VPCMPUD_mon KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m32bcst^VPCMPUD_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_YmmReg; byte=0x1E; KReg_reg ... & YmmReg2_m256_m32bcst; VPCMPUD_mon & VPCMPUD_op
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpud_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst, VPCMPUD_op );
|
|
KReg_reg = zext(AVXOpMask[0,8]) & tmp;
|
|
}
|
|
|
|
# VPCMPD/VPCMPUD 5-342 PAGE 2166 LINE 111442
|
|
define pcodeop vpcmpud_avx512f ;
|
|
:^VPCMPUD_mon KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst^VPCMPUD_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & AVXOpMask & evexV5_ZmmReg; byte=0x1E; KReg_reg ... & ZmmReg2_m512_m32bcst; VPCMPUD_mon & VPCMPUD_op
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpud_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, VPCMPUD_op );
|
|
KReg_reg = zext(AVXOpMask[0,16]) & tmp;
|
|
}
|
|
|
|
|
|
VPCMPQ_mon: "VPCMPEQQ" is imm8=0x0 { }
|
|
VPCMPQ_mon: "VPCMPLTQ" is imm8=0x1 { }
|
|
VPCMPQ_mon: "VPCMPLEQ" is imm8=0x2 { }
|
|
VPCMPQ_mon: "VPCMPEQQ" is imm8=0x4 { }
|
|
VPCMPQ_mon: "VPCMPNLTQ" is imm8=0x5 { }
|
|
VPCMPQ_mon: "VPCMPNLEQ" is imm8=0x6 { }
|
|
VPCMPQ_op: "" is imm8=0 { local tmp:1 = 0; export *[const]:1 tmp; }
|
|
VPCMPQ_op: "" is imm8=1 { local tmp:1 = 1; export *[const]:1 tmp; }
|
|
VPCMPQ_op: "" is imm8=2 { local tmp:1 = 2; export *[const]:1 tmp; }
|
|
VPCMPQ_op: "" is imm8=4 { local tmp:1 = 4; export *[const]:1 tmp; }
|
|
VPCMPQ_op: "" is imm8=5 { local tmp:1 = 5; export *[const]:1 tmp; }
|
|
VPCMPQ_op: "" is imm8=6 { local tmp:1 = 6; export *[const]:1 tmp; }
|
|
|
|
VPCMPQ_mon: "VPCMPQ" is imm8 { }
|
|
VPCMPQ_op: ", "^imm8 is imm8 { export *[const]:1 imm8; }
|
|
|
|
# VPCMPQ/VPCMPQ 5-345 PAGE 2169 LINE 111573
|
|
define pcodeop vpcmpq_avx512vl ;
|
|
:^VPCMPQ_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m64bcst^VPCMPQ_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0x1F; KReg_reg ... & XmmReg2_m128_m64bcst; VPCMPQ_mon & VPCMPQ_op
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst, VPCMPQ_op );
|
|
KReg_reg = zext(AVXOpMask[0,2]) & tmp;
|
|
}
|
|
|
|
# VPCMPQ/VPCMPQ 5-345 PAGE 2169 LINE 111577
|
|
:^VPCMPQ_mon KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m64bcst^VPCMPQ_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_YmmReg; byte=0x1F; KReg_reg ... & YmmReg2_m256_m64bcst; VPCMPQ_mon & VPCMPQ_op
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, VPCMPQ_op );
|
|
KReg_reg = zext(AVXOpMask[0,4]) & tmp;
|
|
}
|
|
|
|
# VPCMPQ/VPCMPQ 5-345 PAGE 2169 LINE 111581
|
|
define pcodeop vpcmpq_avx512f ;
|
|
:^VPCMPQ_mon KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst^VPCMPQ_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_ZmmReg; byte=0x1F; KReg_reg ... & ZmmReg2_m512_m64bcst; VPCMPQ_mon & VPCMPQ_op
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, VPCMPQ_op );
|
|
KReg_reg = zext(AVXOpMask[0,8]) & tmp;
|
|
}
|
|
|
|
|
|
VPCMPUQ_mon: "VPCMPEQUQ" is imm8=0x0 { }
|
|
VPCMPUQ_mon: "VPCMPLTUQ" is imm8=0x1 { }
|
|
VPCMPUQ_mon: "VPCMPLEUQ" is imm8=0x2 { }
|
|
VPCMPUQ_mon: "VPCMPEQUQ" is imm8=0x4 { }
|
|
VPCMPUQ_mon: "VPCMPNLTUQ" is imm8=0x5 { }
|
|
VPCMPUQ_mon: "VPCMPNLEUQ" is imm8=0x6 { }
|
|
VPCMPUQ_op: "" is imm8=0 { local tmp:1 = 0; export *[const]:1 tmp; }
|
|
VPCMPUQ_op: "" is imm8=1 { local tmp:1 = 1; export *[const]:1 tmp; }
|
|
VPCMPUQ_op: "" is imm8=2 { local tmp:1 = 2; export *[const]:1 tmp; }
|
|
VPCMPUQ_op: "" is imm8=4 { local tmp:1 = 4; export *[const]:1 tmp; }
|
|
VPCMPUQ_op: "" is imm8=5 { local tmp:1 = 5; export *[const]:1 tmp; }
|
|
VPCMPUQ_op: "" is imm8=6 { local tmp:1 = 6; export *[const]:1 tmp; }
|
|
|
|
VPCMPUQ_mon: "VPCMPUQ" is imm8 { }
|
|
VPCMPUQ_op: ", "^imm8 is imm8 { export *[const]:1 imm8; }
|
|
|
|
# VPCMPQ/VPCMPUQ 5-345 PAGE 2169 LINE 111585
|
|
define pcodeop vpcmpuq_avx512vl ;
|
|
:^VPCMPUQ_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m64bcst^VPCMPUQ_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0x1E; KReg_reg ... & XmmReg2_m128_m64bcst; VPCMPUQ_mon & VPCMPUQ_op
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpuq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst, VPCMPUQ_op );
|
|
KReg_reg = zext(AVXOpMask[0,2]) & tmp;
|
|
}
|
|
|
|
# VPCMPQ/VPCMPUQ 5-345 PAGE 2169 LINE 111589
|
|
:^VPCMPUQ_mon KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m64bcst^VPCMPUQ_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_YmmReg; byte=0x1E; KReg_reg ... & YmmReg2_m256_m64bcst; VPCMPUQ_mon & VPCMPUQ_op
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpuq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, VPCMPUQ_op );
|
|
KReg_reg = zext(AVXOpMask[0,4]) & tmp;
|
|
}
|
|
|
|
# VPCMPQ/VPCMPUQ 5-345 PAGE 2169 LINE 111593
|
|
define pcodeop vpcmpuq_avx512f ;
|
|
:^VPCMPUQ_mon KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst^VPCMPUQ_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_ZmmReg; byte=0x1E; KReg_reg ... & ZmmReg2_m512_m64bcst; VPCMPUQ_mon & VPCMPUQ_op
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vpcmpuq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, VPCMPUQ_op );
|
|
KReg_reg = zext(AVXOpMask[0,8]) & tmp;
|
|
}
|
|
|
|
|
|
VPCMPW_mon: "VPCMPEQW" is imm8=0x0 { }
|
|
VPCMPW_mon: "VPCMPLTW" is imm8=0x1 { }
|
|
VPCMPW_mon: "VPCMPLEW" is imm8=0x2 { }
|
|
VPCMPW_mon: "VPCMPEQW" is imm8=0x4 { }
|
|
VPCMPW_mon: "VPCMPNLTW" is imm8=0x5 { }
|
|
VPCMPW_mon: "VPCMPNLEW" is imm8=0x6 { }
|
|
VPCMPW_op: "" is imm8=0 { local tmp:1 = 0; export *[const]:1 tmp; }
|
|
VPCMPW_op: "" is imm8=1 { local tmp:1 = 1; export *[const]:1 tmp; }
|
|
VPCMPW_op: "" is imm8=2 { local tmp:1 = 2; export *[const]:1 tmp; }
|
|
VPCMPW_op: "" is imm8=4 { local tmp:1 = 4; export *[const]:1 tmp; }
|
|
VPCMPW_op: "" is imm8=5 { local tmp:1 = 5; export *[const]:1 tmp; }
|
|
VPCMPW_op: "" is imm8=6 { local tmp:1 = 6; export *[const]:1 tmp; }
|
|
|
|
VPCMPW_mon: "VPCMPW" is imm8 { }
|
|
VPCMPW_op: ", "^imm8 is imm8 { export *[const]:1 imm8; }
|
|
|
|
|
|
# VPCMPW/VPCMPUW 5-348 PAGE 2172 LINE 111724
|
|
define pcodeop vpcmpw_avx512vl ;
|
|
:^VPCMPW_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128^VPCMPW_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0x3F; KReg_reg ... & XmmReg2_m128; VPCMPW_mon & VPCMPW_op
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpw_avx512vl( evexV5_XmmReg, XmmReg2_m128, VPCMPW_op );
|
|
KReg_reg = zext(AVXOpMask[0,8]) & tmp;
|
|
}
|
|
|
|
# VPCMPW/VPCMPUW 5-348 PAGE 2172 LINE 111728
|
|
:^VPCMPW_mon KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256^VPCMPW_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_YmmReg; byte=0x3F; KReg_reg ... & YmmReg2_m256; VPCMPW_mon & VPCMPW_op
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpw_avx512vl( evexV5_YmmReg, YmmReg2_m256, VPCMPW_op );
|
|
KReg_reg = zext(AVXOpMask[0,16]) & tmp;
|
|
}
|
|
|
|
# VPCMPW/VPCMPUW 5-348 PAGE 2172 LINE 111732
|
|
define pcodeop vpcmpw_avx512bw ;
|
|
:^VPCMPW_mon KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512^VPCMPW_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_ZmmReg; byte=0x3F; KReg_reg ... & ZmmReg2_m512; VPCMPW_mon & VPCMPW_op
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512, VPCMPW_op );
|
|
KReg_reg = zext(AVXOpMask[0,32]) & tmp;
|
|
}
|
|
|
|
|
|
VPCMPUW_mon: "VPCMPEQUW" is imm8=0x0 { }
|
|
VPCMPUW_mon: "VPCMPLTUW" is imm8=0x1 { }
|
|
VPCMPUW_mon: "VPCMPLEUW" is imm8=0x2 { }
|
|
VPCMPUW_mon: "VPCMPEQUW" is imm8=0x4 { }
|
|
VPCMPUW_mon: "VPCMPNLTUW" is imm8=0x5 { }
|
|
VPCMPUW_mon: "VPCMPNLEUW" is imm8=0x6 { }
|
|
VPCMPUW_op: "" is imm8=0 { local tmp:1 = 0; export *[const]:1 tmp; }
|
|
VPCMPUW_op: "" is imm8=1 { local tmp:1 = 1; export *[const]:1 tmp; }
|
|
VPCMPUW_op: "" is imm8=2 { local tmp:1 = 2; export *[const]:1 tmp; }
|
|
VPCMPUW_op: "" is imm8=4 { local tmp:1 = 4; export *[const]:1 tmp; }
|
|
VPCMPUW_op: "" is imm8=5 { local tmp:1 = 5; export *[const]:1 tmp; }
|
|
VPCMPUW_op: "" is imm8=6 { local tmp:1 = 6; export *[const]:1 tmp; }
|
|
|
|
VPCMPUW_mon: "VPCMPUW" is imm8 { }
|
|
VPCMPUW_op: ", "^imm8 is imm8 { export *[const]:1 imm8; }
|
|
|
|
|
|
# VPCMPUW/VPCMPUUW 5-348 PAGE 2172 LINE 111724
|
|
define pcodeop vpcmpuw_avx512vl ;
|
|
:^VPCMPUW_mon KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128^VPCMPUW_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0x3E; KReg_reg ... & XmmReg2_m128; VPCMPUW_mon & VPCMPUW_op
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpuw_avx512vl( evexV5_XmmReg, XmmReg2_m128, VPCMPUW_op );
|
|
KReg_reg = zext(AVXOpMask[0,8]) & tmp;
|
|
}
|
|
|
|
# VPCMPUW/VPCMPUUW 5-348 PAGE 2172 LINE 111728
|
|
:^VPCMPUW_mon KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256^VPCMPUW_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_YmmReg; byte=0x3E; KReg_reg ... & YmmReg2_m256; VPCMPUW_mon & VPCMPUW_op
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpuw_avx512vl( evexV5_YmmReg, YmmReg2_m256, VPCMPUW_op );
|
|
KReg_reg = zext(AVXOpMask[0,16]) & tmp;
|
|
}
|
|
|
|
# VPCMPUW/VPCMPUUW 5-348 PAGE 2172 LINE 111732
|
|
define pcodeop vpcmpuw_avx512bw ;
|
|
:^VPCMPUW_mon KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512^VPCMPUW_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & AVXOpMask & evexV5_ZmmReg; byte=0x3E; KReg_reg ... & ZmmReg2_m512; VPCMPUW_mon & VPCMPUW_op
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vpcmpuw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512, VPCMPUW_op );
|
|
KReg_reg = zext(AVXOpMask[0,32]) & tmp;
|
|
}
|
|
|
|
|
|
|
|
# VPCOMPRESSD 5-351 PAGE 2175 LINE 111873
|
|
define pcodeop vpcompressd_avx512vl ;
|
|
:VPCOMPRESSD XmmReg2^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x8B; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vpcompressd_avx512vl( XmmReg1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg2 = zext(XmmResult);
|
|
}
|
|
|
|
:VPCOMPRESSD m128^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x8B; XmmReg1 ... & m128
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vpcompressd_avx512vl( XmmReg1 );
|
|
XmmMask = m128;
|
|
build XmmOpMask32;
|
|
m128 = XmmResult;
|
|
}
|
|
|
|
# VPCOMPRESSD 5-351 PAGE 2175 LINE 111875
|
|
:VPCOMPRESSD YmmReg2^YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x8B; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmResult = vpcompressd_avx512vl( YmmReg1 );
|
|
YmmMask = YmmReg2;
|
|
build YmmOpMask32;
|
|
ZmmReg2 = zext(YmmResult);
|
|
}
|
|
|
|
:VPCOMPRESSD m256^YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x8B; YmmReg1 ... & m256
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmResult = vpcompressd_avx512vl( YmmReg1 );
|
|
YmmMask = m256;
|
|
build YmmOpMask32;
|
|
m256 = YmmResult;
|
|
}
|
|
|
|
# VPCOMPRESSD 5-351 PAGE 2175 LINE 111877
|
|
define pcodeop vpcompressd_avx512f ;
|
|
:VPCOMPRESSD ZmmReg2_m512^ZmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32; byte=0x8B; ZmmReg1 ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
ZmmResult = vpcompressd_avx512f( ZmmReg1 );
|
|
ZmmMask = ZmmReg2_m512;
|
|
build ZmmOpMask32;
|
|
ZmmReg2_m512 = ZmmResult;
|
|
}
|
|
|
|
# VPCOMPRESSQ 5-353 PAGE 2177 LINE 111970
|
|
define pcodeop vpcompressq_avx512vl ;
|
|
:VPCOMPRESSQ XmmReg2^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask64; byte=0x8B; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmReg2 = vpcompressq_avx512vl( XmmReg1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg2 = zext(XmmResult);
|
|
}
|
|
|
|
:VPCOMPRESSQ m128^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask64; byte=0x8B; XmmReg1 ... & m128
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vpcompressq_avx512vl( XmmReg1 );
|
|
XmmMask = m128;
|
|
build XmmOpMask64;
|
|
m128 = XmmResult;
|
|
}
|
|
|
|
# VPCOMPRESSQ 5-353 PAGE 2177 LINE 111972
|
|
:VPCOMPRESSQ YmmReg2^YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask64; byte=0x8B; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmResult = vpcompressq_avx512vl( YmmReg1 );
|
|
YmmMask = YmmReg2;
|
|
build YmmOpMask64;
|
|
ZmmReg2 = zext(YmmResult);
|
|
}
|
|
|
|
:VPCOMPRESSQ m256 YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask64; byte=0x8B; YmmReg1 ... & m256
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmResult = vpcompressq_avx512vl( YmmReg1 );
|
|
YmmMask = m256;
|
|
build YmmOpMask64;
|
|
m256 = YmmResult;
|
|
}
|
|
|
|
# VPCOMPRESSQ 5-353 PAGE 2177 LINE 111974
|
|
define pcodeop vpcompressq_avx512f ;
|
|
:VPCOMPRESSQ ZmmReg2_m512^ZmmOpMask64, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask64; byte=0x8B; ZmmReg1 ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
ZmmResult = vpcompressq_avx512f( ZmmReg1 );
|
|
ZmmMask = ZmmReg2_m512;
|
|
build ZmmOpMask64;
|
|
ZmmReg2_m512 = ZmmResult;
|
|
}
|
|
|
|
# VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112068
|
|
define pcodeop vpconflictd_avx512vl ;
|
|
:VPCONFLICTD XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xC4; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpconflictd_avx512vl( XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112072
|
|
:VPCONFLICTD YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xC4; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpconflictd_avx512vl( YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112076
|
|
define pcodeop vpconflictd_avx512cd ;
|
|
:VPCONFLICTD ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xC4; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpconflictd_avx512cd( ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112080
|
|
define pcodeop vpconflictq_avx512vl ;
|
|
:VPCONFLICTQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xC4; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpconflictq_avx512vl( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112084
|
|
:VPCONFLICTQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xC4; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpconflictq_avx512vl( YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112088
|
|
define pcodeop vpconflictq_avx512cd ;
|
|
:VPCONFLICTQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xC4; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpconflictq_avx512cd( ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPERMD/VPERMW 5-362 PAGE 2186 LINE 112407
|
|
define pcodeop vpermd_avx512vl ;
|
|
:VPERMD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x36; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpermd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPERMD/VPERMW 5-362 PAGE 2186 LINE 112410
|
|
define pcodeop vpermd_avx512f ;
|
|
:VPERMD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x36; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpermd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPERMD/VPERMW 5-362 PAGE 2186 LINE 112413
|
|
define pcodeop vpermw_avx512vl ;
|
|
:VPERMW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x8D; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpermw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPERMD/VPERMW 5-362 PAGE 2186 LINE 112417
|
|
:VPERMW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x8D; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpermw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPERMD/VPERMW 5-362 PAGE 2186 LINE 112421
|
|
define pcodeop vpermw_avx512bw ;
|
|
:VPERMW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x8D; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpermw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112553
|
|
define pcodeop vpermi2w_avx512vl ;
|
|
:VPERMI2W XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x75; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpermi2w_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112556
|
|
:VPERMI2W YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x75; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpermi2w_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112559
|
|
define pcodeop vpermi2w_avx512bw ;
|
|
:VPERMI2W ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x75; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpermi2w_avx512bw( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112562
|
|
define pcodeop vpermi2d_avx512vl ;
|
|
:VPERMI2D XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x76; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpermi2d_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112566
|
|
:VPERMI2D YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x76; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpermi2d_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112570
|
|
define pcodeop vpermi2d_avx512f ;
|
|
:VPERMI2D ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x76; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpermi2d_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112574
|
|
define pcodeop vpermi2q_avx512vl ;
|
|
:VPERMI2Q XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x76; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpermi2q_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112578
|
|
:VPERMI2Q YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x76; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpermi2q_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112582
|
|
define pcodeop vpermi2q_avx512f ;
|
|
:VPERMI2Q ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x76; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpermi2q_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112586
|
|
define pcodeop vpermi2ps_avx512vl ;
|
|
:VPERMI2PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x77; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpermi2ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112590
|
|
:VPERMI2PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x77; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpermi2ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112594
|
|
define pcodeop vpermi2ps_avx512f ;
|
|
:VPERMI2PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x77; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpermi2ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPERMI2W/D/Q/PS/PD 5-366 PAGE 2190 LINE 112610
|
|
define pcodeop vpermi2pd_avx512vl ;
|
|
:VPERMI2PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x77; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpermi2pd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPERMI2W/D/Q/PS/PD 5-366 PAGE 2190 LINE 112614
|
|
:VPERMI2PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x77; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpermi2pd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPERMI2W/D/Q/PS/PD 5-366 PAGE 2190 LINE 112618
|
|
define pcodeop vpermi2pd_avx512f ;
|
|
:VPERMI2PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x77; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpermi2pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPERMILPD 5-371 PAGE 2195 LINE 112866
|
|
define pcodeop vpermilpd_avx512vl ;
|
|
:VPERMILPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x0D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)
|
|
{
|
|
XmmResult = vpermilpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPERMILPD 5-371 PAGE 2195 LINE 112869
|
|
:VPERMILPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x0D; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)
|
|
{
|
|
YmmResult = vpermilpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPERMILPD 5-371 PAGE 2195 LINE 112872
|
|
define pcodeop vpermilpd_avx512f ;
|
|
:VPERMILPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x0D; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)
|
|
{
|
|
ZmmResult = vpermilpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPERMILPD 5-371 PAGE 2195 LINE 112879
|
|
:VPERMILPD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x05; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM)
|
|
{
|
|
XmmResult = vpermilpd_avx512vl( XmmReg2_m128_m64bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPERMILPD 5-371 PAGE 2195 LINE 112882
|
|
:VPERMILPD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x05; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM)
|
|
{
|
|
YmmResult = vpermilpd_avx512vl( YmmReg2_m256_m64bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPERMILPD 5-371 PAGE 2195 LINE 112885
|
|
:VPERMILPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x05; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM)
|
|
{
|
|
ZmmResult = vpermilpd_avx512f( ZmmReg2_m512_m64bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPERMILPS 5-376 PAGE 2200 LINE 113170
|
|
define pcodeop vpermilps_avx512vl ;
|
|
:VPERMILPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x0C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)
|
|
{
|
|
XmmResult = vpermilps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPERMILPS 5-376 PAGE 2200 LINE 113173
|
|
:VPERMILPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x0C; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)
|
|
{
|
|
YmmResult = vpermilps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPERMILPS 5-376 PAGE 2200 LINE 113176
|
|
define pcodeop vpermilps_avx512f ;
|
|
:VPERMILPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x0C; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)
|
|
{
|
|
ZmmResult = vpermilps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPERMILPS 5-376 PAGE 2200 LINE 113179
|
|
:VPERMILPS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x04; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM)
|
|
{
|
|
XmmResult = vpermilps_avx512vl( XmmReg2_m128_m32bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPERMILPS 5-376 PAGE 2200 LINE 113182
|
|
:VPERMILPS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x04; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM)
|
|
{
|
|
YmmResult = vpermilps_avx512vl( YmmReg2_m256_m32bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPERMILPS 5-376 PAGE 2200 LINE 113186
|
|
:VPERMILPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x04; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM)
|
|
{
|
|
ZmmResult = vpermilps_avx512f( ZmmReg2_m512_m32bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPERMPD 5-381 PAGE 2205 LINE 113456
|
|
define pcodeop vpermpd_avx512vl ;
|
|
:VPERMPD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x01; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RMI)
|
|
{
|
|
YmmResult = vpermpd_avx512vl( YmmReg2_m256_m64bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPERMPD 5-381 PAGE 2205 LINE 113459
|
|
define pcodeop vpermpd_avx512f ;
|
|
:VPERMPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x01; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RMI)
|
|
{
|
|
ZmmResult = vpermpd_avx512f( ZmmReg2_m512_m64bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPERMPD 5-381 PAGE 2205 LINE 113462
|
|
:VPERMPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x16; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)
|
|
{
|
|
YmmResult = vpermpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPERMPD 5-381 PAGE 2205 LINE 113465
|
|
:VPERMPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x16; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)
|
|
{
|
|
ZmmResult = vpermpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPERMPS 5-384 PAGE 2208 LINE 113636
|
|
define pcodeop vpermps_avx512vl ;
|
|
:VPERMPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x16; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpermps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPERMPS 5-384 PAGE 2208 LINE 113639
|
|
define pcodeop vpermps_avx512f ;
|
|
:VPERMPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x16; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpermps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPERMQ 5-387 PAGE 2211 LINE 113771
|
|
define pcodeop vpermq_avx512vl ;
|
|
:VPERMQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x00; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RMI)
|
|
{
|
|
YmmResult = vpermq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPERMQ 5-387 PAGE 2211 LINE 113774
|
|
define pcodeop vpermq_avx512f ;
|
|
:VPERMQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x00; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RMI)
|
|
{
|
|
ZmmResult = vpermq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPERMQ 5-387 PAGE 2211 LINE 113777
|
|
:VPERMQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x36; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)
|
|
{
|
|
YmmResult = vpermq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPERMQ 5-387 PAGE 2211 LINE 113780
|
|
:VPERMQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x36; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)
|
|
{
|
|
ZmmResult = vpermq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
define pcodeop vpermt2pd_avx512f;
|
|
:VPERMT2PD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x7F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst {
|
|
XmmResult = vpermt2pd_avx512f( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
:VPERMT2PD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x7F; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst {
|
|
YmmResult = vpermt2pd_avx512f( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
:VPERMT2PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x7F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst {
|
|
ZmmResult = vpermt2pd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPEXPANDD 5-390 PAGE 2214 LINE 113945
|
|
define pcodeop vpexpandd_avx512vl ;
|
|
:VPEXPANDD XmmReg1^XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x89; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vpexpandd_avx512vl( XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPEXPANDD 5-390 PAGE 2214 LINE 113948
|
|
:VPEXPANDD YmmReg1^YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x89; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmResult = vpexpandd_avx512vl( YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPEXPANDD 5-390 PAGE 2214 LINE 113951
|
|
define pcodeop vpexpandd_avx512f ;
|
|
:VPEXPANDD ZmmReg1^ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x89; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
ZmmResult = vpexpandd_avx512f( ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPEXPANDQ 5-392 PAGE 2216 LINE 114033
|
|
define pcodeop vpexpandq_avx512vl ;
|
|
:VPEXPANDQ XmmReg1^XmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x89; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vpexpandq_avx512vl( XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPEXPANDQ 5-392 PAGE 2216 LINE 114035
|
|
:VPEXPANDQ YmmReg1^YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x89; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
YmmResult = vpexpandq_avx512vl( YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPEXPANDQ 5-392 PAGE 2216 LINE 114037
|
|
define pcodeop vpexpandq_avx512f ;
|
|
:VPEXPANDQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x89; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
ZmmResult = vpexpandq_avx512f( ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPLZCNTD/Q 5-394 PAGE 2218 LINE 114118
|
|
define pcodeop vplzcntd_avx512vl ;
|
|
:VPLZCNTD XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x44; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vplzcntd_avx512vl( XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPLZCNTD/Q 5-394 PAGE 2218 LINE 114122
|
|
:VPLZCNTD YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x44; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vplzcntd_avx512vl( YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPLZCNTD/Q 5-394 PAGE 2218 LINE 114126
|
|
define pcodeop vplzcntd_avx512cd ;
|
|
:VPLZCNTD ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x44; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vplzcntd_avx512cd( ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPLZCNTD/Q 5-394 PAGE 2218 LINE 114130
|
|
define pcodeop vplzcntq_avx512vl ;
|
|
:VPLZCNTQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x44; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vplzcntq_avx512vl( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPLZCNTD/Q 5-394 PAGE 2218 LINE 114134
|
|
:VPLZCNTQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x44; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vplzcntq_avx512vl( YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPLZCNTD/Q 5-394 PAGE 2218 LINE 114138
|
|
define pcodeop vplzcntq_avx512cd ;
|
|
:VPLZCNTQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x44; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vplzcntq_avx512cd( ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114413
|
|
define pcodeop vpmovm2b_avx512vl ;
|
|
:VPMOVM2B XmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x28; (XmmReg1 & ZmmReg1) & KReg_rm
|
|
{
|
|
local tmp:16 = vpmovm2b_avx512vl( KReg_rm );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114415
|
|
:VPMOVM2B YmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x28; (YmmReg1 & ZmmReg1) & KReg_rm
|
|
{
|
|
local tmp:32 = vpmovm2b_avx512vl( KReg_rm );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114417
|
|
define pcodeop vpmovm2b_avx512bw ;
|
|
:VPMOVM2B ZmmReg1, KReg_rm is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x28; ZmmReg1 & KReg_rm
|
|
{
|
|
ZmmReg1 = vpmovm2b_avx512bw( KReg_rm );
|
|
}
|
|
|
|
# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114419
|
|
define pcodeop vpmovm2w_avx512vl ;
|
|
:VPMOVM2W XmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x28; (XmmReg1 & ZmmReg1) & KReg_rm
|
|
{
|
|
local tmp:16 = vpmovm2w_avx512vl( KReg_rm );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114421
|
|
:VPMOVM2W YmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x28; (YmmReg1 & ZmmReg1) & KReg_rm
|
|
{
|
|
local tmp:32 = vpmovm2w_avx512vl( KReg_rm );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114423
|
|
define pcodeop vpmovm2w_avx512bw ;
|
|
:VPMOVM2W ZmmReg1, KReg_rm is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x28; ZmmReg1 & KReg_rm
|
|
{
|
|
ZmmReg1 = vpmovm2w_avx512bw( KReg_rm );
|
|
}
|
|
|
|
# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114425
|
|
define pcodeop vpmovm2d_avx512vl ;
|
|
:VPMOVM2D XmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x38; (XmmReg1 & ZmmReg1) & KReg_rm
|
|
{
|
|
local tmp:16 = vpmovm2d_avx512vl( KReg_rm );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114427
|
|
:VPMOVM2D YmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x38; (YmmReg1 & ZmmReg1) & KReg_rm
|
|
{
|
|
local tmp:32 = vpmovm2d_avx512vl( KReg_rm );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114429
|
|
define pcodeop vpmovm2d_avx512dq ;
|
|
:VPMOVM2D ZmmReg1, KReg_rm is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x38; ZmmReg1 & KReg_rm
|
|
{
|
|
ZmmReg1 = vpmovm2d_avx512dq( KReg_rm );
|
|
}
|
|
|
|
# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114431
|
|
define pcodeop vpmovm2q_avx512vl ;
|
|
:VPMOVM2Q XmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x38; (XmmReg1 & ZmmReg1) & KReg_rm
|
|
{
|
|
local tmp:16 = vpmovm2q_avx512vl( KReg_rm );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114433
|
|
:VPMOVM2Q YmmReg1, KReg_rm is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x38; (YmmReg1 & ZmmReg1) & KReg_rm
|
|
{
|
|
local tmp:32 = vpmovm2q_avx512vl( KReg_rm );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q 5-400 PAGE 2224 LINE 114435
|
|
define pcodeop vpmovm2q_avx512dq ;
|
|
:VPMOVM2Q ZmmReg1, KReg_rm is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x38; ZmmReg1 & KReg_rm
|
|
{
|
|
ZmmReg1 = vpmovm2q_avx512dq( KReg_rm );
|
|
}
|
|
|
|
# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114542
|
|
define pcodeop vpmovb2m_avx512vl ;
|
|
:VPMOVB2M KReg_reg, XmmReg2 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x29; KReg_reg & (mod=0x3 & XmmReg2)
|
|
{
|
|
KReg_reg = vpmovb2m_avx512vl( XmmReg2 );
|
|
}
|
|
|
|
# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114544
|
|
:VPMOVB2M KReg_reg, YmmReg2 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x29; KReg_reg & (mod=0x3 & YmmReg2)
|
|
{
|
|
KReg_reg = vpmovb2m_avx512vl( YmmReg2 );
|
|
}
|
|
|
|
# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114546
|
|
define pcodeop vpmovb2m_avx512bw ;
|
|
:VPMOVB2M KReg_reg, ZmmReg2 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x29; KReg_reg & (mod=0x3 & ZmmReg2)
|
|
{
|
|
KReg_reg = vpmovb2m_avx512bw( ZmmReg2 );
|
|
}
|
|
|
|
# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114548
|
|
define pcodeop vpmovw2m_avx512vl ;
|
|
:VPMOVW2M KReg_reg, XmmReg2 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x29; KReg_reg & (mod=0x3 & XmmReg2)
|
|
{
|
|
KReg_reg = vpmovw2m_avx512vl( XmmReg2 );
|
|
}
|
|
|
|
# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114550
|
|
:VPMOVW2M KReg_reg, YmmReg2 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x29; KReg_reg & (mod=0x3 & YmmReg2)
|
|
{
|
|
KReg_reg = vpmovw2m_avx512vl( YmmReg2 );
|
|
}
|
|
|
|
# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114552
|
|
define pcodeop vpmovw2m_avx512bw ;
|
|
:VPMOVW2M KReg_reg, ZmmReg2 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x29; KReg_reg & (mod=0x3 & ZmmReg2)
|
|
{
|
|
KReg_reg = vpmovw2m_avx512bw( ZmmReg2 );
|
|
}
|
|
|
|
# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114554
|
|
define pcodeop vpmovd2m_avx512vl ;
|
|
:VPMOVD2M KReg_reg, XmmReg2 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x39; KReg_reg & (mod=0x3 & XmmReg2)
|
|
{
|
|
KReg_reg = vpmovd2m_avx512vl( XmmReg2 );
|
|
}
|
|
|
|
# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114556
|
|
:VPMOVD2M KReg_reg, YmmReg2 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x39; KReg_reg & (mod=0x3 & YmmReg2)
|
|
{
|
|
KReg_reg = vpmovd2m_avx512vl( YmmReg2 );
|
|
}
|
|
|
|
# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114558
|
|
define pcodeop vpmovd2m_avx512dq ;
|
|
:VPMOVD2M KReg_reg, ZmmReg2 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0); byte=0x39; KReg_reg & (mod=0x3 & ZmmReg2)
|
|
{
|
|
KReg_reg = vpmovd2m_avx512dq( ZmmReg2 );
|
|
}
|
|
|
|
# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114560
|
|
define pcodeop vpmovq2m_avx512vl ;
|
|
:VPMOVQ2M KReg_reg, XmmReg2 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x39; KReg_reg & (mod=0x3 & XmmReg2)
|
|
{
|
|
KReg_reg = vpmovq2m_avx512vl( XmmReg2 );
|
|
}
|
|
|
|
# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114562
|
|
:VPMOVQ2M KReg_reg, YmmReg2 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x39; KReg_reg & (mod=0x3 & YmmReg2)
|
|
{
|
|
KReg_reg = vpmovq2m_avx512vl( YmmReg2 );
|
|
}
|
|
|
|
# VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M 5-403 PAGE 2227 LINE 114564
|
|
define pcodeop vpmovq2m_avx512dq ;
|
|
:VPMOVQ2M KReg_reg, ZmmReg2 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1); byte=0x39; KReg_reg & (mod=0x3 & ZmmReg2)
|
|
{
|
|
KReg_reg = vpmovq2m_avx512dq( ZmmReg2 );
|
|
}
|
|
|
|
|
|
# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115959
|
|
define pcodeop vprolvd_avx512vl ;
|
|
:VPROLVD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)
|
|
{
|
|
XmmResult = vprolvd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115962
|
|
define pcodeop vprold_avx512vl ;
|
|
:VPROLD evexV5_XmmReg^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask32; byte=0x72; reg_opcode=1 ... & XmmReg2_m128_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)
|
|
{
|
|
XmmResult = vprold_avx512vl( XmmReg2_m128_m32bcst, imm8:1 );
|
|
XmmMask = evexV5_XmmReg;
|
|
build XmmOpMask32;
|
|
evexV5_ZmmReg = zext(XmmResult);
|
|
}
|
|
|
|
# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115965
|
|
define pcodeop vprolvq_avx512vl ;
|
|
:VPROLVQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)
|
|
{
|
|
XmmResult = vprolvq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115968
|
|
define pcodeop vprolq_avx512vl ;
|
|
:VPROLQ evexV5_XmmReg^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask64; byte=0x72; reg_opcode=1 ... & XmmReg2_m128_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)
|
|
{
|
|
XmmResult = vprolq_avx512vl( XmmReg2_m128_m64bcst, imm8:1 );
|
|
XmmMask = evexV5_XmmReg;
|
|
build XmmOpMask64;
|
|
evexV5_ZmmReg = zext(XmmResult);
|
|
}
|
|
|
|
# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115971
|
|
:VPROLVD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)
|
|
{
|
|
YmmResult = vprolvd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115974
|
|
:VPROLD evexV5_YmmReg^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask32; byte=0x72; reg_opcode=1 ... & YmmReg2_m256_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)
|
|
{
|
|
YmmResult = vprold_avx512vl( YmmReg2_m256_m32bcst, imm8:1 );
|
|
YmmMask = evexV5_YmmReg;
|
|
build YmmOpMask32;
|
|
evexV5_ZmmReg = zext(YmmResult);
|
|
}
|
|
|
|
# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115977
|
|
:VPROLVQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)
|
|
{
|
|
YmmResult = vprolvq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115980
|
|
:VPROLQ evexV5_YmmReg^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask64; byte=0x72; reg_opcode=1 ... & YmmReg2_m256_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)
|
|
{
|
|
YmmResult = vprolq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 );
|
|
YmmMask = evexV5_YmmReg;
|
|
build YmmOpMask64;
|
|
evexV5_ZmmReg = zext(YmmResult);
|
|
}
|
|
|
|
# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115983
|
|
define pcodeop vprolvd_avx512f ;
|
|
:VPROLVD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x15; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)
|
|
{
|
|
ZmmResult = vprolvd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115987
|
|
define pcodeop vprold_avx512f ;
|
|
:VPROLD evexV5_ZmmReg^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & ZmmOpMask32; byte=0x72; reg_opcode=1 ... & ZmmReg2_m512_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)
|
|
{
|
|
ZmmResult = vprold_avx512f( ZmmReg2_m512_m32bcst, imm8:1 );
|
|
ZmmMask = evexV5_ZmmReg;
|
|
build ZmmOpMask32;
|
|
evexV5_ZmmReg = ZmmResult;
|
|
}
|
|
|
|
# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115990
|
|
define pcodeop vprolvq_avx512f ;
|
|
:VPROLVQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x15; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)
|
|
{
|
|
ZmmResult = vprolvq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115993
|
|
define pcodeop vprolq_avx512f ;
|
|
:VPROLQ evexV5_ZmmReg^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & ZmmOpMask64; byte=0x72; reg_opcode=1 ... & ZmmReg2_m512_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)
|
|
{
|
|
ZmmResult = vprolq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 );
|
|
ZmmMask = evexV5_ZmmReg;
|
|
build ZmmOpMask64;
|
|
evexV5_ZmmReg = ZmmResult;
|
|
}
|
|
|
|
# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116190
|
|
define pcodeop vprorvd_avx512vl ;
|
|
:VPRORVD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)
|
|
{
|
|
XmmResult = vprorvd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116194
|
|
define pcodeop vprord_avx512vl ;
|
|
:VPRORD evexV5_XmmReg^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask32; byte=0x72; reg_opcode=0 ... & XmmReg2_m128_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)
|
|
{
|
|
XmmResult = vprord_avx512vl( XmmReg2_m128_m32bcst, imm8:1 );
|
|
XmmMask = evexV5_XmmReg;
|
|
build XmmOpMask32;
|
|
evexV5_ZmmReg = zext(XmmResult);
|
|
}
|
|
|
|
# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116197
|
|
define pcodeop vprorvq_avx512vl ;
|
|
:VPRORVQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)
|
|
{
|
|
XmmResult = vprorvq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116200
|
|
define pcodeop vprorq_avx512vl ;
|
|
:VPRORQ evexV5_XmmReg^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (evexV5_XmmReg & evexV5_ZmmReg) & XmmOpMask64; byte=0x72; reg_opcode=0 ... & XmmReg2_m128_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)
|
|
{
|
|
XmmResult = vprorq_avx512vl( XmmReg2_m128_m64bcst, imm8:1 );
|
|
XmmMask = evexV5_XmmReg;
|
|
build XmmOpMask64;
|
|
evexV5_ZmmReg = zext(XmmResult);
|
|
}
|
|
|
|
# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116203
|
|
:VPRORVD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)
|
|
{
|
|
YmmResult = vprorvd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116207
|
|
:VPRORD evexV5_YmmReg^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask32; byte=0x72; reg_opcode=0 ... & YmmReg2_m256_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)
|
|
{
|
|
YmmResult = vprord_avx512vl( YmmReg2_m256_m32bcst, imm8:1 );
|
|
YmmMask = evexV5_YmmReg;
|
|
build YmmOpMask32;
|
|
evexV5_ZmmReg = zext(YmmResult);
|
|
}
|
|
|
|
# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116210
|
|
:VPRORVQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)
|
|
{
|
|
YmmResult = vprorvq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116213
|
|
:VPRORQ evexV5_YmmReg^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (evexV5_YmmReg & evexV5_ZmmReg) & YmmOpMask64; byte=0x72; reg_opcode=0 ... & YmmReg2_m256_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)
|
|
{
|
|
YmmResult = vprorq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 );
|
|
YmmMask = evexV5_YmmReg;
|
|
build YmmOpMask64;
|
|
evexV5_ZmmReg = zext(YmmResult);
|
|
}
|
|
|
|
# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116216
|
|
define pcodeop vprorvd_avx512f ;
|
|
:VPRORVD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x14; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)
|
|
{
|
|
ZmmResult = vprorvd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116220
|
|
define pcodeop vprord_avx512f ;
|
|
:VPRORD evexV5_ZmmReg^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & ZmmOpMask32; byte=0x72; reg_opcode=0 ... & ZmmReg2_m512_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)
|
|
{
|
|
ZmmResult = vprord_avx512f( ZmmReg2_m512_m32bcst, imm8:1 );
|
|
ZmmMask = evexV5_ZmmReg;
|
|
build ZmmOpMask32;
|
|
evexV5_ZmmReg = ZmmResult;
|
|
}
|
|
|
|
# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116223
|
|
define pcodeop vprorvq_avx512f ;
|
|
:VPRORVQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x14; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM)
|
|
{
|
|
ZmmResult = vprorvq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116226
|
|
define pcodeop vprorq_avx512f ;
|
|
:VPRORQ evexV5_ZmmReg^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & ZmmOpMask64; byte=0x72; reg_opcode=0 ... & ZmmReg2_m512_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI)
|
|
{
|
|
ZmmResult = vprorq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 );
|
|
ZmmMask = evexV5_ZmmReg;
|
|
build ZmmOpMask64;
|
|
evexV5_ZmmReg = ZmmResult;
|
|
}
|
|
|
|
# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116424
|
|
define pcodeop vpscatterdd_avx512vl ;
|
|
:VPSCATTERDD x_vm32x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA0; XmmReg1 ... & x_vm32x
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vpscatterdd_avx512vl( x_vm32x, XmmOpMask, XmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116426
|
|
:VPSCATTERDD y_vm32y^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0xA0; YmmReg1 ... & y_vm32y
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vpscatterdd_avx512vl( y_vm32y, YmmOpMask, YmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116428
|
|
define pcodeop vpscatterdd_avx512f ;
|
|
:VPSCATTERDD z_vm32z^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xA0; ZmmReg1 ... & z_vm32z
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vpscatterdd_avx512f( z_vm32z, ZmmOpMask, ZmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116430
|
|
define pcodeop vpscatterdq_avx512vl ;
|
|
:VPSCATTERDQ x_vm32x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xA0; XmmReg1 ... & x_vm32x
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vpscatterdq_avx512vl( x_vm32x, XmmOpMask, XmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116432
|
|
:VPSCATTERDQ y_vm32y^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xA0; YmmReg1 ... & y_vm32y
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vpscatterdq_avx512vl( y_vm32y, YmmOpMask, YmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116434
|
|
define pcodeop vpscatterdq_avx512f ;
|
|
:VPSCATTERDQ z_vm32z^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xA0; ZmmReg1 ... & z_vm32z
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vpscatterdq_avx512f( z_vm32z, ZmmOpMask, ZmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
@ifdef IA64
|
|
#technically these should be supported in 32-bit mode, but the assembly differences are notable, and we don't handle vm64 in 32-bit
|
|
# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116436
|
|
# WARNING: did not recognize qualifier /vsib for "VPSCATTERQD vm64x {k1}, xmm1"
|
|
define pcodeop vpscatterqd_avx512vl ;
|
|
:VPSCATTERQD q_vm64x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA1; XmmReg1 ... & q_vm64x
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vpscatterqd_avx512vl( q_vm64x, XmmOpMask, XmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116438
|
|
# WARNING: did not recognize qualifier /vsib for "VPSCATTERQD vm64y {k1}, xmm1"
|
|
:VPSCATTERQD q_vm64x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA1; XmmReg1 ... & q_vm64x
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vpscatterqd_avx512vl( q_vm64x, XmmOpMask, XmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116440
|
|
# WARNING: did not recognize qualifier /vsib for "VPSCATTERQD vm64z {k1}, ymm1"
|
|
define pcodeop vpscatterqd_avx512f ;
|
|
:VPSCATTERQD q_vm64y^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0xA1; YmmReg1 ... & q_vm64y
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vpscatterqd_avx512f( q_vm64y, YmmOpMask, YmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116442
|
|
# WARNING: did not recognize qualifier /vsib for "VPSCATTERQQ vm64x {k1}, xmm1"
|
|
define pcodeop vpscatterqq_avx512vl ;
|
|
:VPSCATTERQQ x_vm64x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xA1; XmmReg1 ... & x_vm64x
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vpscatterqq_avx512vl( x_vm64x, XmmOpMask, XmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116444
|
|
# WARNING: did not recognize qualifier /vsib for "VPSCATTERQQ vm64y {k1}, ymm1"
|
|
:VPSCATTERQQ y_vm64y^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xA1; YmmReg1 ... & y_vm64y
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vpscatterqq_avx512vl( y_vm64y, YmmOpMask, YmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116446
|
|
# WARNING: did not recognize qualifier /vsib for "VPSCATTERQQ vm64z {k1}, zmm1"
|
|
define pcodeop vpscatterqq_avx512f ;
|
|
:VPSCATTERQQ z_vm64z^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xA1; ZmmReg1 ... & z_vm64z
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vpscatterqq_avx512f( z_vm64z, ZmmOpMask, ZmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
@endif
|
|
|
|
# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116632
|
|
define pcodeop vpsllvw_avx512vl ;
|
|
:VPSLLVW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x12; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpsllvw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116635
|
|
:VPSLLVW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x12; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpsllvw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116638
|
|
define pcodeop vpsllvw_avx512bw ;
|
|
:VPSLLVW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x12; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpsllvw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116641
|
|
define pcodeop vpsllvd_avx512vl ;
|
|
:VPSLLVD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x47; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpsllvd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116644
|
|
:VPSLLVD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x47; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpsllvd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116647
|
|
define pcodeop vpsllvd_avx512f ;
|
|
:VPSLLVD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x47; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpsllvd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116650
|
|
define pcodeop vpsllvq_avx512vl ;
|
|
:VPSLLVQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x47; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpsllvq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116653
|
|
:VPSLLVQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x47; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpsllvq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116656
|
|
define pcodeop vpsllvq_avx512f ;
|
|
:VPSLLVQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x47; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpsllvq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116880
|
|
define pcodeop vpsravw_avx512vl ;
|
|
:VPSRAVW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x11; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpsravw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116883
|
|
:VPSRAVW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x11; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpsravw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116886
|
|
define pcodeop vpsravw_avx512bw ;
|
|
:VPSRAVW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x11; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpsravw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116889
|
|
define pcodeop vpsravd_avx512vl ;
|
|
:VPSRAVD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x46; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpsravd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116893
|
|
:VPSRAVD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x46; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpsravd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116897
|
|
define pcodeop vpsravd_avx512f ;
|
|
:VPSRAVD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x46; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpsravd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116901
|
|
define pcodeop vpsravq_avx512vl ;
|
|
:VPSRAVQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x46; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpsravq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116905
|
|
:VPSRAVQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x46; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpsravq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116910
|
|
define pcodeop vpsravq_avx512f ;
|
|
:VPSRAVQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x46; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpsravq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117151
|
|
define pcodeop vpsrlvw_avx512vl ;
|
|
:VPSRLVW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
XmmResult = vpsrlvw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117154
|
|
:VPSRLVW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x10; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
YmmResult = vpsrlvw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117157
|
|
define pcodeop vpsrlvw_avx512bw ;
|
|
:VPSRLVW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x10; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
ZmmResult = vpsrlvw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117160
|
|
define pcodeop vpsrlvd_avx512vl ;
|
|
:VPSRLVD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x45; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpsrlvd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117163
|
|
:VPSRLVD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x45; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpsrlvd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117166
|
|
define pcodeop vpsrlvd_avx512f ;
|
|
:VPSRLVD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x45; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpsrlvd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117169
|
|
define pcodeop vpsrlvq_avx512vl ;
|
|
:VPSRLVQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x45; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpsrlvq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117172
|
|
:VPSRLVQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x45; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpsrlvq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117175
|
|
define pcodeop vpsrlvq_avx512f ;
|
|
:VPSRLVQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x45; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpsrlvq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117395
|
|
define pcodeop vpternlogd_avx512vl ;
|
|
:VPTERNLOGD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x25; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpternlogd_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117400
|
|
:VPTERNLOGD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_YmmReg; byte=0x25; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpternlogd_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117405
|
|
define pcodeop vpternlogd_avx512f ;
|
|
:VPTERNLOGD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x25; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpternlogd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117410
|
|
define pcodeop vpternlogq_avx512vl ;
|
|
:VPTERNLOGQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_XmmReg; byte=0x25; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vpternlogq_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117415
|
|
:VPTERNLOGQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_YmmReg; byte=0x25; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vpternlogq_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117420
|
|
define pcodeop vpternlogq_avx512f ;
|
|
:VPTERNLOGQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x25; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vpternlogq_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117559
|
|
define pcodeop vptestmb_avx512vl ;
|
|
:VPTESTMB KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0x26; KReg_reg ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vptestmb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
KReg_reg = zext(AVXOpMask[0,16]) & tmp;
|
|
}
|
|
|
|
# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117562
|
|
:VPTESTMB KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_YmmReg; byte=0x26; KReg_reg ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vptestmb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
KReg_reg = zext(AVXOpMask[0,32]) & tmp;
|
|
}
|
|
|
|
# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117565
|
|
define pcodeop vptestmb_avx512bw ;
|
|
:VPTESTMB KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_ZmmReg; byte=0x26; KReg_reg ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vptestmb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
KReg_reg = zext(AVXOpMask[0,64]) & tmp;
|
|
}
|
|
|
|
# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117568
|
|
define pcodeop vptestmw_avx512vl ;
|
|
:VPTESTMW KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0x26; KReg_reg ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vptestmw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
KReg_reg = zext(AVXOpMask[0,8]) & tmp;
|
|
}
|
|
|
|
# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117571
|
|
:VPTESTMW KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_YmmReg; byte=0x26; KReg_reg ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vptestmw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
KReg_reg = zext(AVXOpMask[0,16]) & tmp;
|
|
}
|
|
|
|
# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117574
|
|
define pcodeop vptestmw_avx512bw ;
|
|
:VPTESTMW KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_ZmmReg; byte=0x26; KReg_reg ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vptestmw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
KReg_reg = zext(AVXOpMask[0,32]) & tmp;
|
|
}
|
|
|
|
# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117577
|
|
define pcodeop vptestmd_avx512vl ;
|
|
:VPTESTMD KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0x27; KReg_reg ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vptestmd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
KReg_reg = zext(AVXOpMask[0,4]) & tmp;
|
|
}
|
|
|
|
# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117581
|
|
:VPTESTMD KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_YmmReg; byte=0x27; KReg_reg ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vptestmd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
KReg_reg = zext(AVXOpMask[0,8]) & tmp;
|
|
}
|
|
|
|
# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117585
|
|
define pcodeop vptestmd_avx512f ;
|
|
:VPTESTMD KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_ZmmReg; byte=0x27; KReg_reg ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vptestmd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
KReg_reg = zext(AVXOpMask[0,16]) & tmp;
|
|
}
|
|
|
|
# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117589
|
|
define pcodeop vptestmq_avx512vl ;
|
|
:VPTESTMQ KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0x27; KReg_reg ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vptestmq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
KReg_reg = zext(AVXOpMask[0,2]) & tmp;
|
|
}
|
|
|
|
# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117593
|
|
:VPTESTMQ KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_YmmReg; byte=0x27; KReg_reg ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vptestmq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
KReg_reg = zext(AVXOpMask[0,4]) & tmp;
|
|
}
|
|
|
|
# VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117597
|
|
define pcodeop vptestmq_avx512f ;
|
|
:VPTESTMQ KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_ZmmReg; byte=0x27; KReg_reg ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vptestmq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
KReg_reg = zext(AVXOpMask[0,8]) & tmp;
|
|
}
|
|
|
|
# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117717
|
|
define pcodeop vptestnmb_avx512vl ;
|
|
:VPTESTNMB KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0x26; KReg_reg ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vptestnmb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
KReg_reg = zext(AVXOpMask[0,16]) & tmp;
|
|
}
|
|
|
|
# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117721
|
|
:VPTESTNMB KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_YmmReg; byte=0x26; KReg_reg ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vptestnmb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
KReg_reg = zext(AVXOpMask[0,32]) & tmp;
|
|
}
|
|
|
|
# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117725
|
|
define pcodeop vptestnmb_avx512f ;
|
|
:VPTESTNMB KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_ZmmReg; byte=0x26; KReg_reg ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vptestnmb_avx512f( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
KReg_reg = zext(AVXOpMask[0,64]) & tmp;
|
|
}
|
|
|
|
# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117729
|
|
define pcodeop vptestnmw_avx512vl ;
|
|
:VPTESTNMW KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0x26; KReg_reg ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vptestnmw_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
KReg_reg = zext(AVXOpMask[0,8]) & tmp;
|
|
}
|
|
|
|
# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117733
|
|
:VPTESTNMW KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_YmmReg; byte=0x26; KReg_reg ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vptestnmw_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
KReg_reg = zext(AVXOpMask[0,16]) & tmp;
|
|
}
|
|
|
|
# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117737
|
|
define pcodeop vptestnmw_avx512f ;
|
|
:VPTESTNMW KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_ZmmReg; byte=0x26; KReg_reg ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
|
|
{
|
|
local tmp = vptestnmw_avx512f( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
KReg_reg = zext(AVXOpMask[0,32]) & tmp;
|
|
}
|
|
|
|
# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117741
|
|
define pcodeop vptestnmd_avx512vl ;
|
|
:VPTESTNMD KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_XmmReg; byte=0x27; KReg_reg ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vptestnmd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
KReg_reg = zext(AVXOpMask[0,4]) & tmp;
|
|
}
|
|
|
|
# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117745
|
|
:VPTESTNMD KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_YmmReg; byte=0x27; KReg_reg ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vptestnmd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
KReg_reg = zext(AVXOpMask[0,8]) & tmp;
|
|
}
|
|
|
|
# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117749
|
|
define pcodeop vptestnmd_avx512f ;
|
|
:VPTESTNMD KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & AVXOpMask & evexV5_ZmmReg; byte=0x27; KReg_reg ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vptestnmd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
KReg_reg = zext(AVXOpMask[0,16]) & tmp;
|
|
}
|
|
|
|
# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117753
|
|
define pcodeop vptestnmq_avx512vl ;
|
|
:VPTESTNMQ KReg_reg AVXOpMask, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_XmmReg; byte=0x27; KReg_reg ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vptestnmq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
KReg_reg = zext(AVXOpMask[0,2]) & tmp;
|
|
}
|
|
|
|
# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117757
|
|
:VPTESTNMQ KReg_reg AVXOpMask, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_YmmReg; byte=0x27; KReg_reg ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vptestnmq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
KReg_reg = zext(AVXOpMask[0,4]) & tmp;
|
|
}
|
|
|
|
# VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117761
|
|
define pcodeop vptestnmq_avx512f ;
|
|
:VPTESTNMQ KReg_reg AVXOpMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & AVXOpMask & evexV5_ZmmReg; byte=0x27; KReg_reg ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
local tmp = vptestnmq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
KReg_reg = zext(AVXOpMask[0,8]) & tmp;
|
|
}
|
|
|
|
# VRANGEPD 5-470 PAGE 2294 LINE 117905
|
|
define pcodeop vrangepd_avx512vl ;
|
|
:VRANGEPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_XmmReg; byte=0x50; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vrangepd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VRANGEPD 5-470 PAGE 2294 LINE 117910
|
|
:VRANGEPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_YmmReg; byte=0x50; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vrangepd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VRANGEPD 5-470 PAGE 2294 LINE 117915
|
|
define pcodeop vrangepd_avx512dq ;
|
|
:VRANGEPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x50; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vrangepd_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VRANGEPS 5-475 PAGE 2299 LINE 118139
|
|
define pcodeop vrangeps_avx512vl ;
|
|
:VRANGEPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x50; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vrangeps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VRANGEPS 5-475 PAGE 2299 LINE 118144
|
|
:VRANGEPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_YmmReg; byte=0x50; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vrangeps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VRANGEPS 5-475 PAGE 2299 LINE 118149
|
|
define pcodeop vrangeps_avx512dq ;
|
|
:VRANGEPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x50; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vrangeps_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VRANGESD 5-479 PAGE 2303 LINE 118318
|
|
define pcodeop vrangesd_avx512dq ;
|
|
:VRANGESD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64; imm8
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vrangesd_avx512dq( evexV5_XmmReg, XmmReg2_m64, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VRANGESS 5-482 PAGE 2306 LINE 118473
|
|
define pcodeop vrangess_avx512dq ;
|
|
:VRANGESS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32; imm8
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vrangess_avx512dq( evexV5_XmmReg, XmmReg2_m32, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VRCP14PD 5-485 PAGE 2309 LINE 118626
|
|
define pcodeop vrcp14pd_avx512vl ;
|
|
:VRCP14PD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vrcp14pd_avx512vl( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VRCP14PD 5-485 PAGE 2309 LINE 118629
|
|
:VRCP14PD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4C; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vrcp14pd_avx512vl( YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VRCP14PD 5-485 PAGE 2309 LINE 118632
|
|
define pcodeop vrcp14pd_avx512f ;
|
|
:VRCP14PD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4C; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vrcp14pd_avx512f( ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VRCP14SD 5-487 PAGE 2311 LINE 118726
|
|
define pcodeop vrcp14sd_avx512f ;
|
|
:VRCP14SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x4D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vrcp14sd_avx512f( evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VRCP14PS 5-489 PAGE 2313 LINE 118800
|
|
define pcodeop vrcp14ps_avx512vl ;
|
|
:VRCP14PS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vrcp14ps_avx512vl( XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VRCP14PS 5-489 PAGE 2313 LINE 118803
|
|
:VRCP14PS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4C; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vrcp14ps_avx512vl( YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VRCP14PS 5-489 PAGE 2313 LINE 118806
|
|
define pcodeop vrcp14ps_avx512f ;
|
|
:VRCP14PS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4C; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vrcp14ps_avx512f( ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VRCP14SS 5-491 PAGE 2315 LINE 118904
|
|
define pcodeop vrcp14ss_avx512f ;
|
|
:VRCP14SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x4D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vrcp14ss_avx512f( evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VRCP28PD 5-493 PAGE 2317 LINE 118979
|
|
define pcodeop vrcp28pd_avx512er ;
|
|
:VRCP28PD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xCA; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vrcp28pd_avx512er( ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VRCP28SD 5-495 PAGE 2319 LINE 119074
|
|
define pcodeop vrcp28sd_avx512er ;
|
|
:VRCP28SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xCB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vrcp28sd_avx512er( evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VRCP28PS 5-497 PAGE 2321 LINE 119167
|
|
define pcodeop vrcp28ps_avx512er ;
|
|
:VRCP28PS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xCA; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vrcp28ps_avx512er( ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VRCP28SS 5-499 PAGE 2323 LINE 119263
|
|
define pcodeop vrcp28ss_avx512er ;
|
|
:VRCP28SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xCB; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vrcp28ss_avx512er( evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VREDUCEPD 5-501 PAGE 2325 LINE 119356
|
|
define pcodeop vreducepd_avx512vl ;
|
|
:VREDUCEPD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x56; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vreducepd_avx512vl( XmmReg2_m128_m64bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VREDUCEPD 5-501 PAGE 2325 LINE 119360
|
|
:VREDUCEPD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x56; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vreducepd_avx512vl( YmmReg2_m256_m64bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VREDUCEPD 5-501 PAGE 2325 LINE 119364
|
|
define pcodeop vreducepd_avx512dq ;
|
|
:VREDUCEPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x56; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vreducepd_avx512dq( ZmmReg2_m512_m64bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VREDUCESD 5-504 PAGE 2328 LINE 119510
|
|
define pcodeop vreducesd_avx512dq ;
|
|
:VREDUCESD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vreducesd_avx512dq( evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VREDUCEPS 5-506 PAGE 2330 LINE 119605
|
|
define pcodeop vreduceps_avx512vl ;
|
|
:VREDUCEPS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x56; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vreduceps_avx512vl( XmmReg2_m128_m32bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VREDUCEPS 5-506 PAGE 2330 LINE 119609
|
|
:VREDUCEPS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x56; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vreduceps_avx512vl( YmmReg2_m256_m32bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VREDUCEPS 5-506 PAGE 2330 LINE 119613
|
|
define pcodeop vreduceps_avx512dq ;
|
|
:VREDUCEPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x56; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vreduceps_avx512dq( ZmmReg2_m512_m32bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VREDUCESS 5-508 PAGE 2332 LINE 119719
|
|
define pcodeop vreducess_avx512dq ;
|
|
:VREDUCESS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vreducess_avx512dq( evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VRNDSCALEPD 5-510 PAGE 2334 LINE 119814
|
|
define pcodeop vrndscalepd_avx512vl ;
|
|
:VRNDSCALEPD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x09; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vrndscalepd_avx512vl( XmmReg2_m128_m64bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VRNDSCALEPD 5-510 PAGE 2334 LINE 119818
|
|
:VRNDSCALEPD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x09; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vrndscalepd_avx512vl( YmmReg2_m256_m64bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VRNDSCALEPD 5-510 PAGE 2334 LINE 119822
|
|
define pcodeop vrndscalepd_avx512f ;
|
|
:VRNDSCALEPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x09; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vrndscalepd_avx512f( ZmmReg2_m512_m64bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VRNDSCALESD 5-514 PAGE 2338 LINE 119998
|
|
define pcodeop vrndscalesd_avx512f ;
|
|
:VRNDSCALESD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_XmmReg; byte=0x0B; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64; imm8
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vrndscalesd_avx512f( evexV5_XmmReg, XmmReg2_m64, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VRNDSCALEPS 5-516 PAGE 2340 LINE 120116
|
|
define pcodeop vrndscaleps_avx512vl ;
|
|
:VRNDSCALEPS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x08; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vrndscaleps_avx512vl( XmmReg2_m128_m32bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VRNDSCALEPS 5-516 PAGE 2340 LINE 120120
|
|
:VRNDSCALEPS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x08; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vrndscaleps_avx512vl( YmmReg2_m256_m32bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VRNDSCALEPS 5-516 PAGE 2340 LINE 120124
|
|
define pcodeop vrndscaleps_avx512f ;
|
|
:VRNDSCALEPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x08; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vrndscaleps_avx512f( ZmmReg2_m512_m32bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VRNDSCALESS 5-519 PAGE 2343 LINE 120263
|
|
define pcodeop vrndscaless_avx512f ;
|
|
:VRNDSCALESS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_XmmReg; byte=0x0A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vrndscaless_avx512f( evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VRSQRT14PD 5-521 PAGE 2345 LINE 120381
|
|
define pcodeop vrsqrt14pd_avx512vl ;
|
|
:VRSQRT14PD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4E; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vrsqrt14pd_avx512vl( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VRSQRT14PD 5-521 PAGE 2345 LINE 120385
|
|
:VRSQRT14PD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4E; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vrsqrt14pd_avx512vl( YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VRSQRT14PD 5-521 PAGE 2345 LINE 120389
|
|
define pcodeop vrsqrt14pd_avx512f ;
|
|
:VRSQRT14PD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4E; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vrsqrt14pd_avx512f( ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VRSQRT14SD 5-523 PAGE 2347 LINE 120491
|
|
define pcodeop vrsqrt14sd_avx512f ;
|
|
:VRSQRT14SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x4F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vrsqrt14sd_avx512f( evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VRSQRT14PS 5-525 PAGE 2349 LINE 120578
|
|
define pcodeop vrsqrt14ps_avx512vl ;
|
|
:VRSQRT14PS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4E; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vrsqrt14ps_avx512vl( XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VRSQRT14PS 5-525 PAGE 2349 LINE 120582
|
|
:VRSQRT14PS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4E; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vrsqrt14ps_avx512vl( YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VRSQRT14PS 5-525 PAGE 2349 LINE 120586
|
|
define pcodeop vrsqrt14ps_avx512f ;
|
|
:VRSQRT14PS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4E; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vrsqrt14ps_avx512f( ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VRSQRT14SS 5-527 PAGE 2351 LINE 120690
|
|
define pcodeop vrsqrt14ss_avx512f ;
|
|
:VRSQRT14SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x4F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vrsqrt14ss_avx512f( evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VRSQRT28PD 5-529 PAGE 2353 LINE 120778
|
|
define pcodeop vrsqrt28pd_avx512er ;
|
|
:VRSQRT28PD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xCC; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vrsqrt28pd_avx512er( ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VRSQRT28SD 5-531 PAGE 2355 LINE 120869
|
|
define pcodeop vrsqrt28sd_avx512er ;
|
|
:VRSQRT28SD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0xCD; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vrsqrt28sd_avx512er( evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VRSQRT28PS 5-533 PAGE 2357 LINE 120959
|
|
define pcodeop vrsqrt28ps_avx512er ;
|
|
:VRSQRT28PS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xCC; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vrsqrt28ps_avx512er( ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VRSQRT28SS 5-535 PAGE 2359 LINE 121051
|
|
define pcodeop vrsqrt28ss_avx512er ;
|
|
:VRSQRT28SS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0xCD; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vrsqrt28ss_avx512er( evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VSCALEFPD 5-537 PAGE 2361 LINE 121140
|
|
define pcodeop vscalefpd_avx512vl ;
|
|
:VSCALEFPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x2C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vscalefpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VSCALEFPD 5-537 PAGE 2361 LINE 121143
|
|
:VSCALEFPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x2C; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vscalefpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VSCALEFPD 5-537 PAGE 2361 LINE 121146
|
|
define pcodeop vscalefpd_avx512f ;
|
|
:VSCALEFPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x2C; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vscalefpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VSCALEFSD 5-540 PAGE 2364 LINE 121269
|
|
define pcodeop vscalefsd_avx512f ;
|
|
:VSCALEFSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x2D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vscalefsd_avx512f( evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VSCALEFPS 5-542 PAGE 2366 LINE 121355
|
|
define pcodeop vscalefps_avx512vl ;
|
|
:VSCALEFPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x2C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vscalefps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VSCALEFPS 5-542 PAGE 2366 LINE 121358
|
|
:VSCALEFPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x2C; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vscalefps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VSCALEFPS 5-542 PAGE 2366 LINE 121361
|
|
define pcodeop vscalefps_avx512f ;
|
|
:VSCALEFPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x2C; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vscalefps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VSCALEFSS 5-544 PAGE 2368 LINE 121470
|
|
define pcodeop vscalefss_avx512f ;
|
|
:VSCALEFSS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x2D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
XmmResult = vscalefss_avx512f( evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121559
|
|
define pcodeop vscatterdps_avx512vl ;
|
|
:VSCATTERDPS x_vm32x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA2; XmmReg1 ... & x_vm32x
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vscatterdps_avx512vl( x_vm32x, XmmOpMask, XmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121561
|
|
:VSCATTERDPS y_vm32y^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0xA2; YmmReg1 ... & y_vm32y
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vscatterdps_avx512vl( y_vm32y, YmmOpMask, YmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121563
|
|
define pcodeop vscatterdps_avx512f ;
|
|
:VSCATTERDPS z_vm32z^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xA2; ZmmReg1 ... & z_vm32z
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vscatterdps_avx512f( z_vm32z, ZmmOpMask, ZmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121565
|
|
define pcodeop vscatterdpd_avx512vl ;
|
|
:VSCATTERDPD x_vm32x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xA2; XmmReg1 ... & x_vm32x
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vscatterdpd_avx512vl( x_vm32x, XmmOpMask, XmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121567
|
|
:VSCATTERDPD y_vm32y^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xA2; YmmReg1 ... & y_vm32y
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vscatterdpd_avx512vl( y_vm32y, YmmOpMask, YmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121569
|
|
define pcodeop vscatterdpd_avx512f ;
|
|
:VSCATTERDPD z_vm32z^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xA2; ZmmReg1 ... & z_vm32z
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vscatterdpd_avx512f( z_vm32z, ZmmOpMask, ZmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
@ifdef IA64
|
|
# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121571
|
|
define pcodeop vscatterqps_avx512vl ;
|
|
:VSCATTERQPS q_vm64x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA3; XmmReg1 ... & q_vm64x
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vscatterqps_avx512vl( q_vm64x, XmmOpMask, XmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121573
|
|
:VSCATTERQPS q_vm64y^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA3; XmmReg1 ... & q_vm64y
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vscatterqps_avx512vl( q_vm64y, XmmOpMask, XmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121575
|
|
define pcodeop vscatterqps_avx512f ;
|
|
:VSCATTERQPS q_vm64z^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0xA3; YmmReg1 ... & q_vm64z
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vscatterqps_avx512f( q_vm64z, YmmOpMask, YmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121577
|
|
define pcodeop vscatterqpd_avx512vl ;
|
|
:VSCATTERQPD x_vm64x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xA3; XmmReg1 ... & x_vm64x
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vscatterqpd_avx512vl( x_vm64x, XmmOpMask, XmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121579
|
|
:VSCATTERQPD y_vm64y^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xA3; YmmReg1 ... & y_vm64y
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vscatterqpd_avx512vl( y_vm64y, YmmOpMask, YmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
@endif
|
|
|
|
@ifdef IA64
|
|
# VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121581
|
|
define pcodeop vscatterqpd_avx512f ;
|
|
:VSCATTERQPD z_vm64z^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xA3; ZmmReg1 ... & z_vm64z
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vscatterqpd_avx512f( z_vm64z, ZmmOpMask, ZmmReg1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
@endif
|
|
|
|
# VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD 5-551 PAGE 2375 LINE 121759
|
|
define pcodeop vscatterpf0dps_avx512pf ;
|
|
:VSCATTERPF0DPS z_vm32z^ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xC6; reg_opcode=5 ... & z_vm32z
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vscatterpf0dps_avx512pf( z_vm32z , ZmmOpMask);
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
@ifdef IA64
|
|
# VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD 5-551 PAGE 2375 LINE 121762
|
|
define pcodeop vscatterpf0qps_avx512pf ;
|
|
:VSCATTERPF0QPS z_vm64z^ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xC7; reg_opcode=5 ... & z_vm64z
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vscatterpf0qps_avx512pf( z_vm64z, ZmmOpMask );
|
|
# TODO missing destination or side effects
|
|
}
|
|
@endif
|
|
|
|
# VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD 5-551 PAGE 2375 LINE 121765
|
|
define pcodeop vscatterpf0dpd_avx512pf ;
|
|
:VSCATTERPF0DPD y_vm32y^YmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xC6; reg_opcode=5 ... & y_vm32y
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vscatterpf0dpd_avx512pf( y_vm32y, YmmOpMask );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
@ifdef IA64
|
|
# VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD 5-551 PAGE 2375 LINE 121768
|
|
define pcodeop vscatterpf0qpd_avx512pf ;
|
|
:VSCATTERPF0QPD z_vm64z^ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xC7; reg_opcode=5 ... & z_vm64z
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vscatterpf0qpd_avx512pf( z_vm64z, ZmmOpMask );
|
|
# TODO missing destination or side effects
|
|
}
|
|
@endif
|
|
|
|
# VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD 5-553 PAGE 2377 LINE 121877
|
|
define pcodeop vscatterpf1dps_avx512pf ;
|
|
:VSCATTERPF1DPS z_vm32z^ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xC6; reg_opcode=6 ... & z_vm32z
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vscatterpf1dps_avx512pf( z_vm32z, ZmmOpMask );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
@ifdef IA64
|
|
# VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD 5-553 PAGE 2377 LINE 121880
|
|
define pcodeop vscatterpf1qps_avx512pf ;
|
|
:VSCATTERPF1QPS z_vm64z^ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xC7; reg_opcode=6 ... & z_vm64z
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vscatterpf1qps_avx512pf( z_vm64z, ZmmOpMask );
|
|
# TODO missing destination or side effects
|
|
}
|
|
@endif
|
|
|
|
# VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD 5-553 PAGE 2377 LINE 121883
|
|
define pcodeop vscatterpf1dpd_avx512pf ;
|
|
:VSCATTERPF1DPD y_vm32y^YmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xC6; reg_opcode=6 ... & y_vm32y
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vscatterpf1dpd_avx512pf( y_vm32y, YmmOpMask );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
@ifdef IA64
|
|
# VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD 5-553 PAGE 2377 LINE 121886
|
|
define pcodeop vscatterpf1qpd_avx512pf ;
|
|
:VSCATTERPF1QPD z_vm64z^ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xC7; reg_opcode=6 ... & z_vm64z
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
|
|
{
|
|
vscatterpf1qpd_avx512pf( z_vm64z, ZmmOpMask );
|
|
# TODO missing destination or side effects
|
|
}
|
|
@endif
|
|
|
|
# VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 121994
|
|
define pcodeop vshuff32x4_avx512vl ;
|
|
:VSHUFF32X4 YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_YmmReg; byte=0x23; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vshuff32x4_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 121998
|
|
define pcodeop vshuff32x4_avx512f ;
|
|
:VSHUFF32x4 ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x23; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vshuff32x4_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122002
|
|
define pcodeop vshuff64x2_avx512vl ;
|
|
:VSHUFF64X2 YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_YmmReg; byte=0x23; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vshuff64x2_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122006
|
|
define pcodeop vshuff64x2_avx512f ;
|
|
:VSHUFF64x2 ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x23; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vshuff64x2_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122010
|
|
define pcodeop vshufi32x4_avx512vl ;
|
|
:VSHUFI32X4 YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_YmmReg; byte=0x43; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vshufi32x4_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122013
|
|
define pcodeop vshufi32x4_avx512f ;
|
|
:VSHUFI32x4 ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x43; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vshufi32x4_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122016
|
|
define pcodeop vshufi64x2_avx512vl ;
|
|
:VSHUFI64X2 YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_YmmReg; byte=0x43; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vshufi64x2_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122019
|
|
define pcodeop vshufi64x2_avx512f ;
|
|
:VSHUFI64x2 ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x43; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vshufi64x2_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# XORPD 5-596 PAGE 2420 LINE 123834
|
|
define pcodeop vxorpd_avx512vl ;
|
|
:VXORPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vxorpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# XORPD 5-596 PAGE 2420 LINE 123837
|
|
:VXORPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x57; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vxorpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# XORPD 5-596 PAGE 2420 LINE 123840
|
|
define pcodeop vxorpd_avx512dq ;
|
|
:VXORPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x57; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vxorpd_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# XORPS 5-599 PAGE 2423 LINE 123959
|
|
define pcodeop vxorps_avx512vl ;
|
|
:VXORPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
XmmResult = vxorps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# XORPS 5-599 PAGE 2423 LINE 123962
|
|
:VXORPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x57; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
YmmResult = vxorps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# XORPS 5-599 PAGE 2423 LINE 123965
|
|
define pcodeop vxorps_avx512dq ;
|
|
:VXORPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x57; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
|
|
{
|
|
ZmmResult = vxorps_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# AVX512 BMI, FMA, and FP16 updates
|
|
|
|
# AESDEC 3-51 PAGE 621 LINE 35875
|
|
define pcodeop vaesdec_vaes ;
|
|
:VAESDEC XmmReg1, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_XmmReg; byte=0xDE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
local tmp:16 = vaesdec_vaes( evexV5_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# AESDEC 3-51 PAGE 621 LINE 35879
|
|
:VAESDEC YmmReg1, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_YmmReg; byte=0xDE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
local tmp:32 = vaesdec_vaes( evexV5_YmmReg, YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# AESDEC 3-51 PAGE 621 LINE 35883
|
|
:VAESDEC ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xDE; ZmmReg1 ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
ZmmReg1 = vaesdec_vaes( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
}
|
|
|
|
# AESDECLAST 3-57 PAGE 627 LINE 36144
|
|
define pcodeop vaesdeclast_vaes ;
|
|
:VAESDECLAST XmmReg1, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_XmmReg; byte=0xDF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
local tmp:16 = vaesdeclast_vaes( evexV5_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# AESDECLAST 3-57 PAGE 627 LINE 36148
|
|
:VAESDECLAST YmmReg1, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_YmmReg; byte=0xDF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
local tmp:32 = vaesdeclast_vaes( evexV5_YmmReg, YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# AESDECLAST 3-57 PAGE 627 LINE 36152
|
|
:VAESDECLAST ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xDF; ZmmReg1 ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
ZmmReg1 = vaesdeclast_vaes( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
}
|
|
|
|
# AESENC 3-63 PAGE 633 LINE 36420
|
|
define pcodeop vaesenc_vaes ;
|
|
:VAESENC XmmReg1, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_XmmReg; byte=0xDC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
local tmp:16 = vaesenc_vaes( evexV5_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# AESENC 3-63 PAGE 633 LINE 36423
|
|
:VAESENC YmmReg1, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_YmmReg; byte=0xDC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
local tmp:32 = vaesenc_vaes( evexV5_YmmReg, YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# AESENC 3-63 PAGE 633 LINE 36426
|
|
:VAESENC ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xDC; ZmmReg1 ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
ZmmReg1 = vaesenc_vaes( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
}
|
|
|
|
# AESENCLAST 3-69 PAGE 639 LINE 36687
|
|
define pcodeop vaesenclast_vaes ;
|
|
:VAESENCLAST XmmReg1, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_XmmReg; byte=0xDD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
local tmp:16 = vaesenclast_vaes( evexV5_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# AESENCLAST 3-69 PAGE 639 LINE 36691
|
|
:VAESENCLAST YmmReg1, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_YmmReg; byte=0xDD; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
local tmp:32 = vaesenclast_vaes( evexV5_YmmReg, YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# AESENCLAST 3-69 PAGE 639 LINE 36695
|
|
:VAESENCLAST ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xDD; ZmmReg1 ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
ZmmReg1 = vaesenclast_vaes( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
}
|
|
|
|
# PCLMULQDQ 4-242 PAGE 1362 LINE 76037
|
|
define pcodeop vpclmulqdq_vpclmulqdq ;
|
|
:VPCLMULQDQ XmmReg1, evexV5_XmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_XmmReg; byte=0x44; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
local tmp:16 = vpclmulqdq_vpclmulqdq( evexV5_XmmReg, XmmReg2_m128, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PCLMULQDQ 4-242 PAGE 1362 LINE 76042
|
|
:VPCLMULQDQ YmmReg1, evexV5_YmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_YmmReg; byte=0x44; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
local tmp:32 = vpclmulqdq_vpclmulqdq( evexV5_YmmReg, YmmReg2_m256, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PCLMULQDQ 4-242 PAGE 1362 LINE 76047
|
|
:VPCLMULQDQ ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x44; ZmmReg1 ... & ZmmReg2_m512; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
ZmmReg1 = vpclmulqdq_vpclmulqdq( evexV5_ZmmReg, ZmmReg2_m512, imm8:1 );
|
|
}
|
|
|
|
# VADDPH 5-5 PAGE 1829 LINE 101735
|
|
define pcodeop vaddph_avx512fp16 ;
|
|
:VADDPH XmmReg1 XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vaddph_avx512fp16( evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VADDPH 5-5 PAGE 1829 LINE 101738
|
|
:VADDPH YmmReg1 YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x58; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vaddph_avx512fp16( evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VADDPH 5-5 PAGE 1829 LINE 101741
|
|
:VADDPH ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x58; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vaddph_avx512fp16( evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VADDSH 5-7 PAGE 1831 LINE 101824
|
|
define pcodeop vaddsh_avx512fp16 ;
|
|
:VADDSH XmmReg1 XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vaddsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
VCMPPH_mon: "VCMPEQPH" is imm8=0x0 { }
|
|
VCMPPH_op: "" is imm8=0x0 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPLTPH" is imm8=0x1 { }
|
|
VCMPPH_op: "" is imm8=0x1 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPLEPH" is imm8=0x2 { }
|
|
VCMPPH_op: "" is imm8=0x2 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPUNORDPH" is imm8=0x3 { }
|
|
VCMPPH_op: "" is imm8=0x3 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPNEQPH" is imm8=0x4 { }
|
|
VCMPPH_op: "" is imm8=0x4 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPNLTPH" is imm8=0x5 { }
|
|
VCMPPH_op: "" is imm8=0x5 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPNLEPH" is imm8=0x6 { }
|
|
VCMPPH_op: "" is imm8=0x6 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPORDPH" is imm8=0x7 { }
|
|
VCMPPH_op: "" is imm8=0x7 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPEQ_UQPH" is imm8=0x8 { }
|
|
VCMPPH_op: "" is imm8=0x8 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPNGEPH" is imm8=0x9 { }
|
|
VCMPPH_op: "" is imm8=0x9 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPNGTPH" is imm8=0xa { }
|
|
VCMPPH_op: "" is imm8=0xa & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPFALSEPH" is imm8=0xb { }
|
|
VCMPPH_op: "" is imm8=0xb & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPNEQ_OQPH" is imm8=0xc { }
|
|
VCMPPH_op: "" is imm8=0xc & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPGEPH" is imm8=0xd { }
|
|
VCMPPH_op: "" is imm8=0xd & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPGTPH" is imm8=0xe { }
|
|
VCMPPH_op: "" is imm8=0xe & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPTRUEPH" is imm8=0xf { }
|
|
VCMPPH_op: "" is imm8=0xf & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPEQ_OSPH" is imm8=0x10 { }
|
|
VCMPPH_op: "" is imm8=0x10 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPLT_OQPH" is imm8=0x11 { }
|
|
VCMPPH_op: "" is imm8=0x11 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPLE_OQPH" is imm8=0x12 { }
|
|
VCMPPH_op: "" is imm8=0x12 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPUNORD_SPH" is imm8=0x13 { }
|
|
VCMPPH_op: "" is imm8=0x13 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPNEQ_USPH" is imm8=0x14 { }
|
|
VCMPPH_op: "" is imm8=0x14 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPNLT_UQPH" is imm8=0x15 { }
|
|
VCMPPH_op: "" is imm8=0x15 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPNLE_UQPH" is imm8=0x16 { }
|
|
VCMPPH_op: "" is imm8=0x16 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPORD_SPH" is imm8=0x17 { }
|
|
VCMPPH_op: "" is imm8=0x17 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPEQ_USPH" is imm8=0x18 { }
|
|
VCMPPH_op: "" is imm8=0x18 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPNGE_UQPH" is imm8=0x19 { }
|
|
VCMPPH_op: "" is imm8=0x19 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPNGT_UQPH" is imm8=0x1a { }
|
|
VCMPPH_op: "" is imm8=0x1a & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPFALSE_OSPH" is imm8=0x1b { }
|
|
VCMPPH_op: "" is imm8=0x1b & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPNEQ_OSPH" is imm8=0x1c { }
|
|
VCMPPH_op: "" is imm8=0x1c & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPGE_OQPH" is imm8=0x1d { }
|
|
VCMPPH_op: "" is imm8=0x1d & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPGT_OQPH" is imm8=0x1e { }
|
|
VCMPPH_op: "" is imm8=0x1e & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPTRUE_USPH" is imm8=0x1f { }
|
|
VCMPPH_op: "" is imm8=0x1f & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPPH_mon: "VCMPPH" is imm8 { }
|
|
VCMPPH_op: ", "^imm8 is imm8 { export *[const]:1 imm8; }
|
|
|
|
define pcodeop vcmpph_avx512fp16;
|
|
:^VCMPPH_mon KReg_reg^XmmOpMask, evexV5_XmmReg, XmmReg2_m128_m16bcst^VCMPPH_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xC2; KReg_reg ... & XmmReg2_m128_m16bcst; VCMPPH_mon & VCMPPH_op
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
KReg_reg = vcmpph_avx512fp16( evexV5_XmmReg, XmmReg2_m128_m16bcst, XmmOpMask, VCMPPH_op );
|
|
}
|
|
|
|
# VCMPPH 5-21 PAGE 1845 LINE 102586
|
|
:^VCMPPH_mon KReg_reg^YmmOpMask, evexV5_YmmReg, YmmReg2_m256_m16bcst^VCMPPH_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask & evexV5_YmmReg; byte=0xC2; KReg_reg ... & YmmReg2_m256_m16bcst; VCMPPH_mon & VCMPPH_op
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
|
|
KReg_reg = vcmpph_avx512fp16( evexV5_YmmReg, YmmReg2_m256_m16bcst, YmmOpMask, VCMPPH_op );
|
|
}
|
|
|
|
# VCMPPH 5-21 PAGE 1845 LINE 102590
|
|
:^VCMPPH_mon KReg_reg^ZmmOpMask, evexV5_ZmmReg, ZmmReg2_m512_m16bcst^VCMPPH_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & ZmmOpMask & evexV5_ZmmReg; byte=0xC2; KReg_reg ... & ZmmReg2_m512_m16bcst; VCMPPH_mon & VCMPPH_op
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
KReg_reg = vcmpph_avx512fp16( evexV5_ZmmReg, ZmmReg2_m512_m16bcst, ZmmOpMask, VCMPPH_op );
|
|
}
|
|
|
|
VCMPSH_mon: "VCMPEQSH" is imm8=0x0 { }
|
|
VCMPSH_op: "" is imm8=0x0 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPLTSH" is imm8=0x1 { }
|
|
VCMPSH_op: "" is imm8=0x1 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPLESH" is imm8=0x2 { }
|
|
VCMPSH_op: "" is imm8=0x2 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPUNORDSH" is imm8=0x3 { }
|
|
VCMPSH_op: "" is imm8=0x3 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPNEQSH" is imm8=0x4 { }
|
|
VCMPSH_op: "" is imm8=0x4 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPNLTSH" is imm8=0x5 { }
|
|
VCMPSH_op: "" is imm8=0x5 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPNLESH" is imm8=0x6 { }
|
|
VCMPSH_op: "" is imm8=0x6 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPORDSH" is imm8=0x7 { }
|
|
VCMPSH_op: "" is imm8=0x7 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPEQ_UQSH" is imm8=0x8 { }
|
|
VCMPSH_op: "" is imm8=0x8 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPNGESH" is imm8=0x9 { }
|
|
VCMPSH_op: "" is imm8=0x9 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPNGTSH" is imm8=0xa { }
|
|
VCMPSH_op: "" is imm8=0xa & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPFALSESH" is imm8=0xb { }
|
|
VCMPSH_op: "" is imm8=0xb & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPNEQ_OQSH" is imm8=0xc { }
|
|
VCMPSH_op: "" is imm8=0xc & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPGESH" is imm8=0xd { }
|
|
VCMPSH_op: "" is imm8=0xd & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPGTSH" is imm8=0xe { }
|
|
VCMPSH_op: "" is imm8=0xe & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPTRUESH" is imm8=0xf { }
|
|
VCMPSH_op: "" is imm8=0xf & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPEQ_OSSH" is imm8=0x10 { }
|
|
VCMPSH_op: "" is imm8=0x10 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPLT_OQSH" is imm8=0x11 { }
|
|
VCMPSH_op: "" is imm8=0x11 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPLE_OQSH" is imm8=0x12 { }
|
|
VCMPSH_op: "" is imm8=0x12 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPUNORD_SSH" is imm8=0x13 { }
|
|
VCMPSH_op: "" is imm8=0x13 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPNEQ_USSH" is imm8=0x14 { }
|
|
VCMPSH_op: "" is imm8=0x14 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPNLT_UQSH" is imm8=0x15 { }
|
|
VCMPSH_op: "" is imm8=0x15 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPNLE_UQSH" is imm8=0x16 { }
|
|
VCMPSH_op: "" is imm8=0x16 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPORD_SSH" is imm8=0x17 { }
|
|
VCMPSH_op: "" is imm8=0x17 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPEQ_USSH" is imm8=0x18 { }
|
|
VCMPSH_op: "" is imm8=0x18 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPNGE_UQSH" is imm8=0x19 { }
|
|
VCMPSH_op: "" is imm8=0x19 & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPNGT_UQSH" is imm8=0x1a { }
|
|
VCMPSH_op: "" is imm8=0x1a & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPFALSE_OSSH" is imm8=0x1b { }
|
|
VCMPSH_op: "" is imm8=0x1b & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPNEQ_OSSH" is imm8=0x1c { }
|
|
VCMPSH_op: "" is imm8=0x1c & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPGE_OQSH" is imm8=0x1d { }
|
|
VCMPSH_op: "" is imm8=0x1d & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPGT_OQSH" is imm8=0x1e { }
|
|
VCMPSH_op: "" is imm8=0x1e & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPTRUE_USSH" is imm8=0x1f { }
|
|
VCMPSH_op: "" is imm8=0x1f & imm8_val { export *[const]:1 imm8_val; }
|
|
VCMPSH_mon: "VCMPSH" is imm8 { }
|
|
VCMPSH_op: ", "^imm8 is imm8 { export *[const]:1 imm8; }
|
|
|
|
# VCMPSH 5-23 PAGE 1847 LINE 102692
|
|
define pcodeop vcmpsh_avx512fp16 ;
|
|
:^VCMPSH_mon KReg_reg^XmmOpMask, evexV5_XmmReg, XmmReg2_m16^VCMPSH_op is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xC2; KReg_reg ... & XmmReg2_m16; VCMPSH_mon & VCMPSH_op
|
|
{
|
|
KReg_reg = vcmpsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16, XmmOpMask, VCMPSH_op );
|
|
}
|
|
|
|
# VCOMISH 5-25 PAGE 1849 LINE 102783
|
|
define pcodeop vcomish_avx512fp16 ;
|
|
:VCOMISH XmmReg1, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0); byte=0x2F; XmmReg1 ... & XmmReg2_m16
|
|
{
|
|
vcomish_avx512fp16( XmmReg1, XmmReg2_m16 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# VCVTDQ2PH 5-31 PAGE 1855 LINE 103058
|
|
define pcodeop vcvtdq2ph_avx512fp16 ;
|
|
:VCVTDQ2PH XmmReg1^XmmOpMask16, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x5B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvtdq2ph_avx512fp16( XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult[0,64]);
|
|
}
|
|
|
|
# VCVTDQ2PH 5-31 PAGE 1855 LINE 103062
|
|
:VCVTDQ2PH XmmReg1^XmmOpMask16, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x5B; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvtdq2ph_avx512fp16( YmmReg2_m256_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTDQ2PH 5-31 PAGE 1855 LINE 103066
|
|
:VCVTDQ2PH YmmReg1^YmmOpMask16, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16; byte=0x5B; (YmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vcvtdq2ph_avx512fp16( ZmmReg2_m512_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTNE2PS2BF16 5-33 PAGE 1857 LINE 103147
|
|
define pcodeop vcvtne2ps2bf16_avx512vl ;
|
|
:VCVTNE2PS2BF16 XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x72; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvtne2ps2bf16_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTNE2PS2BF16 5-33 PAGE 1857 LINE 103150
|
|
:VCVTNE2PS2BF16 YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x72; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vcvtne2ps2bf16_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTNE2PS2BF16 5-33 PAGE 1857 LINE 103153
|
|
define pcodeop vcvtne2ps2bf16_avx512f ;
|
|
:VCVTNE2PS2BF16 ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x72; ZmmReg1 ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vcvtne2ps2bf16_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTNEPS2BF16 5-35 PAGE 1859 LINE 103231
|
|
define pcodeop vcvtneps2bf16_avx512vl ;
|
|
:VCVTNEPS2BF16 XmmReg1^XmmOpMask16, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x72; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvtneps2bf16_avx512vl( XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult[0,64]);
|
|
}
|
|
|
|
# VCVTNEPS2BF16 5-35 PAGE 1859 LINE 103234
|
|
:VCVTNEPS2BF16 XmmReg1^XmmOpMask16, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x72; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvtneps2bf16_avx512vl( YmmReg2_m256_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTNEPS2BF16 5-35 PAGE 1859 LINE 103237
|
|
define pcodeop vcvtneps2bf16_avx512f ;
|
|
:VCVTNEPS2BF16 YmmReg1^YmmOpMask16, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x72; (YmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vcvtneps2bf16_avx512f( ZmmReg2_m512_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTPD2PH 5-37 PAGE 1861 LINE 103327
|
|
define pcodeop vcvtpd2ph_avx512fp16 ;
|
|
:VCVTPD2PH XmmReg1^XmmOpMask16, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W1) & XmmOpMask16; byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvtpd2ph_avx512fp16( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult[0,32]);
|
|
}
|
|
|
|
# VCVTPD2PH 5-37 PAGE 1861 LINE 103331
|
|
:VCVTPD2PH XmmReg1^XmmOpMask16, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W1) & XmmOpMask16; byte=0x5A; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvtpd2ph_avx512fp16( YmmReg2_m256_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult[0,64]);
|
|
}
|
|
|
|
# VCVTPD2PH 5-37 PAGE 1861 LINE 103335
|
|
:VCVTPD2PH XmmReg1^XmmOpMask16, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W1) & XmmOpMask16; byte=0x5A; (XmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvtpd2ph_avx512fp16( ZmmReg2_m512_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTPH2DQ 5-45 PAGE 1869 LINE 103774
|
|
define pcodeop vcvtph2dq_avx512fp16 ;
|
|
:VCVTPH2DQ XmmReg1^XmmOpMask32, XmmReg2_m64_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask32; byte=0x5B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64_m16bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)
|
|
{
|
|
XmmResult = vcvtph2dq_avx512fp16( XmmReg2_m64_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTPH2DQ 5-45 PAGE 1869 LINE 103778
|
|
:VCVTPH2DQ YmmReg1^YmmOpMask32, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask32; byte=0x5B; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)
|
|
{
|
|
YmmResult = vcvtph2dq_avx512fp16( XmmReg2_m128_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTPH2DQ 5-45 PAGE 1869 LINE 103782
|
|
:VCVTPH2DQ ZmmReg1^ZmmOpMask32, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask32; byte=0x5B; ZmmReg1 ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)
|
|
{
|
|
ZmmResult = vcvtph2dq_avx512fp16( YmmReg2_m256_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTPH2PD 5-47 PAGE 1871 LINE 103861
|
|
define pcodeop vcvtph2pd_avx512fp16 ;
|
|
:VCVTPH2PD XmmReg1^XmmOpMask64, XmmReg2_m32_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask64; byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32_m16bcst
|
|
{
|
|
XmmResult = vcvtph2pd_avx512fp16( XmmReg2_m32_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTPH2PD 5-47 PAGE 1871 LINE 103864
|
|
:VCVTPH2PD YmmReg1^YmmOpMask64, XmmReg2_m64_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask64; byte=0x5A; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64_m16bcst
|
|
{
|
|
YmmResult = vcvtph2pd_avx512fp16( XmmReg2_m64_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTPH2PD 5-47 PAGE 1871 LINE 103867
|
|
:VCVTPH2PD ZmmReg1^ZmmOpMask64, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask64; byte=0x5A; ZmmReg1 ... & XmmReg2_m128_m16bcst
|
|
{
|
|
ZmmResult = vcvtph2pd_avx512fp16( XmmReg2_m128_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTPH2PS/VCVTPH2PSX 5-49 PAGE 1873 LINE 103953
|
|
define pcodeop vcvtph2psx_avx512fp16 ;
|
|
:VCVTPH2PSX XmmReg1^XmmOpMask32, XmmReg2_m64_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask32; byte=0x13; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64_m16bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)
|
|
{
|
|
XmmResult = vcvtph2psx_avx512fp16( XmmReg2_m64_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTPH2PS/VCVTPH2PSX 5-49 PAGE 1873 LINE 103957
|
|
:VCVTPH2PSX YmmReg1^YmmOpMask32, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask32; byte=0x13; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)
|
|
{
|
|
YmmResult = vcvtph2psx_avx512fp16( XmmReg2_m128_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTPH2PS/VCVTPH2PSX 5-49 PAGE 1873 LINE 103961
|
|
:VCVTPH2PSX ZmmReg1^ZmmOpMask32, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask32; byte=0x13; ZmmReg1 ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)
|
|
{
|
|
ZmmResult = vcvtph2psx_avx512fp16( YmmReg2_m256_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTPH2QQ 5-53 PAGE 1877 LINE 104149
|
|
define pcodeop vcvtph2qq_avx512fp16 ;
|
|
:VCVTPH2QQ XmmReg1^XmmOpMask64, XmmReg2_m32_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask64; byte=0x7B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32_m16bcst
|
|
{
|
|
XmmResult = vcvtph2qq_avx512fp16( XmmReg2_m32_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTPH2QQ 5-53 PAGE 1877 LINE 104152
|
|
:VCVTPH2QQ YmmReg1^YmmOpMask64, XmmReg2_m64_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask64; byte=0x7B; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64_m16bcst
|
|
{
|
|
YmmResult = vcvtph2qq_avx512fp16( XmmReg2_m64_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTPH2QQ 5-53 PAGE 1877 LINE 104155
|
|
:VCVTPH2QQ ZmmReg1^ZmmOpMask64, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask64; byte=0x7B; ZmmReg1 ... & XmmReg2_m128_m16bcst
|
|
{
|
|
ZmmResult = vcvtph2qq_avx512fp16( XmmReg2_m128_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTPH2UDQ 5-55 PAGE 1879 LINE 104237
|
|
define pcodeop vcvtph2udq_avx512fp16 ;
|
|
:VCVTPH2UDQ XmmReg1^XmmOpMask32, XmmReg2_m64_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask32; byte=0x79; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64_m16bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)
|
|
{
|
|
XmmResult = vcvtph2udq_avx512fp16( XmmReg2_m64_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTPH2UDQ 5-55 PAGE 1879 LINE 104241
|
|
:VCVTPH2UDQ YmmReg1^YmmOpMask32, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask32; byte=0x79; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)
|
|
{
|
|
YmmResult = vcvtph2udq_avx512fp16( XmmReg2_m128_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTPH2UDQ 5-55 PAGE 1879 LINE 104245
|
|
:VCVTPH2UDQ ZmmReg1^ZmmOpMask32, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask32; byte=0x79; ZmmReg1 ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)
|
|
{
|
|
ZmmResult = vcvtph2udq_avx512fp16( YmmReg2_m256_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTPH2UQQ 5-57 PAGE 1881 LINE 104324
|
|
define pcodeop vcvtph2uqq_avx512fp16 ;
|
|
:VCVTPH2UQQ XmmReg1^XmmOpMask64, XmmReg2_m32_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask64; byte=0x79; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32_m16bcst
|
|
{
|
|
XmmResult = vcvtph2uqq_avx512fp16( XmmReg2_m32_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTPH2UQQ 5-57 PAGE 1881 LINE 104327
|
|
:VCVTPH2UQQ YmmReg1^YmmOpMask64, XmmReg2_m64_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask64; byte=0x79; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64_m16bcst
|
|
{
|
|
YmmResult = vcvtph2uqq_avx512fp16( XmmReg2_m64_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTPH2UQQ 5-57 PAGE 1881 LINE 104331
|
|
:VCVTPH2UQQ ZmmReg1^ZmmOpMask64, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask64; byte=0x79; ZmmReg1 ... & XmmReg2_m128_m16bcst
|
|
{
|
|
ZmmResult = vcvtph2uqq_avx512fp16( XmmReg2_m128_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTPH2UW 5-59 PAGE 1883 LINE 104412
|
|
define pcodeop vcvtph2uw_avx512fp16 ;
|
|
:VCVTPH2UW XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x7D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvtph2uw_avx512fp16( XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTPH2UW 5-59 PAGE 1883 LINE 104415
|
|
:VCVTPH2UW YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16; byte=0x7D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vcvtph2uw_avx512fp16( YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTPH2UW 5-59 PAGE 1883 LINE 104418
|
|
:VCVTPH2UW ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16; byte=0x7D; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vcvtph2uw_avx512fp16( ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTPH2W 5-61 PAGE 1885 LINE 104499
|
|
define pcodeop vcvtph2w_avx512fp16 ;
|
|
:VCVTPH2W XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x7D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvtph2w_avx512fp16( XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTPH2W 5-61 PAGE 1885 LINE 104502
|
|
:VCVTPH2W YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16; byte=0x7D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vcvtph2w_avx512fp16( YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTPH2W 5-61 PAGE 1885 LINE 104505
|
|
:VCVTPH2W ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16; byte=0x7D; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vcvtph2w_avx512fp16( ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
|
|
# VCVTPS2PHX 5-67 PAGE 1891 LINE 104781
|
|
define pcodeop vcvtps2phx_avx512fp16 ;
|
|
:VCVTPS2PHX XmmReg1^XmmOpMask16, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x1D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvtps2phx_avx512fp16( XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult[0,64]);
|
|
}
|
|
|
|
# VCVTPS2PHX 5-67 PAGE 1891 LINE 104785
|
|
:VCVTPS2PHX XmmReg1^XmmOpMask16, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x1D; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvtps2phx_avx512fp16( YmmReg2_m256_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTPS2PHX 5-67 PAGE 1891 LINE 104789
|
|
:VCVTPS2PHX YmmReg1^YmmOpMask16, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16; byte=0x1D; (YmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vcvtps2phx_avx512fp16( ZmmReg2_m512_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTQQ2PH 5-78 PAGE 1902 LINE 105354
|
|
define pcodeop vcvtqq2ph_avx512fp16 ;
|
|
:VCVTQQ2PH XmmReg1^XmmOpMask16, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W1) & XmmOpMask16; byte=0x5B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvtqq2ph_avx512fp16( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult[0,32]);
|
|
}
|
|
|
|
# VCVTQQ2PH 5-78 PAGE 1902 LINE 105358
|
|
:VCVTQQ2PH XmmReg1^XmmOpMask16, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W1) & XmmOpMask16; byte=0x5B; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvtqq2ph_avx512fp16( YmmReg2_m256_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult[0,64]);
|
|
}
|
|
|
|
# VCVTQQ2PH 5-78 PAGE 1902 LINE 105362
|
|
:VCVTQQ2PH XmmReg1^XmmOpMask16, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W1) & XmmOpMask16; byte=0x5B; (XmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvtqq2ph_avx512fp16( ZmmReg2_m512_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTSD2SH 5-82 PAGE 1906 LINE 105553
|
|
define pcodeop vcvtsd2sh_avx512fp16 ;
|
|
:VCVTSD2SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F2) & $(VEX_MAP5) & $(VEX_W1) & XmmOpMask & evexV5_XmmReg; byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
{
|
|
XmmResult = vcvtsd2sh_avx512fp16( evexV5_XmmReg, XmmReg2_m64 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTSH2SD 5-85 PAGE 1909 LINE 105683
|
|
define pcodeop vcvtsh2sd_avx512fp16 ;
|
|
:VCVTSH2SD XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vcvtsh2sd_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,64], XmmOpMask[0,1], XmmResult[0,64], XmmMask[0,64]);
|
|
XmmResult[64,64] = XmmReg1[16,64]; # DEST[127:64] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTSH2SI 5-86 PAGE 1910 LINE 105738
|
|
define pcodeop vcvtsh2si_avx512fp16 ;
|
|
:VCVTSH2SI Reg32, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0); byte=0x2D; (Reg32 & check_Reg32_dest) ... & XmmReg2_m16
|
|
{
|
|
Reg32 = vcvtsh2si_avx512fp16( XmmReg2_m16 );
|
|
build check_Reg32_dest;
|
|
}
|
|
|
|
# VCVTSH2SI 5-86 PAGE 1910 LINE 105740
|
|
@ifdef IA64
|
|
:VCVTSH2SI Reg64, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W1); byte=0x2D; Reg64 ... & XmmReg2_m16
|
|
{
|
|
Reg64 = vcvtsh2si_avx512fp16( XmmReg2_m16 );
|
|
}
|
|
@endif
|
|
|
|
# VCVTSH2SS 5-87 PAGE 1911 LINE 105796
|
|
define pcodeop vcvtsh2ss_avx512fp16 ;
|
|
:VCVTSH2SS XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_NONE) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x13; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vcvtsh2ss_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,32], XmmOpMask[0,1], XmmResult[0,32], XmmMask[0,32]);
|
|
XmmResult[32,96] = XmmReg1[32,96]; # DEST[127:32] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTSH2USI 5-88 PAGE 1912 LINE 105851
|
|
define pcodeop vcvtsh2usi_avx512fp16 ;
|
|
:VCVTSH2USI Reg32, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0); byte=0x79; (Reg32 & check_Reg32_dest) ... & XmmReg2_m16
|
|
{
|
|
Reg32 = vcvtsh2usi_avx512fp16( XmmReg2_m16 );
|
|
build check_Reg32_dest;
|
|
}
|
|
|
|
# VCVTSH2USI 5-88 PAGE 1912 LINE 105853
|
|
@ifdef IA64
|
|
:VCVTSH2USI Reg64, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W1); byte=0x79; Reg64 ... & XmmReg2_m16
|
|
{
|
|
Reg64 = vcvtsh2usi_avx512fp16( XmmReg2_m16 );
|
|
}
|
|
@endif
|
|
|
|
# VCVTSI2SH 5-89 PAGE 1913 LINE 105910
|
|
define pcodeop vcvtsi2sh_avx512fp16 ;
|
|
:VCVTSI2SH XmmReg1, evexV5_XmmReg, rm32 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & evexV5_XmmReg; byte=0x2A; (XmmReg1 & ZmmReg1) ... & rm32
|
|
{
|
|
local tmp:16 = vcvtsi2sh_avx512fp16( evexV5_XmmReg, rm32 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VCVTSI2SH 5-89 PAGE 1913 LINE 105914
|
|
@ifdef IA64
|
|
:VCVTSI2SH XmmReg1, evexV5_XmmReg, rm64 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W1) & evexV5_XmmReg; byte=0x2A; (XmmReg1 & ZmmReg1) ... & rm64
|
|
{
|
|
local tmp:16 = vcvtsi2sh_avx512fp16( evexV5_XmmReg, rm64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
@endif
|
|
|
|
# VCVTSS2SH 5-91 PAGE 1915 LINE 105984
|
|
define pcodeop vcvtss2sh_avx512fp16 ;
|
|
:VCVTSS2SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x1D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
|
|
{
|
|
XmmResult = vcvtss2sh_avx512fp16( evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTTPH2DQ 5-100 PAGE 1924 LINE 106453
|
|
define pcodeop vcvttph2dq_avx512fp16 ;
|
|
:VCVTTPH2DQ XmmReg1^XmmOpMask32, XmmReg2_m64_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask32; byte=0x5B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64_m16bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)
|
|
{
|
|
XmmResult = vcvttph2dq_avx512fp16( XmmReg2_m64_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTTPH2DQ 5-100 PAGE 1924 LINE 106457
|
|
:VCVTTPH2DQ YmmReg1^YmmOpMask32, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask32; byte=0x5B; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)
|
|
{
|
|
YmmResult = vcvttph2dq_avx512fp16( XmmReg2_m128_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTTPH2DQ 5-100 PAGE 1924 LINE 106461
|
|
:VCVTTPH2DQ ZmmReg1^ZmmOpMask32, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask32; byte=0x5B; ZmmReg1 ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)
|
|
{
|
|
ZmmResult = vcvttph2dq_avx512fp16( YmmReg2_m256_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTTPH2QQ 5-102 PAGE 1926 LINE 106537
|
|
define pcodeop vcvttph2qq_avx512fp16 ;
|
|
:VCVTTPH2QQ XmmReg1^XmmOpMask64, XmmReg2_m32_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask64; byte=0x7A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32_m16bcst
|
|
{
|
|
XmmResult = vcvttph2qq_avx512fp16( XmmReg2_m32_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTTPH2QQ 5-102 PAGE 1926 LINE 106541
|
|
:VCVTTPH2QQ YmmReg1^YmmOpMask64, XmmReg2_m64_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask64; byte=0x7A; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64_m16bcst
|
|
{
|
|
YmmResult = vcvttph2qq_avx512fp16( XmmReg2_m64_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTTPH2QQ 5-102 PAGE 1926 LINE 106545
|
|
:VCVTTPH2QQ ZmmReg1^ZmmOpMask64, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask64; byte=0x7A; ZmmReg1 ... & XmmReg2_m128_m16bcst
|
|
{
|
|
ZmmResult = vcvttph2qq_avx512fp16( XmmReg2_m128_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTTPH2UDQ 5-104 PAGE 1928 LINE 106622
|
|
define pcodeop vcvttph2udq_avx512fp16 ;
|
|
:VCVTTPH2UDQ XmmReg1^XmmOpMask32, XmmReg2_m64_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask32; byte=0x78; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64_m16bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)
|
|
{
|
|
XmmResult = vcvttph2udq_avx512fp16( XmmReg2_m64_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTTPH2UDQ 5-104 PAGE 1928 LINE 106626
|
|
:VCVTTPH2UDQ YmmReg1^YmmOpMask32, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask32; byte=0x78; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)
|
|
{
|
|
YmmResult = vcvttph2udq_avx512fp16( XmmReg2_m128_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTTPH2UDQ 5-104 PAGE 1928 LINE 106630
|
|
:VCVTTPH2UDQ ZmmReg1^ZmmOpMask32, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask32; byte=0x78; ZmmReg1 ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 1; ] # (TupleType Half)
|
|
{
|
|
ZmmResult = vcvttph2udq_avx512fp16( YmmReg2_m256_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTTPH2UQQ 5-106 PAGE 1930 LINE 106706
|
|
define pcodeop vcvttph2uqq_avx512fp16 ;
|
|
:VCVTTPH2UQQ XmmReg1^XmmOpMask64, XmmReg2_m32_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask64; byte=0x78; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32_m16bcst
|
|
{
|
|
XmmResult = vcvttph2uqq_avx512fp16( XmmReg2_m32_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTTPH2UQQ 5-106 PAGE 1930 LINE 106710
|
|
:VCVTTPH2UQQ YmmReg1^YmmOpMask64, XmmReg2_m64_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask64; byte=0x78; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64_m16bcst
|
|
{
|
|
YmmResult = vcvttph2uqq_avx512fp16( XmmReg2_m64_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTTPH2UQQ 5-106 PAGE 1930 LINE 106714
|
|
:VCVTTPH2UQQ ZmmReg1^ZmmOpMask64, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask64; byte=0x78; ZmmReg1 ... & XmmReg2_m128_m16bcst
|
|
{
|
|
ZmmResult = vcvttph2uqq_avx512fp16( XmmReg2_m128_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTTPH2UW 5-108 PAGE 1932 LINE 106790
|
|
define pcodeop vcvttph2uw_avx512fp16 ;
|
|
:VCVTTPH2UW XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x7C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvttph2uw_avx512fp16( XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTTPH2UW 5-108 PAGE 1932 LINE 106794
|
|
:VCVTTPH2UW YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16; byte=0x7C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vcvttph2uw_avx512fp16( YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTTPH2UW 5-108 PAGE 1932 LINE 106798
|
|
:VCVTTPH2UW ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16; byte=0x7C; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vcvttph2uw_avx512fp16( ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTTPH2W 5-110 PAGE 1934 LINE 106874
|
|
define pcodeop vcvttph2w_avx512fp16 ;
|
|
:VCVTTPH2W XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x7C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvttph2w_avx512fp16( XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTTPH2W 5-110 PAGE 1934 LINE 106878
|
|
:VCVTTPH2W YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16; byte=0x7C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vcvttph2w_avx512fp16( YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTTPH2W 5-110 PAGE 1934 LINE 106882
|
|
:VCVTTPH2W ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16; byte=0x7C; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vcvttph2w_avx512fp16( ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTTSH2SI 5-119 PAGE 1943 LINE 107355
|
|
define pcodeop vcvttsh2si_avx512fp16 ;
|
|
:VCVTTSH2SI Reg32, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0); byte=0x2C; (Reg32 & check_Reg32_dest)... & XmmReg2_m16
|
|
{
|
|
Reg32 = vcvttsh2si_avx512fp16( XmmReg2_m16 );
|
|
build check_Reg32_dest;
|
|
}
|
|
|
|
# VCVTTSH2SI 5-119 PAGE 1943 LINE 107358
|
|
@ifdef IA64
|
|
:VCVTTSH2SI Reg64, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W1); byte=0x2C; Reg64 ... & XmmReg2_m16
|
|
{
|
|
Reg64 = vcvttsh2si_avx512fp16( XmmReg2_m16 );
|
|
}
|
|
@endif
|
|
|
|
# VCVTTSH2USI 5-120 PAGE 1944 LINE 107409
|
|
define pcodeop vcvttsh2usi_avx512fp16 ;
|
|
:VCVTTSH2USI Reg32, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0); byte=0x78; (Reg32 & check_Reg32_dest) ... & XmmReg2_m16
|
|
{
|
|
Reg32 = vcvttsh2usi_avx512fp16( XmmReg2_m16 );
|
|
build check_Reg32_dest;
|
|
}
|
|
|
|
# VCVTTSH2USI 5-120 PAGE 1944 LINE 107412
|
|
@ifdef IA64
|
|
:VCVTTSH2USI Reg64, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W1); byte=0x78; Reg64 ... & XmmReg2_m16
|
|
{
|
|
Reg64 = vcvttsh2usi_avx512fp16( XmmReg2_m16 );
|
|
}
|
|
@endif
|
|
|
|
# VCVTUDQ2PH 5-124 PAGE 1948 LINE 107633
|
|
define pcodeop vcvtudq2ph_avx512fp16 ;
|
|
:VCVTUDQ2PH XmmReg1^XmmOpMask16, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x7A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvtudq2ph_avx512fp16( XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult[0,64]);
|
|
}
|
|
|
|
# VCVTUDQ2PH 5-124 PAGE 1948 LINE 107637
|
|
:VCVTUDQ2PH XmmReg1^XmmOpMask16, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x7A; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvtudq2ph_avx512fp16( YmmReg2_m256_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTUDQ2PH 5-124 PAGE 1948 LINE 107641
|
|
:VCVTUDQ2PH YmmReg1^YmmOpMask16, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16; byte=0x7A; (YmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vcvtudq2ph_avx512fp16( ZmmReg2_m512_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTUQQ2PH 5-130 PAGE 1954 LINE 107951
|
|
define pcodeop vcvtuqq2ph_avx512fp16 ;
|
|
:VCVTUQQ2PH XmmReg1^XmmOpMask16, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_MAP5) & $(VEX_W1) & XmmOpMask16; byte=0x7A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvtuqq2ph_avx512fp16( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult[0,32]);
|
|
}
|
|
|
|
# VCVTUQQ2PH 5-130 PAGE 1954 LINE 107955
|
|
:VCVTUQQ2PH XmmReg1^XmmOpMask16, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_MAP5) & $(VEX_W1) & XmmOpMask16; byte=0x7A; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvtuqq2ph_avx512fp16( YmmReg2_m256_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult[0,64]);
|
|
}
|
|
|
|
# VCVTUQQ2PH 5-130 PAGE 1954 LINE 107959
|
|
:VCVTUQQ2PH XmmReg1^XmmOpMask16, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_MAP5) & $(VEX_W1) & XmmOpMask16; byte=0x7A; (XmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvtuqq2ph_avx512fp16( ZmmReg2_m512_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTUSI2SH 5-132 PAGE 1956 LINE 108039
|
|
define pcodeop vcvtusi2sh_avx512fp16 ;
|
|
:VCVTUSI2SH XmmReg1, evexV5_XmmReg, rm32 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & evexV5_XmmReg; byte=0x7B; (XmmReg1 & ZmmReg1) ... & rm32
|
|
{
|
|
local tmp:16 = vcvtusi2sh_avx512fp16( evexV5_XmmReg, rm32 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VCVTUSI2SH 5-132 PAGE 1956 LINE 108043
|
|
@ifdef IA64
|
|
:VCVTUSI2SH XmmReg1, evexV5_XmmReg, rm64 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W1) & evexV5_XmmReg; byte=0x7B; (XmmReg1 & ZmmReg1) ... & rm64
|
|
{
|
|
local tmp:16 = vcvtusi2sh_avx512fp16( evexV5_XmmReg, rm64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
@endif
|
|
|
|
# VCVTUW2PH 5-140 PAGE 1964 LINE 108377
|
|
define pcodeop vcvtuw2ph_avx512fp16 ;
|
|
:VCVTUW2PH XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x7D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvtuw2ph_avx512fp16( XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTUW2PH 5-140 PAGE 1964 LINE 108380
|
|
:VCVTUW2PH YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16; byte=0x7D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vcvtuw2ph_avx512fp16( YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTUW2PH 5-140 PAGE 1964 LINE 108383
|
|
:VCVTUW2PH ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16; byte=0x7D; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vcvtuw2ph_avx512fp16( ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VCVTW2PH 5-142 PAGE 1966 LINE 108464
|
|
define pcodeop vcvtw2ph_avx512fp16 ;
|
|
:VCVTW2PH XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x7D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vcvtw2ph_avx512fp16( XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VCVTW2PH 5-142 PAGE 1966 LINE 108467
|
|
:VCVTW2PH YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16; byte=0x7D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vcvtw2ph_avx512fp16( YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VCVTW2PH 5-142 PAGE 1966 LINE 108470
|
|
:VCVTW2PH ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16; byte=0x7D; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vcvtw2ph_avx512fp16( ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VDIVPH 5-147 PAGE 1971 LINE 108747
|
|
define pcodeop vdivph_avx512fp16 ;
|
|
:VDIVPH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vdivph_avx512fp16( evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VDIVPH 5-147 PAGE 1971 LINE 108750
|
|
:VDIVPH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x5E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vdivph_avx512fp16( evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VDIVPH 5-147 PAGE 1971 LINE 108753
|
|
:VDIVPH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x5E; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vdivph_avx512fp16( evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VDIVSH 5-149 PAGE 1973 LINE 108842
|
|
define pcodeop vdivsh_avx512fp16 ;
|
|
:VDIVSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vdivsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = evexV5_XmmReg[16,112]; #DEST[127:16] := SRC1[127:16]
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VDPBF16PS 5-150 PAGE 1974 LINE 108901
|
|
define pcodeop vdpbf16ps_avx512vl ;
|
|
:VDPBF16PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x52; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vdpbf16ps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VDPBF16PS 5-150 PAGE 1974 LINE 108905
|
|
:VDPBF16PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x52; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vdpbf16ps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VDPBF16PS 5-150 PAGE 1974 LINE 108909
|
|
define pcodeop vdpbf16ps_avx512f ;
|
|
:VDPBF16PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x52; ZmmReg1 ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vdpbf16ps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFCMADDCPH/VFMADDCPH 5-170 PAGE 1994 LINE 109930
|
|
define pcodeop vfcmaddcph_avx512fp16 ;
|
|
:VFCMADDCPH XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vfcmaddcph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFCMADDCPH/VFMADDCPH 5-170 PAGE 1994 LINE 109934
|
|
:VFCMADDCPH YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vfcmaddcph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFCMADDCPH/VFMADDCPH 5-170 PAGE 1994 LINE 109938
|
|
:VFCMADDCPH ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x56; ZmmReg1 ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vfcmaddcph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFCMADDCPH/VFMADDCPH 5-170 PAGE 1994 LINE 109942
|
|
define pcodeop vfmaddcph_avx512fp16 ;
|
|
:VFMADDCPH XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vfmaddcph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFCMADDCPH/VFMADDCPH 5-170 PAGE 1994 LINE 109946
|
|
:VFMADDCPH YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vfmaddcph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFCMADDCPH/VFMADDCPH 5-170 PAGE 1994 LINE 109950
|
|
:VFMADDCPH ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x56; ZmmReg1 ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vfmaddcph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFCMADDCSH/VFMADDCSH 5-173 PAGE 1997 LINE 110095
|
|
define pcodeop vfcmaddcsh_avx512fp16 ;
|
|
:VFCMADDCSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F2) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
|
|
{
|
|
XmmResult = vfcmaddcsh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,32], XmmOpMask[0,1], XmmResult[0,32], XmmMask[0,32]);
|
|
XmmResult[32,96] = evexV5_XmmReg[32,96]; # DEST[127:32] := src1[127:32] // copy upper part of src1
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFCMADDCSH/VFMADDCSH 5-173 PAGE 1997 LINE 110100
|
|
define pcodeop vfmaddcsh_avx512fp16 ;
|
|
:VFMADDCSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
|
|
{
|
|
XmmResult = vfmaddcsh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,32], XmmOpMask[0,1], XmmResult[0,32], XmmMask[0,32]);
|
|
XmmResult[32,96] = evexV5_XmmReg[32,96]; # DEST[127:32] := src1[127:32] // copy upper part of src1
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFCMULCPH/VFMULCPH 5-175 PAGE 1999 LINE 110198
|
|
define pcodeop vfcmulcph_avx512fp16 ;
|
|
:VFCMULCPH XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0xD6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vfcmulcph_avx512fp16( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFCMULCPH/VFMULCPH 5-175 PAGE 1999 LINE 110202
|
|
:VFCMULCPH YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0xD6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vfcmulcph_avx512fp16( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFCMULCPH/VFMULCPH 5-175 PAGE 1999 LINE 110206
|
|
:VFCMULCPH ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0xD6; ZmmReg1 ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vfcmulcph_avx512fp16( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFCMULCPH/VFMULCPH 5-175 PAGE 1999 LINE 110210
|
|
define pcodeop vfmulcph_avx512fp16 ;
|
|
:VFMULCPH XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0xD6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vfmulcph_avx512fp16( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFCMULCPH/VFMULCPH 5-175 PAGE 1999 LINE 110213
|
|
:VFMULCPH YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0xD6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vfmulcph_avx512fp16( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFCMULCPH/VFMULCPH 5-175 PAGE 1999 LINE 110216
|
|
:VFMULCPH ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0xD6; ZmmReg1 ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vfmulcph_avx512fp16( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFCMULCSH/VFMULCSH 5-178 PAGE 2002 LINE 110374
|
|
define pcodeop vfcmulcsh_avx512fp16 ;
|
|
:VFCMULCSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F2) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xD7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
|
|
{
|
|
XmmResult = vfcmulcsh_avx512fp16( evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,32], XmmOpMask[0,1], XmmResult[0,32], XmmMask[0,32]);
|
|
XmmResult[32,96] = evexV5_XmmReg[32,96]; # DEST[127:32] := src1[127:32] // copy upper part of src1
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFCMULCSH/VFMULCSH 5-178 PAGE 2002 LINE 110379
|
|
define pcodeop vfmulcsh_avx512fp16 ;
|
|
:VFMULCSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xD7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
|
|
{
|
|
XmmResult = vfmulcsh_avx512fp16( evexV5_XmmReg, XmmReg2_m32 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,32], XmmOpMask[0,1], XmmResult[0,32], XmmMask[0,32]);
|
|
XmmResult[32,96] = evexV5_XmmReg[32,96]; # DEST[127:32] := src1[127:32] // copy upper part of src1
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111596
|
|
define pcodeop vfmadd132ph_avx512fp16 ;
|
|
:VFMADD132PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x98; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vfmadd132ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111599
|
|
:VFMADD132PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x98; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vfmadd132ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111602
|
|
:VFMADD132PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x98; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vfmadd132ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111605
|
|
define pcodeop vfmadd213ph_avx512fp16 ;
|
|
:VFMADD213PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xA8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vfmadd213ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111608
|
|
:VFMADD213PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xA8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vfmadd213ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111611
|
|
:VFMADD213PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xA8; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vfmadd213ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111614
|
|
define pcodeop vfmadd231ph_avx512fp16 ;
|
|
:VFMADD231PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xB8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vfmadd231ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111617
|
|
:VFMADD231PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xB8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vfmadd231ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111620
|
|
:VFMADD231PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xB8; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vfmadd231ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111623
|
|
define pcodeop vfnmadd132ph_avx512fp16 ;
|
|
:VFNMADD132PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x9C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vfnmadd132ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111627
|
|
:VFNMADD132PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x9C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vfnmadd132ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111631
|
|
:VFNMADD132PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x9C; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vfnmadd132ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111635
|
|
define pcodeop vfnmadd213ph_avx512fp16 ;
|
|
:VFNMADD213PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xAC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vfnmadd213ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]PH 5-201 PAGE 2025 LINE 111639
|
|
:VFNMADD213PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xAC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vfnmadd213ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]PH 5-202 PAGE 2026 LINE 111655
|
|
:VFNMADD213PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xAC; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vfnmadd213ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]PH 5-202 PAGE 2026 LINE 111659
|
|
define pcodeop vfnmadd231ph_avx512fp16 ;
|
|
:VFNMADD231PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xBC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vfnmadd231ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]PH 5-202 PAGE 2026 LINE 111663
|
|
:VFNMADD231PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xBC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vfnmadd231ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]PH 5-202 PAGE 2026 LINE 111667
|
|
:VFNMADD231PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xBC; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vfnmadd231ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]SH 5-219 PAGE 2043 LINE 112545
|
|
define pcodeop vfmadd132sh_avx512fp16 ;
|
|
:VFMADD132SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x99; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vfmadd132sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]SH 5-219 PAGE 2043 LINE 112548
|
|
define pcodeop vfmadd213sh_avx512fp16 ;
|
|
:VFMADD213SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xA9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vfmadd213sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]SH 5-219 PAGE 2043 LINE 112551
|
|
define pcodeop vfmadd231sh_avx512fp16 ;
|
|
:VFMADD231SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xB9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vfmadd231sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]SH 5-219 PAGE 2043 LINE 112554
|
|
define pcodeop vfnmadd132sh_avx512fp16 ;
|
|
:VFNMADD132SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x9D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vfnmadd132sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]SH 5-219 PAGE 2043 LINE 112557
|
|
define pcodeop vfnmadd213sh_avx512fp16 ;
|
|
:VFNMADD213SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xAD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vfnmadd213sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VF[,N]MADD[132,213,231]SH 5-219 PAGE 2043 LINE 112560
|
|
define pcodeop vfnmadd231sh_avx512fp16 ;
|
|
:VFNMADD231SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xBD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vfnmadd231sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
# VFMADDSUB132PH/VFMADDSUB213PH/VFMADDSUB231PH 5-232 PAGE 2056 LINE 113276
|
|
define pcodeop vfmaddsub132ph_avx512fp16 ;
|
|
:VFMADDSUB132PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x96; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vfmaddsub132ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMADDSUB132PH/VFMADDSUB213PH/VFMADDSUB231PH 5-232 PAGE 2056 LINE 113280
|
|
:VFMADDSUB132PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x96; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vfmaddsub132ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMADDSUB132PH/VFMADDSUB213PH/VFMADDSUB231PH 5-232 PAGE 2056 LINE 113284
|
|
:VFMADDSUB132PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x96; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vfmaddsub132ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMADDSUB132PH/VFMADDSUB213PH/VFMADDSUB231PH 5-232 PAGE 2056 LINE 113288
|
|
define pcodeop vfmaddsub213ph_avx512fp16 ;
|
|
:VFMADDSUB213PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xA6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vfmaddsub213ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMADDSUB132PH/VFMADDSUB213PH/VFMADDSUB231PH 5-232 PAGE 2056 LINE 113292
|
|
:VFMADDSUB213PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xA6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vfmaddsub213ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMADDSUB132PH/VFMADDSUB213PH/VFMADDSUB231PH 5-232 PAGE 2056 LINE 113296
|
|
:VFMADDSUB213PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xA6; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vfmaddsub213ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMADDSUB132PH/VFMADDSUB213PH/VFMADDSUB231PH 5-232 PAGE 2056 LINE 113300
|
|
define pcodeop vfmaddsub231ph_avx512fp16 ;
|
|
:VFMADDSUB231PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xB6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vfmaddsub231ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMADDSUB132PH/VFMADDSUB213PH/VFMADDSUB231PH 5-232 PAGE 2056 LINE 113304
|
|
:VFMADDSUB231PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xB6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vfmaddsub231ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMADDSUB132PH/VFMADDSUB213PH/VFMADDSUB231PH 5-232 PAGE 2056 LINE 113308
|
|
:VFMADDSUB231PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xB6; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vfmaddsub231ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114283
|
|
define pcodeop vfmsub132ph_avx512fp16 ;
|
|
:VFMSUB132PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x9A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vfmsub132ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114286
|
|
:VFMSUB132PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x9A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vfmsub132ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114289
|
|
:VFMSUB132PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x9A; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vfmsub132ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114292
|
|
define pcodeop vfmsub213ph_avx512fp16 ;
|
|
:VFMSUB213PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xAA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vfmsub213ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114295
|
|
:VFMSUB213PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xAA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vfmsub213ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114298
|
|
:VFMSUB213PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xAA; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vfmsub213ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114301
|
|
define pcodeop vfmsub231ph_avx512fp16 ;
|
|
:VFMSUB231PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xBA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vfmsub231ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114304
|
|
:VFMSUB231PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vfmsub231ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114307
|
|
:VFMSUB231PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xBA; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vfmsub231ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114310
|
|
define pcodeop vfnmsub132ph_avx512fp16 ;
|
|
:VFNMSUB132PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x9E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vfnmsub132ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114314
|
|
:VFNMSUB132PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x9E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vfnmsub132ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114318
|
|
:VFNMSUB132PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x9E; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vfnmsub132ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114322
|
|
define pcodeop vfnmsub213ph_avx512fp16 ;
|
|
:VFNMSUB213PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xAE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vfnmsub213ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VF[,N]MSUB[132,213,231]PH 5-250 PAGE 2074 LINE 114326
|
|
:VFNMSUB213PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xAE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vfnmsub213ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VF[,N]MSUB[132,213,231]PH 5-251 PAGE 2075 LINE 114342
|
|
:VFNMSUB213PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xAE; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vfnmsub213ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VF[,N]MSUB[132,213,231]PH 5-251 PAGE 2075 LINE 114346
|
|
define pcodeop vfnmsub231ph_avx512fp16 ;
|
|
:VFNMSUB231PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xBE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vfnmsub231ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VF[,N]MSUB[132,213,231]PH 5-251 PAGE 2075 LINE 114350
|
|
:VFNMSUB231PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xBE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vfnmsub231ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VF[,N]MSUB[132,213,231]PH 5-251 PAGE 2075 LINE 114354
|
|
:VFNMSUB231PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xBE; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vfnmsub231ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VF[,N]MSUB[132,213,231]SH 5-265 PAGE 2089 LINE 115111
|
|
define pcodeop vfmsub132sh_avx512fp16 ;
|
|
:VFMSUB132SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x9B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vfmsub132sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VF[,N]MSUB[132,213,231]SH 5-265 PAGE 2089 LINE 115114
|
|
define pcodeop vfmsub213sh_avx512fp16 ;
|
|
:VFMSUB213SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xAB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vfmsub213sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VF[,N]MSUB[132,213,231]SH 5-265 PAGE 2089 LINE 115117
|
|
define pcodeop vfmsub231sh_avx512fp16 ;
|
|
:VFMSUB231SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xBB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vfmsub231sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VF[,N]MSUB[132,213,231]SH 5-265 PAGE 2089 LINE 115120
|
|
define pcodeop vfnmsub132sh_avx512fp16 ;
|
|
:VFNMSUB132SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x9F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vfnmsub132sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VF[,N]MSUB[132,213,231]SH 5-265 PAGE 2089 LINE 115124
|
|
define pcodeop vfnmsub213sh_avx512fp16 ;
|
|
:VFNMSUB213SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xAF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vfnmsub213sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VF[,N]MSUB[132,213,231]SH 5-265 PAGE 2089 LINE 115128
|
|
define pcodeop vfnmsub231sh_avx512fp16 ;
|
|
:VFNMSUB231SH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0xBF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vfnmsub231sh_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMSUBADD132PH/VFMSUBADD213PH/VFMSUBADD231PH 5-278 PAGE 2102 LINE 115851
|
|
define pcodeop vfmsubadd132ph_avx512fp16 ;
|
|
:VFMSUBADD132PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vfmsubadd132ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMSUBADD132PH/VFMSUBADD213PH/VFMSUBADD231PH 5-278 PAGE 2102 LINE 115855
|
|
:VFMSUBADD132PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vfmsubadd132ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMSUBADD132PH/VFMSUBADD213PH/VFMSUBADD231PH 5-278 PAGE 2102 LINE 115859
|
|
:VFMSUBADD132PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x97; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vfmsubadd132ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMSUBADD132PH/VFMSUBADD213PH/VFMSUBADD231PH 5-278 PAGE 2102 LINE 115863
|
|
define pcodeop vfmsubadd213ph_avx512fp16 ;
|
|
:VFMSUBADD213PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vfmsubadd213ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMSUBADD132PH/VFMSUBADD213PH/VFMSUBADD231PH 5-278 PAGE 2102 LINE 115867
|
|
:VFMSUBADD213PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vfmsubadd213ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMSUBADD132PH/VFMSUBADD213PH/VFMSUBADD231PH 5-278 PAGE 2102 LINE 115871
|
|
:VFMSUBADD213PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xA7; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vfmsubadd213ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VFMSUBADD132PH/VFMSUBADD213PH/VFMSUBADD231PH 5-278 PAGE 2102 LINE 115875
|
|
define pcodeop vfmsubadd231ph_avx512fp16 ;
|
|
:VFMSUBADD231PH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vfmsubadd231ph_avx512fp16( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VFMSUBADD132PH/VFMSUBADD213PH/VFMSUBADD231PH 5-278 PAGE 2102 LINE 115879
|
|
:VFMSUBADD231PH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vfmsubadd231ph_avx512fp16( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VFMSUBADD132PH/VFMSUBADD213PH/VFMSUBADD231PH 5-278 PAGE 2102 LINE 115883
|
|
:VFMSUBADD231PH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0xB7; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vfmsubadd231ph_avx512fp16( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
ClassNeg: "Negative" is imm8_6=1 & imm8_7=0 {}
|
|
ClassNeg: "Negative,SNAN" is imm8_6=1 & imm8_7=1 {}
|
|
ClassNeg: "SNAN" is imm8_6=0 & imm8_7=1 {}
|
|
|
|
ClassDenorm: "Denormal" is imm8_5=1 & imm8_6_7=0 {}
|
|
ClassDenorm: "Denormal,"^ClassNeg is imm8_5=1 & ClassNeg {}
|
|
ClassDenorm: ClassNeg is imm8_5=0 & ClassNeg {}
|
|
|
|
ClassNegI: "NegINF" is imm8_4=1 & imm8_5_7=0 {}
|
|
ClassNegI: "NegINF,"^ClassDenorm is imm8_4=1 & ClassDenorm {}
|
|
ClassNegI: ClassDenorm is imm8_4=0 & ClassDenorm {}
|
|
|
|
ClassPosI: "PosINF" is imm8_3=1 & imm8_4_7=0 {}
|
|
ClassPosI: "PosINF,"^ClassNegI is imm8_3=1 & ClassNegI {}
|
|
ClassPosI: ClassNegI is imm8_3=0 & ClassNegI {}
|
|
|
|
ClassNegZ: "NegZero" is imm8_2=1 & imm8_3_7=0 {}
|
|
ClassNegZ: "NegZero,"^ClassPosI is imm8_2=1 & ClassPosI {}
|
|
ClassNegZ: ClassPosI is imm8_2=0 & ClassPosI {}
|
|
|
|
ClassPosZ: "PosZero" is imm8_1=1 & imm8_2_7=0 {}
|
|
ClassPosZ: "PosZero,"^ClassNegZ is imm8_1=1 & ClassNegZ {}
|
|
ClassPosZ: ClassNegZ is imm8_1=0 & ClassNegZ {}
|
|
|
|
ClassQNaN: "QNAN" is imm8_0=1 & imm8_1_7=0 {}
|
|
ClassQNaN: "QNAN,"^ClassPosZ is imm8_0=1 & ClassPosZ {}
|
|
ClassQNaN: ClassPosZ is imm8_0=0 & ClassPosZ {}
|
|
ClassQNaN: "" is imm8=0 {}
|
|
|
|
ClassOp: "{"^ClassQNaN^"}" is ClassQNaN & imm8 { export *[const]:1 imm8;}
|
|
# VFPCLASSPH 5-332 PAGE 2156 LINE 118786
|
|
define pcodeop vfpclassph_avx512fp16 ;
|
|
:VFPCLASSPH KReg_reg^XmmOpMask, XmmReg2_m128_m16bcst, ClassOp is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x66; KReg_reg ... & XmmReg2_m128_m16bcst; ClassOp
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
local tmp:8 = vfpclassph_avx512fp16( XmmReg2_m128_m16bcst, XmmOpMask, ClassOp );
|
|
KReg_reg = tmp;
|
|
}
|
|
|
|
# VFPCLASSPH 5-332 PAGE 2156 LINE 118792
|
|
:VFPCLASSPH KReg_reg^XmmOpMask, YmmReg2_m256_m16bcst, ClassOp is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x66; KReg_reg ... & YmmReg2_m256_m16bcst; ClassOp
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
local tmp:8 = vfpclassph_avx512fp16( YmmReg2_m256_m16bcst, XmmOpMask, ClassOp );
|
|
KReg_reg = tmp;
|
|
}
|
|
|
|
# VFPCLASSPH 5-332 PAGE 2156 LINE 118798
|
|
:VFPCLASSPH KReg_reg^XmmOpMask, ZmmReg2_m512_m16bcst, ClassOp is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x66; KReg_reg ... & ZmmReg2_m512_m16bcst; ClassOp
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
local tmp:8 = vfpclassph_avx512fp16( ZmmReg2_m512_m16bcst, XmmOpMask, ClassOp );
|
|
KReg_reg = tmp;
|
|
}
|
|
|
|
# VFPCLASSSH 5-339 PAGE 2163 LINE 119114
|
|
define pcodeop vfpclasssh_avx512fp16 ;
|
|
:VFPCLASSSH KReg_reg^XmmOpMask, XmmReg2_m16, ClassOp is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x67; KReg_reg ... & XmmReg2_m16; ClassOp
|
|
{
|
|
local tmp:8 = vfpclasssh_avx512fp16( XmmReg2_m16, XmmOpMask, ClassOp );
|
|
KReg_reg = tmp;
|
|
}
|
|
|
|
# VGETEXPPH 5-359 PAGE 2183 LINE 120137
|
|
define pcodeop vgetexpph_avx512fp16 ;
|
|
:VGETEXPPH XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16; byte=0x42; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vgetexpph_avx512fp16( XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VGETEXPPH 5-359 PAGE 2183 LINE 120141
|
|
:VGETEXPPH YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16; byte=0x42; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vgetexpph_avx512fp16( YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VGETEXPPH 5-359 PAGE 2183 LINE 120145
|
|
:VGETEXPPH ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16; byte=0x42; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vgetexpph_avx512fp16( ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VGETEXPSH 5-368 PAGE 2192 LINE 120571
|
|
define pcodeop vgetexpsh_avx512fp16 ;
|
|
:VGETEXPSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x43; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vgetexpsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VGETMANTPH 5-376 PAGE 2200 LINE 120939
|
|
define pcodeop vgetmantph_avx512fp16 ;
|
|
:VGETMANTPH XmmReg1^XmmOpMask16,XmmReg2_m128_m16bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask16; byte=0x26; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vgetmantph_avx512fp16( XmmReg2_m128_m16bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VGETMANTPH 5-376 PAGE 2200 LINE 120943
|
|
:VGETMANTPH YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask16; byte=0x26; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vgetmantph_avx512fp16( YmmReg2_m256_m16bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VGETMANTPH 5-376 PAGE 2200 LINE 120947
|
|
:VGETMANTPH ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & ZmmOpMask16; byte=0x26; ZmmReg1 ... & ZmmReg2_m512_m16bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vgetmantph_avx512fp16( ZmmReg2_m512_m16bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VGETMANTSH 5-385 PAGE 2209 LINE 121406
|
|
define pcodeop vgetmantsh_avx512fp16 ;
|
|
:VGETMANTSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16, imm8 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x27; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16; imm8
|
|
{
|
|
XmmResult = vgetmantsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VMAXPH 5-400 PAGE 2224 LINE 122191
|
|
define pcodeop vmaxph_avx512fp16 ;
|
|
:VMAXPH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vmaxph_avx512fp16( evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VMAXPH 5-400 PAGE 2224 LINE 122194
|
|
:VMAXPH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x5F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vmaxph_avx512fp16( evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VMAXPH 5-400 PAGE 2224 LINE 122197
|
|
:VMAXPH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x5F; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vmaxph_avx512fp16( evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VMAXSH 5-402 PAGE 2226 LINE 122291
|
|
define pcodeop vmaxsh_avx512fp16 ;
|
|
:VMAXSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vmaxsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VMINPH 5-404 PAGE 2228 LINE 122372
|
|
define pcodeop vminph_avx512fp16 ;
|
|
:VMINPH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vminph_avx512fp16( evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VMINPH 5-404 PAGE 2228 LINE 122375
|
|
:VMINPH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x5D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vminph_avx512fp16( evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VMINPH 5-404 PAGE 2228 LINE 122378
|
|
:VMINPH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x5D; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vminph_avx512fp16( evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VMINSH 5-406 PAGE 2230 LINE 122472
|
|
define pcodeop vminsh_avx512fp16 ;
|
|
:VMINSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vminsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VMOVSH 5-408 PAGE 2232 LINE 122557
|
|
define pcodeop vmovsh_avx512fp16 ;
|
|
:VMOVSH XmmReg1^XmmOpMask, m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask; byte=0x10; (XmmReg1 & ZmmReg1) ... & m16
|
|
{
|
|
local tmp = m16;
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], tmp, XmmMask[0,16]);
|
|
XmmResult[16,112] = 0;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VMOVSH 5-408 PAGE 2232 LINE 122559
|
|
:VMOVSH m16^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask; byte=0x11; XmmReg1 ... & m16
|
|
{
|
|
local tmp:2 = XmmReg1(0);
|
|
local mask = m16;
|
|
build XmmOpMask;
|
|
conditionalAssign(tmp, XmmOpMask[0,1], tmp, mask);
|
|
m16 = tmp;
|
|
}
|
|
|
|
# VMOVSH 5-408 PAGE 2232 LINE 122561
|
|
# WARNING: duplicate opcode EVEX.LLIG.F3.MAP5.W0 10 /r last seen on 5-408 PAGE 2232 LINE 122557 for "VMOVSH xmm1{k1}{z}, xmm2, xmm3"
|
|
:VMOVSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x10; (XmmReg1 & ZmmReg1) & (mod=0x3 & XmmReg2)
|
|
{
|
|
local tmp = XmmReg2(0);
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], tmp, XmmMask[0,16]);
|
|
XmmResult[16,112] = evexV5_XmmReg[16,112]; # DEST[127:16] := SRC1[127:16]
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VMOVSH 5-408 PAGE 2232 LINE 122564
|
|
# WARNING: duplicate opcode EVEX.LLIG.F3.MAP5.W0 11 /r last seen on 5-408 PAGE 2232 LINE 122559 for "VMOVSH xmm1{k1}{z}, xmm2, xmm3"
|
|
:VMOVSH XmmReg2^XmmOpMask, evexV5_XmmReg, XmmReg1 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x11; XmmReg1 & (mod=0x3 & (XmmReg2 & ZmmReg2))
|
|
{
|
|
XmmResult = XmmReg1;
|
|
XmmMask = XmmReg2;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = evexV5_XmmReg[16,112]; # DEST[127:16] := SRC1[127:16]
|
|
ZmmReg2 = zext(XmmResult);
|
|
}
|
|
|
|
# VMOVW 5-410 PAGE 2234 LINE 122642
|
|
define pcodeop vmovw_avx512fp16 ;
|
|
:VMOVW XmmReg1, rm16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_WIG); byte=0x6E; (XmmReg1 & ZmmReg1) ... & rm16
|
|
{
|
|
local tmp:2 = rm16 ;
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VMOVW 5-410 PAGE 2234 LINE 122644
|
|
:VMOVW rm16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP5) & $(VEX_WIG); byte=0x7E; XmmReg1 ... & rm16
|
|
{
|
|
rm16 = XmmReg1(0);
|
|
}
|
|
|
|
# VMULPH 5-411 PAGE 2235 LINE 122691
|
|
define pcodeop vmulph_avx512fp16 ;
|
|
:VMULPH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vmulph_avx512fp16( evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VMULPH 5-411 PAGE 2235 LINE 122694
|
|
:VMULPH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x59; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vmulph_avx512fp16( evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VMULPH 5-411 PAGE 2235 LINE 122697
|
|
:VMULPH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x59; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vmulph_avx512fp16( evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VMULSH 5-413 PAGE 2237 LINE 122785
|
|
define pcodeop vmulsh_avx512fp16 ;
|
|
:VMULSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vmulsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = evexV5_XmmReg[16,112]; # DEST[127:16] := SRC1[127:16]
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VP2INTERSECTD/VP2INTERSECTQ 5-414 PAGE 2238 LINE 122845
|
|
define pcodeop vp2intersectd_avx512vl ;
|
|
:VP2INTERSECTD KReg_reg, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W0) & evexV5_XmmReg; byte=0x68; KReg_reg ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
KReg_reg = vp2intersectd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
}
|
|
|
|
# VP2INTERSECTD/VP2INTERSECTQ 5-414 PAGE 2238 LINE 122849
|
|
:VP2INTERSECTD KReg_reg, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W0) & evexV5_YmmReg; byte=0x68; KReg_reg ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
KReg_reg = vp2intersectd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
}
|
|
|
|
# VP2INTERSECTD/VP2INTERSECTQ 5-414 PAGE 2238 LINE 122853
|
|
define pcodeop vp2intersectd_avx512f ;
|
|
:VP2INTERSECTD KReg_reg, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x68; KReg_reg ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
KReg_reg = vp2intersectd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
}
|
|
|
|
# VP2INTERSECTD/VP2INTERSECTQ 5-414 PAGE 2238 LINE 122857
|
|
define pcodeop vp2intersectq_avx512vl ;
|
|
:VP2INTERSECTQ KReg_reg, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W1) & evexV5_XmmReg; byte=0x68; KReg_reg ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
KReg_reg = vp2intersectq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
}
|
|
|
|
# VP2INTERSECTD/VP2INTERSECTQ 5-414 PAGE 2238 LINE 122861
|
|
:VP2INTERSECTQ KReg_reg, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W1) & evexV5_YmmReg; byte=0x68; KReg_reg ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
KReg_reg = vp2intersectq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
}
|
|
|
|
# VP2INTERSECTD/VP2INTERSECTQ 5-414 PAGE 2238 LINE 122865
|
|
define pcodeop vp2intersectq_avx512f ;
|
|
:VP2INTERSECTQ KReg_reg, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x68; KReg_reg ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
KReg_reg = vp2intersectq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
}
|
|
|
|
# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124606
|
|
define pcodeop vpcompressb_avx512_vbmi2 ;
|
|
:VPCOMPRESSB m128^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0x63; XmmReg1 ... & m128
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)
|
|
{
|
|
XmmResult = vpcompressb_avx512_vbmi2( XmmReg1, XmmOpMask );
|
|
m128 = XmmResult;
|
|
}
|
|
|
|
# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124608
|
|
# WARNING: duplicate opcode EVEX.128.66.0F38.W0 63 /r last seen on 5-449 PAGE 2273 LINE 124606 for "VPCOMPRESSB xmm1{k1}{z}, xmm2"
|
|
:VPCOMPRESSB XmmReg2^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0x63; XmmReg1 & (mod=0x3 & (XmmReg2 & ZmmReg2))
|
|
{
|
|
XmmResult = vpcompressb_avx512_vbmi2( XmmReg1, XmmOpMask );
|
|
ZmmReg2 = zext(XmmResult);
|
|
}
|
|
|
|
# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124610
|
|
:VPCOMPRESSB m256^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0x63; YmmReg1 ... & m256
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)
|
|
{
|
|
YmmResult = vpcompressb_avx512_vbmi2( YmmReg1, YmmOpMask );
|
|
m256 = YmmResult;
|
|
}
|
|
|
|
# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124612
|
|
# WARNING: duplicate opcode EVEX.256.66.0F38.W0 63 /r last seen on 5-449 PAGE 2273 LINE 124610 for "VPCOMPRESSB ymm1{k1}{z}, ymm2"
|
|
:VPCOMPRESSB YmmReg2^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0x63; YmmReg1 & (mod=0x3 & (YmmReg2 & ZmmReg2))
|
|
{
|
|
YmmResult = vpcompressb_avx512_vbmi2( YmmReg1, YmmOpMask );
|
|
ZmmReg2 = zext(YmmResult);
|
|
}
|
|
|
|
# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124614
|
|
:VPCOMPRESSB m512^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0x63; ZmmReg1 ... & m512
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)
|
|
{
|
|
ZmmResult = vpcompressb_avx512_vbmi2( ZmmReg1, ZmmOpMask );
|
|
m512 = ZmmResult;
|
|
}
|
|
|
|
# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124616
|
|
# WARNING: duplicate opcode EVEX.512.66.0F38.W0 63 /r last seen on 5-449 PAGE 2273 LINE 124614 for "VPCOMPRESSB zmm1{k1}{z}, zmm2"
|
|
:VPCOMPRESSB ZmmReg2^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0x63; ZmmReg1 & (mod=0x3 & ZmmReg2)
|
|
{
|
|
ZmmResult = vpcompressb_avx512_vbmi2( ZmmReg1, ZmmOpMask );
|
|
ZmmReg2 = ZmmResult;
|
|
}
|
|
|
|
# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124618
|
|
define pcodeop vpcompressw_avx512_vbmi2 ;
|
|
:VPCOMPRESSW m128^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0x63; XmmReg1 ... & m128
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)
|
|
{
|
|
XmmResult = vpcompressw_avx512_vbmi2( XmmReg1, XmmOpMask );
|
|
m128 = XmmResult;
|
|
}
|
|
|
|
# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124620
|
|
# WARNING: duplicate opcode EVEX.128.66.0F38.W1 63 /r last seen on 5-449 PAGE 2273 LINE 124618 for "VPCOMPRESSW xmm1{k1}{z}, xmm2"
|
|
:VPCOMPRESSW XmmReg2^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0x63; XmmReg1 & (mod=0x3 & (XmmReg2 & ZmmReg2))
|
|
{
|
|
XmmResult = vpcompressw_avx512_vbmi2( XmmReg1, XmmOpMask );
|
|
ZmmReg2 = zext(XmmResult);
|
|
}
|
|
|
|
# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124622
|
|
:VPCOMPRESSW m256^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0x63; YmmReg1 ... & m256
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)
|
|
{
|
|
YmmResult = vpcompressw_avx512_vbmi2( YmmReg1, YmmOpMask );
|
|
m256 = YmmResult;
|
|
}
|
|
|
|
# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124624
|
|
# WARNING: duplicate opcode EVEX.256.66.0F38.W1 63 /r last seen on 5-449 PAGE 2273 LINE 124622 for "VPCOMPRESSW ymm1{k1}{z}, ymm2"
|
|
:VPCOMPRESSW YmmReg2^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0x63; YmmReg1 & (mod=0x3 & (YmmReg2 & ZmmReg2))
|
|
{
|
|
YmmResult = vpcompressw_avx512_vbmi2( YmmReg1, YmmOpMask );
|
|
ZmmReg2 = zext(YmmResult);
|
|
}
|
|
|
|
# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124626
|
|
:VPCOMPRESSW m512^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0x63; ZmmReg1 ... & m512
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)
|
|
{
|
|
ZmmResult = vpcompressw_avx512_vbmi2( ZmmReg1, ZmmOpMask );
|
|
m512 = ZmmResult;
|
|
}
|
|
|
|
# VPCOMPRESSB/VCOMPRESSW 5-449 PAGE 2273 LINE 124628
|
|
# WARNING: duplicate opcode EVEX.512.66.0F38.W1 63 /r last seen on 5-449 PAGE 2273 LINE 124626 for "VPCOMPRESSW zmm1{k1}{z}, zmm2"
|
|
:VPCOMPRESSW ZmmReg2^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0x63; ZmmReg1 & (mod=0x3 & ZmmReg2)
|
|
{
|
|
ZmmResult = vpcompressw_avx512_vbmi2( ZmmReg1, ZmmOpMask );
|
|
ZmmReg2 = ZmmResult;
|
|
}
|
|
|
|
# VPDPBUSD 5-459 PAGE 2283 LINE 125092
|
|
define pcodeop vpdpbusd_avx512_vnni ;
|
|
:VPDPBUSD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x50; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vpdpbusd_avx512_vnni( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPDPBUSD 5-459 PAGE 2283 LINE 125097
|
|
:VPDPBUSD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x50; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vpdpbusd_avx512_vnni( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPDPBUSD 5-459 PAGE 2283 LINE 125102
|
|
:VPDPBUSD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x50; ZmmReg1 ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vpdpbusd_avx512_vnni( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPDPBUSDS 5-461 PAGE 2285 LINE 125211
|
|
define pcodeop vpdpbusds_avx512_vnni ;
|
|
:VPDPBUSDS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vpdpbusds_avx512_vnni( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPDPBUSDS 5-461 PAGE 2285 LINE 125217
|
|
:VPDPBUSDS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x51; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vpdpbusds_avx512_vnni( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPDPBUSDS 5-461 PAGE 2285 LINE 125223
|
|
:VPDPBUSDS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x51; ZmmReg1 ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vpdpbusds_avx512_vnni( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPDPWSSD 5-463 PAGE 2287 LINE 125329
|
|
define pcodeop vpdpwssd_avx512_vnni ;
|
|
:VPDPWSSD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x52; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vpdpwssd_avx512_vnni( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPDPWSSD 5-463 PAGE 2287 LINE 125334
|
|
:VPDPWSSD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x52; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vpdpwssd_avx512_vnni( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPDPWSSD 5-463 PAGE 2287 LINE 125339
|
|
:VPDPWSSD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x52; ZmmReg1 ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vpdpwssd_avx512_vnni( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPDPWSSDS 5-465 PAGE 2289 LINE 125436
|
|
define pcodeop vpdpwssds_avx512_vnni ;
|
|
:VPDPWSSDS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x53; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vpdpwssds_avx512_vnni( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPDPWSSDS 5-465 PAGE 2289 LINE 125442
|
|
:VPDPWSSDS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x53; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vpdpwssds_avx512_vnni( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPDPWSSDS 5-465 PAGE 2289 LINE 125448
|
|
:VPDPWSSDS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x53; ZmmReg1 ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vpdpwssds_avx512_vnni( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPERMB 5-471 PAGE 2295 LINE 125727
|
|
define pcodeop vpermb_avx512vl ;
|
|
:VPERMB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8 & evexV5_XmmReg; byte=0x8D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
XmmResult = vpermb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPERMB 5-471 PAGE 2295 LINE 125730
|
|
:VPERMB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8 & evexV5_YmmReg; byte=0x8D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
YmmResult = vpermb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPERMB 5-471 PAGE 2295 LINE 125733
|
|
define pcodeop vpermb_avx512_vbmi ;
|
|
:VPERMB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask8 & evexV5_ZmmReg; byte=0x8D; ZmmReg1 ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
ZmmResult = vpermb_avx512_vbmi( evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPERMI2B 5-476 PAGE 2300 LINE 125958
|
|
define pcodeop vpermi2b_avx512vl ;
|
|
:VPERMI2B XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8 & evexV5_XmmReg; byte=0x75; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
XmmResult = vpermi2b_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPERMI2B 5-476 PAGE 2300 LINE 125961
|
|
:VPERMI2B YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8 & evexV5_YmmReg; byte=0x75; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
YmmResult = vpermi2b_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPERMI2B 5-476 PAGE 2300 LINE 125964
|
|
define pcodeop vpermi2b_avx512_vbmi ;
|
|
:VPERMI2B ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask8 & evexV5_ZmmReg; byte=0x75; ZmmReg1 ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
ZmmResult = vpermi2b_avx512_vbmi( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPERMT2B 5-503 PAGE 2327 LINE 127434
|
|
define pcodeop vpermt2b_avx512vl ;
|
|
:VPERMT2B XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8 & evexV5_XmmReg; byte=0x7D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
XmmResult = vpermt2b_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPERMT2B 5-503 PAGE 2327 LINE 127437
|
|
:VPERMT2B YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8 & evexV5_YmmReg; byte=0x7D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
YmmResult = vpermt2b_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPERMT2B 5-503 PAGE 2327 LINE 127440
|
|
define pcodeop vpermt2b_avx512_vbmi ;
|
|
:VPERMT2B ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask8 & evexV5_ZmmReg; byte=0x7D; ZmmReg1 ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
ZmmResult = vpermt2b_avx512_vbmi( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127524
|
|
define pcodeop vpermt2w_avx512vl ;
|
|
:VPERMT2W XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask16 & evexV5_XmmReg; byte=0x7D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
XmmResult = vpermt2w_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127527
|
|
:VPERMT2W YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask16 & evexV5_YmmReg; byte=0x7D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
YmmResult = vpermt2w_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127530
|
|
define pcodeop vpermt2w_avx512bw ;
|
|
:VPERMT2W ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x7D; ZmmReg1 ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
ZmmResult = vpermt2w_avx512bw( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127533
|
|
define pcodeop vpermt2d_avx512vl ;
|
|
:VPERMT2D XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x7E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vpermt2d_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127536
|
|
:VPERMT2D YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x7E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vpermt2d_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127539
|
|
define pcodeop vpermt2d_avx512f ;
|
|
:VPERMT2D ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x7E; ZmmReg1 ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vpermt2d_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127542
|
|
define pcodeop vpermt2q_avx512vl ;
|
|
:VPERMT2Q XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask64 & evexV5_XmmReg; byte=0x7E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vpermt2q_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127545
|
|
:VPERMT2Q YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask64 & evexV5_YmmReg; byte=0x7E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vpermt2q_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127548
|
|
define pcodeop vpermt2q_avx512f ;
|
|
:VPERMT2Q ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask64 & evexV5_ZmmReg; byte=0x7E; ZmmReg1 ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vpermt2q_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127551
|
|
define pcodeop vpermt2ps_avx512vl ;
|
|
:VPERMT2PS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x7F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vpermt2ps_avx512vl( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127554
|
|
:VPERMT2PS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x7F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vpermt2ps_avx512vl( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPERMT2W/D/Q/PS/PD 5-505 PAGE 2329 LINE 127557
|
|
define pcodeop vpermt2ps_avx512f ;
|
|
:VPERMT2PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x7F; ZmmReg1 ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vpermt2ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPEXPANDB/VPEXPANDW 5-510 PAGE 2334 LINE 127806
|
|
define pcodeop vpexpandb_avx512_vbmi2 ;
|
|
:VPEXPANDB XmmReg1^XmmOpMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0x62; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)
|
|
{
|
|
XmmResult = vpexpandb_avx512_vbmi2( XmmReg2_m128, XmmOpMask );
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPEXPANDB/VPEXPANDW 5-510 PAGE 2334 LINE 127810
|
|
:VPEXPANDB YmmReg1^YmmOpMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0x62; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)
|
|
{
|
|
YmmResult = vpexpandb_avx512_vbmi2( YmmReg2_m256, YmmOpMask );
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPEXPANDB/VPEXPANDW 5-510 PAGE 2334 LINE 127814
|
|
:VPEXPANDB ZmmReg1^ZmmOpMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0x62; ZmmReg1 ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)
|
|
{
|
|
ZmmResult = vpexpandb_avx512_vbmi2( ZmmReg2_m512, ZmmOpMask );
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPEXPANDB/VPEXPANDW 5-510 PAGE 2334 LINE 127818
|
|
define pcodeop vpexpandw_avx512_vbmi2 ;
|
|
:VPEXPANDW XmmReg1^XmmOpMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0x62; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)
|
|
{
|
|
XmmResult = vpexpandw_avx512_vbmi2( XmmReg2_m128, XmmOpMask );
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPEXPANDB/VPEXPANDW 5-510 PAGE 2334 LINE 127822
|
|
:VPEXPANDW YmmReg1^YmmOpMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0x62; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)
|
|
{
|
|
YmmResult = vpexpandw_avx512_vbmi2( YmmReg2_m256, YmmOpMask );
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPEXPANDB/VPEXPANDW 5-510 PAGE 2334 LINE 127826
|
|
:VPEXPANDW ZmmReg1^ZmmOpMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0x62; ZmmReg1 ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 3; ] # (TupleType Tuple1 Scalar)
|
|
{
|
|
ZmmResult = vpexpandw_avx512_vbmi2( ZmmReg2_m512, ZmmOpMask );
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPMADD52HUQ 5-534 PAGE 2358 LINE 128946
|
|
define pcodeop vpmadd52huq_avx512_ifma ;
|
|
:VPMADD52HUQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask64 & evexV5_XmmReg; byte=0xB5; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vpmadd52huq_avx512_ifma( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPMADD52HUQ 5-534 PAGE 2358 LINE 128950
|
|
:VPMADD52HUQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask64 & evexV5_YmmReg; byte=0xB5; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vpmadd52huq_avx512_ifma( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPMADD52HUQ 5-534 PAGE 2358 LINE 128954
|
|
:VPMADD52HUQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask64 & evexV5_ZmmReg; byte=0xB5; ZmmReg1 ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vpmadd52huq_avx512_ifma( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPMADD52LUQ 5-536 PAGE 2360 LINE 129044
|
|
define pcodeop vpmadd52luq_avx512_ifma ;
|
|
:VPMADD52LUQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask64 & evexV5_XmmReg; byte=0xB4; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vpmadd52luq_avx512_ifma( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPMADD52LUQ 5-536 PAGE 2360 LINE 129048
|
|
:VPMADD52LUQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask64 & evexV5_YmmReg; byte=0xB4; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vpmadd52luq_avx512_ifma( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPMADD52LUQ 5-536 PAGE 2360 LINE 129052
|
|
:VPMADD52LUQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask64 & evexV5_ZmmReg; byte=0xB4; ZmmReg1 ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vpmadd52luq_avx512_ifma( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPMULTISHIFTQB 5-571 PAGE 2395 LINE 130845
|
|
define pcodeop vpmultishiftqb_avx512_vbmi ;
|
|
:VPMULTISHIFTQB XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask8 & evexV5_XmmReg; byte=0x83; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vpmultishiftqb_avx512_vbmi( evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPMULTISHIFTQB 5-571 PAGE 2395 LINE 130849
|
|
:VPMULTISHIFTQB YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask8 & evexV5_YmmReg; byte=0x83; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vpmultishiftqb_avx512_vbmi( evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPMULTISHIFTQB 5-571 PAGE 2395 LINE 130853
|
|
:VPMULTISHIFTQB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask8 & evexV5_ZmmReg; byte=0x83; ZmmReg1 ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vpmultishiftqb_avx512_vbmi( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPOPCNT 5-573 PAGE 2397 LINE 130938
|
|
define pcodeop vpopcntb_avx512_bitalg ;
|
|
:VPOPCNTB XmmReg1^XmmOpMask8, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x54; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
XmmResult = vpopcntb_avx512_bitalg( XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask8;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPOPCNT 5-573 PAGE 2397 LINE 130941
|
|
:VPOPCNTB YmmReg1^YmmOpMask8, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x54; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
YmmResult = vpopcntb_avx512_bitalg( YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask8;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPOPCNT 5-573 PAGE 2397 LINE 130944
|
|
:VPOPCNTB ZmmReg1^ZmmOpMask8, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask8; byte=0x54; ZmmReg1 ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
ZmmResult = vpopcntb_avx512_bitalg( ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask8;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPOPCNT 5-573 PAGE 2397 LINE 130947
|
|
define pcodeop vpopcntw_avx512_bitalg ;
|
|
:VPOPCNTW XmmReg1^XmmOpMask16, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask16; byte=0x54; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
XmmResult = vpopcntw_avx512_bitalg( XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPOPCNT 5-573 PAGE 2397 LINE 130950
|
|
:VPOPCNTW YmmReg1^YmmOpMask16, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask16; byte=0x54; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
YmmResult = vpopcntw_avx512_bitalg( YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPOPCNT 5-573 PAGE 2397 LINE 130953
|
|
:VPOPCNTW ZmmReg1^ZmmOpMask16, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask16; byte=0x54; ZmmReg1 ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
ZmmResult = vpopcntw_avx512_bitalg( ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPOPCNT 5-573 PAGE 2397 LINE 130956
|
|
define pcodeop vpopcntd_avx512_vpopcntdq ;
|
|
:VPOPCNTD XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x55; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vpopcntd_avx512_vpopcntdq( XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPOPCNT 5-573 PAGE 2397 LINE 130959
|
|
:VPOPCNTD YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x55; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vpopcntd_avx512_vpopcntdq( YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPOPCNT 5-573 PAGE 2397 LINE 130962
|
|
:VPOPCNTD ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32; byte=0x55; ZmmReg1 ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vpopcntd_avx512_vpopcntdq( ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPOPCNT 5-573 PAGE 2397 LINE 130965
|
|
define pcodeop vpopcntq_avx512_vpopcntdq ;
|
|
:VPOPCNTQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask64; byte=0x55; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vpopcntq_avx512_vpopcntdq( XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPOPCNT 5-573 PAGE 2397 LINE 130968
|
|
:VPOPCNTQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask64; byte=0x55; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vpopcntq_avx512_vpopcntdq( YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPOPCNT 5-573 PAGE 2397 LINE 130971
|
|
:VPOPCNTQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask64; byte=0x55; ZmmReg1 ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vpopcntq_avx512_vpopcntdq( ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPSHLD 5-588 PAGE 2412 LINE 131746
|
|
define pcodeop vpshldw_avx512_vbmi2 ;
|
|
:VPSHLDW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask16 & evexV5_XmmReg; byte=0x70; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
XmmResult = vpshldw_avx512_vbmi2( evexV5_XmmReg, XmmReg2_m128, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPSHLD 5-588 PAGE 2412 LINE 131749
|
|
:VPSHLDW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask16 & evexV5_YmmReg; byte=0x70; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
YmmResult = vpshldw_avx512_vbmi2( evexV5_YmmReg, YmmReg2_m256, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPSHLD 5-588 PAGE 2412 LINE 131752
|
|
:VPSHLDW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x70; ZmmReg1 ... & ZmmReg2_m512; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
ZmmResult = vpshldw_avx512_vbmi2( evexV5_ZmmReg, ZmmReg2_m512, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPSHLD 5-588 PAGE 2412 LINE 131755
|
|
define pcodeop vpshldd_avx512_vbmi2 ;
|
|
:VPSHLDD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x71; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vpshldd_avx512_vbmi2( evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPSHLD 5-588 PAGE 2412 LINE 131758
|
|
:VPSHLDD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x71; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vpshldd_avx512_vbmi2( evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPSHLD 5-588 PAGE 2412 LINE 131761
|
|
:VPSHLDD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x71; ZmmReg1 ... & ZmmReg2_m512_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vpshldd_avx512_vbmi2( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPSHLD 5-588 PAGE 2412 LINE 131764
|
|
define pcodeop vpshldq_avx512_vbmi2 ;
|
|
:VPSHLDQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64 & evexV5_XmmReg; byte=0x71; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vpshldq_avx512_vbmi2( evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPSHLD 5-588 PAGE 2412 LINE 131767
|
|
:VPSHLDQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask64 & evexV5_YmmReg; byte=0x71; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vpshldq_avx512_vbmi2( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPSHLD 5-588 PAGE 2412 LINE 131770
|
|
:VPSHLDQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & ZmmOpMask64 & evexV5_ZmmReg; byte=0x71; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vpshldq_avx512_vbmi2( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPSHLDV 5-591 PAGE 2415 LINE 131888
|
|
define pcodeop vpshldvw_avx512_vbmi2 ;
|
|
:VPSHLDVW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask16 & evexV5_XmmReg; byte=0x70; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
XmmResult = vpshldvw_avx512_vbmi2( XmmReg1, evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPSHLDV 5-591 PAGE 2415 LINE 131891
|
|
:VPSHLDVW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask16 & evexV5_YmmReg; byte=0x70; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
YmmResult = vpshldvw_avx512_vbmi2( YmmReg1, evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPSHLDV 5-591 PAGE 2415 LINE 131894
|
|
:VPSHLDVW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x70; ZmmReg1 ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
ZmmResult = vpshldvw_avx512_vbmi2( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPSHLDV 5-591 PAGE 2415 LINE 131897
|
|
define pcodeop vpshldvd_avx512_vbmi2 ;
|
|
:VPSHLDVD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x71; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vpshldvd_avx512_vbmi2( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPSHLDV 5-591 PAGE 2415 LINE 131900
|
|
:VPSHLDVD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x71; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vpshldvd_avx512_vbmi2( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPSHLDV 5-591 PAGE 2415 LINE 131903
|
|
:VPSHLDVD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x71; ZmmReg1 ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vpshldvd_avx512_vbmi2( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPSHLDV 5-591 PAGE 2415 LINE 131906
|
|
define pcodeop vpshldvq_avx512_vbmi2 ;
|
|
:VPSHLDVQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask64 & evexV5_XmmReg; byte=0x71; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vpshldvq_avx512_vbmi2( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPSHLDV 5-591 PAGE 2415 LINE 131909
|
|
:VPSHLDVQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask64 & evexV5_YmmReg; byte=0x71; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vpshldvq_avx512_vbmi2( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPSHLDV 5-591 PAGE 2415 LINE 131912
|
|
:VPSHLDVQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask64 & evexV5_ZmmReg; byte=0x71; ZmmReg1 ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vpshldvq_avx512_vbmi2( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPSHRD 5-594 PAGE 2418 LINE 132044
|
|
define pcodeop vpshrdw_avx512_vbmi2 ;
|
|
:VPSHRDW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask16 & evexV5_XmmReg; byte=0x72; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
XmmResult = vpshrdw_avx512_vbmi2( evexV5_XmmReg, XmmReg2_m128, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPSHRD 5-594 PAGE 2418 LINE 132047
|
|
:VPSHRDW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask16 & evexV5_YmmReg; byte=0x72; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
YmmResult = vpshrdw_avx512_vbmi2( evexV5_YmmReg, YmmReg2_m256, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPSHRD 5-594 PAGE 2418 LINE 132050
|
|
:VPSHRDW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x72; ZmmReg1 ... & ZmmReg2_m512; imm8
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
ZmmResult = vpshrdw_avx512_vbmi2( evexV5_ZmmReg, ZmmReg2_m512, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPSHRD 5-594 PAGE 2418 LINE 132053
|
|
define pcodeop vpshrdd_avx512_vbmi2 ;
|
|
:VPSHRDD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x73; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vpshrdd_avx512_vbmi2( evexV5_XmmReg, XmmReg2_m128_m32bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPSHRD 5-594 PAGE 2418 LINE 132056
|
|
:VPSHRDD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x73; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vpshrdd_avx512_vbmi2( evexV5_YmmReg, YmmReg2_m256_m32bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPSHRD 5-594 PAGE 2418 LINE 132059
|
|
:VPSHRDD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x73; ZmmReg1 ... & ZmmReg2_m512_m32bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vpshrdd_avx512_vbmi2( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPSHRD 5-594 PAGE 2418 LINE 132062
|
|
define pcodeop vpshrdq_avx512_vbmi2 ;
|
|
:VPSHRDQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64 & evexV5_XmmReg; byte=0x73; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vpshrdq_avx512_vbmi2( evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPSHRD 5-594 PAGE 2418 LINE 132065
|
|
:VPSHRDQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask64 & evexV5_YmmReg; byte=0x73; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vpshrdq_avx512_vbmi2( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPSHRD 5-594 PAGE 2418 LINE 132068
|
|
:VPSHRDQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & ZmmOpMask64 & evexV5_ZmmReg; byte=0x73; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vpshrdq_avx512_vbmi2( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPSHRDV 5-597 PAGE 2421 LINE 132183
|
|
define pcodeop vpshrdvw_avx512_vbmi2 ;
|
|
:VPSHRDVW XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask16 & evexV5_XmmReg; byte=0x72; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
XmmResult = vpshrdvw_avx512_vbmi2( XmmReg1, evexV5_XmmReg, XmmReg2_m128 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPSHRDV 5-597 PAGE 2421 LINE 132186
|
|
:VPSHRDVW YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask16 & evexV5_YmmReg; byte=0x72; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
YmmResult = vpshrdvw_avx512_vbmi2( YmmReg1, evexV5_YmmReg, YmmReg2_m256 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPSHRDV 5-597 PAGE 2421 LINE 132189
|
|
:VPSHRDVW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x72; ZmmReg1 ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
ZmmResult = vpshrdvw_avx512_vbmi2( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPSHRDV 5-597 PAGE 2421 LINE 132192
|
|
define pcodeop vpshrdvd_avx512_vbmi2 ;
|
|
:VPSHRDVD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32 & evexV5_XmmReg; byte=0x73; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vpshrdvd_avx512_vbmi2( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m32bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask32;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPSHRDV 5-597 PAGE 2421 LINE 132195
|
|
:VPSHRDVD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32 & evexV5_YmmReg; byte=0x73; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vpshrdvd_avx512_vbmi2( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m32bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask32;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPSHRDV 5-597 PAGE 2421 LINE 132198
|
|
:VPSHRDVD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32 & evexV5_ZmmReg; byte=0x73; ZmmReg1 ... & ZmmReg2_m512_m32bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vpshrdvd_avx512_vbmi2( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask32;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPSHRDV 5-597 PAGE 2421 LINE 132201
|
|
define pcodeop vpshrdvq_avx512_vbmi2 ;
|
|
:VPSHRDVQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask64 & evexV5_XmmReg; byte=0x73; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vpshrdvq_avx512_vbmi2( XmmReg1, evexV5_XmmReg, XmmReg2_m128_m64bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask64;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VPSHRDV 5-597 PAGE 2421 LINE 132204
|
|
:VPSHRDVQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask64 & evexV5_YmmReg; byte=0x73; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vpshrdvq_avx512_vbmi2( YmmReg1, evexV5_YmmReg, YmmReg2_m256_m64bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask64;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VPSHRDV 5-597 PAGE 2421 LINE 132207
|
|
:VPSHRDVQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask64 & evexV5_ZmmReg; byte=0x73; ZmmReg1 ... & ZmmReg2_m512_m64bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vpshrdvq_avx512_vbmi2( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask64;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VPSHUFBITQMB 5-600 PAGE 2424 LINE 132322
|
|
define pcodeop vpshufbitqmb_avx512_bitalg ;
|
|
:VPSHUFBITQMB KReg_reg^XmmOpMask, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x8F; KReg_reg ... & XmmReg2_m128
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
local tmp:2 = vpshufbitqmb_avx512_bitalg( evexV5_XmmReg, XmmReg2_m128, XmmOpMask );
|
|
KReg_reg = zext(tmp);
|
|
}
|
|
|
|
# VPSHUFBITQMB 5-600 PAGE 2424 LINE 132325
|
|
:VPSHUFBITQMB KReg_reg^YmmOpMask, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask & evexV5_YmmReg; byte=0x8F; KReg_reg ... & YmmReg2_m256
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
local tmp:4 = vpshufbitqmb_avx512_bitalg( evexV5_YmmReg, YmmReg2_m256, YmmOpMask );
|
|
KReg_reg = zext(tmp);
|
|
}
|
|
|
|
# VPSHUFBITQMB 5-600 PAGE 2424 LINE 132328
|
|
:VPSHUFBITQMB KReg_reg^ZmmOpMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask & evexV5_ZmmReg; byte=0x8F; KReg_reg ... & ZmmReg2_m512
|
|
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
|
|
{
|
|
local tmp:8 = vpshufbitqmb_avx512_bitalg( evexV5_ZmmReg, ZmmReg2_m512, ZmmOpMask );
|
|
KReg_reg = zext(tmp);
|
|
}
|
|
|
|
|
|
# VRCPPH 5-646 PAGE 2470 LINE 134707
|
|
define pcodeop vrcpph_avx512fp16 ;
|
|
:VRCPPH XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16; byte=0x4C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vrcpph_avx512fp16( XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VRCPPH 5-646 PAGE 2470 LINE 134710
|
|
:VRCPPH YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16; byte=0x4C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vrcpph_avx512fp16( YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VRCPPH 5-646 PAGE 2470 LINE 134713
|
|
:VRCPPH ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16; byte=0x4C; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vrcpph_avx512fp16( ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VRCPSH 5-648 PAGE 2472 LINE 134789
|
|
define pcodeop vrcpsh_avx512fp16 ;
|
|
:VRCPSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x4D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vrcpsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
|
|
# VREDUCEPH 5-652 PAGE 2476 LINE 134998
|
|
define pcodeop vreduceph_avx512fp16 ;
|
|
:VREDUCEPH XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask16; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vreduceph_avx512fp16( XmmReg2_m128_m16bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VREDUCEPH 5-652 PAGE 2476 LINE 135003
|
|
:VREDUCEPH YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask16; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vreduceph_avx512fp16( YmmReg2_m256_m16bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VREDUCEPH 5-652 PAGE 2476 LINE 135008
|
|
:VREDUCEPH ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & ZmmOpMask16; byte=0x56; ZmmReg1 ... & ZmmReg2_m512_m16bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vreduceph_avx512fp16( ZmmReg2_m512_m16bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VREDUCESH 5-659 PAGE 2483 LINE 135336
|
|
define pcodeop vreducesh_avx512fp16 ;
|
|
:VREDUCESH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16, imm8 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16; imm8
|
|
{
|
|
XmmResult = vreducesh_avx512fp16( evexV5_XmmReg, XmmReg2_m16, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VRNDSCALEPH 5-666 PAGE 2490 LINE 135677
|
|
define pcodeop vrndscaleph_avx512fp16 ;
|
|
:VRNDSCALEPH XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask16; byte=0x08; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vrndscaleph_avx512fp16( XmmReg2_m128_m16bcst, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VRNDSCALEPH 5-666 PAGE 2490 LINE 135681
|
|
:VRNDSCALEPH YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask16; byte=0x08; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst; imm8
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vrndscaleph_avx512fp16( YmmReg2_m256_m16bcst, imm8:1 );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
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# VRNDSCALEPH 5-666 PAGE 2490 LINE 135685
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:VRNDSCALEPH ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & ZmmOpMask16; byte=0x08; ZmmReg1 ... & ZmmReg2_m512_m16bcst; imm8
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[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vrndscaleph_avx512fp16( ZmmReg2_m512_m16bcst, imm8:1 );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
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|
}
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# VRNDSCALESH 5-674 PAGE 2498 LINE 136097
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define pcodeop vrndscalesh_avx512fp16 ;
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:VRNDSCALESH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16, imm8 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_NONE) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x0A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16; imm8
|
|
{
|
|
XmmResult = vrndscalesh_avx512fp16( evexV5_XmmReg, XmmReg2_m16, imm8:1 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
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|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
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ZmmReg1 = zext(XmmResult);
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|
}
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# VRSQRTPH 5-686 PAGE 2510 LINE 136692
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define pcodeop vrsqrtph_avx512fp16 ;
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:VRSQRTPH XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16; byte=0x4E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vrsqrtph_avx512fp16( XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
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|
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# VRSQRTPH 5-686 PAGE 2510 LINE 136696
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:VRSQRTPH YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16; byte=0x4E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vrsqrtph_avx512fp16( YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VRSQRTPH 5-686 PAGE 2510 LINE 136700
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|
:VRSQRTPH ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16; byte=0x4E; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vrsqrtph_avx512fp16( ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VRSQRTSH 5-688 PAGE 2512 LINE 136781
|
|
define pcodeop vrsqrtsh_avx512fp16 ;
|
|
:VRSQRTSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x4F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vrsqrtsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VSCALEFPH 5-692 PAGE 2516 LINE 136971
|
|
define pcodeop vscalefph_avx512fp16 ;
|
|
:VSCALEFPH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x2C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vscalefph_avx512fp16( evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VSCALEFPH 5-692 PAGE 2516 LINE 136974
|
|
:VSCALEFPH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x2C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vscalefph_avx512fp16( evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VSCALEFPH 5-692 PAGE 2516 LINE 136977
|
|
:VSCALEFPH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x2C; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vscalefph_avx512fp16( evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VSCALEFSH 5-699 PAGE 2523 LINE 137301
|
|
define pcodeop vscalefsh_avx512fp16 ;
|
|
:VSCALEFSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_66) & $(VEX_MAP6) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x2D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vscalefsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VSQRTPH 5-712 PAGE 2536 LINE 137925
|
|
define pcodeop vsqrtph_avx512fp16 ;
|
|
:VSQRTPH XmmReg1^XmmOpMask16, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vsqrtph_avx512fp16( XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VSQRTPH 5-712 PAGE 2536 LINE 137928
|
|
:VSQRTPH YmmReg1^YmmOpMask16, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16; byte=0x51; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vsqrtph_avx512fp16( YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VSQRTPH 5-712 PAGE 2536 LINE 137931
|
|
:VSQRTPH ZmmReg1^ZmmOpMask16, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16; byte=0x51; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vsqrtph_avx512fp16( ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VSQRTSH 5-714 PAGE 2538 LINE 138003
|
|
define pcodeop vsqrtsh_avx512fp16 ;
|
|
:VSQRTSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult[0,16] = sqrt(XmmReg2_m16[0,16]);
|
|
XmmMask = XmmReg1;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = evexV5_XmmReg[16,112]; # DEST[127:16] = src1[127:16]
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VSUBPH 5-715 PAGE 2539 LINE 138057
|
|
define pcodeop vsubph_avx512fp16 ;
|
|
:VSUBPH XmmReg1^XmmOpMask16, evexV5_XmmReg, XmmReg2_m128_m16bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask16 & evexV5_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
XmmResult = vsubph_avx512fp16( evexV5_XmmReg, XmmReg2_m128_m16bcst );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask16;
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VSUBPH 5-715 PAGE 2539 LINE 138060
|
|
:VSUBPH YmmReg1^YmmOpMask16, evexV5_YmmReg, YmmReg2_m256_m16bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & YmmOpMask16 & evexV5_YmmReg; byte=0x5C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
YmmResult = vsubph_avx512fp16( evexV5_YmmReg, YmmReg2_m256_m16bcst );
|
|
YmmMask = YmmReg1;
|
|
build YmmOpMask16;
|
|
ZmmReg1 = zext(YmmResult);
|
|
}
|
|
|
|
# VSUBPH 5-715 PAGE 2539 LINE 138063
|
|
:VSUBPH ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512_m16bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0) & ZmmOpMask16 & evexV5_ZmmReg; byte=0x5C; ZmmReg1 ... & ZmmReg2_m512_m16bcst
|
|
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
|
|
{
|
|
ZmmResult = vsubph_avx512fp16( evexV5_ZmmReg, ZmmReg2_m512_m16bcst );
|
|
ZmmMask = ZmmReg1;
|
|
build ZmmOpMask16;
|
|
ZmmReg1 = ZmmResult;
|
|
}
|
|
|
|
# VSUBSH 5-717 PAGE 2541 LINE 138152
|
|
define pcodeop vsubsh_avx512fp16 ;
|
|
:VSUBSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
XmmResult = vsubsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );
|
|
XmmMask = XmmReg1;
|
|
build XmmOpMask;
|
|
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
|
|
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
|
|
ZmmReg1 = zext(XmmResult);
|
|
}
|
|
|
|
# VUCOMISH 5-721 PAGE 2545 LINE 138358
|
|
define pcodeop vucomish_avx512fp16 ;
|
|
:VUCOMISH XmmReg1, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_NONE) & $(VEX_MAP5) & $(VEX_W0); byte=0x2E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
local tmp:16 = vucomish_avx512fp16( XmmReg2_m16 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|