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352 lines
10 KiB
Plaintext
352 lines
10 KiB
Plaintext
# sleigh specification file for Intel 8048
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# Do not take BS into account when decompiling
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@define SINGLE_REGISTER_BANK ""
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# Treat R0-R7 as not memory mapped (implies SINGLE_REGISTER_BANK)
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@define INTERNAL_REGISTERS ""
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@ifdef INTERNAL_REGISTERS
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@define SINGLE_REGISTER_BANK ""
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@endif
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define endian=little;
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define alignment=1;
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define space CODE type=ram_space size=2 default;
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define space INTMEM type=ram_space size=1;
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define space EXTMEM type=ram_space size=1;
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define space PORT type=ram_space size=1;
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define space register type=register_space size=1;
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define register offset=0x00 size=1 [ A SP ];
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@ifdef INTERNAL_REGISTERS
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define register offset=0x10 size=1 [ R0 R1 R2 R3 R4 R5 R6 R7 ];
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@endif
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define register offset=0x20 size=2 [ PC ];
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define register offset=0x30 size=1 [ C AC F0 F1 BS DFB ]; # single bit
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################################################################
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# Tokens
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################################################################
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define token opbyte (8)
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opfull = (0,7)
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oplo = (0,3)
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ophi = (4,7)
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rn = (0,2) dec
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rnfill = (3,3)
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ri = (0,0) dec
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rifill = (1,3)
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opaddr = (5,7)
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addrfill = (4,4)
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pp = (0,1) dec
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xpp = (0,1) dec
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ppfill = (2,3)
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abit = (5,7) dec
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abfill = (4,4)
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dfb = (4,4)
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bs = (4,4)
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;
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define token aopword (16)
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aoplo = (0,3)
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aaddrfill = (4,4)
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aopaddr = (5,7)
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adata = (8,15)
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;
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define token ImmedByte (8) data=(0,7);
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define token AddrOne (8) addr8=(0,7);
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@ifdef INTERNAL_REGISTERS
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attach variables rn [ R0 R1 R2 R3 R4 R5 R6 R7 ];
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attach variables ri [ R0 R1 ];
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@else
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attach names rn [ R0 R1 R2 R3 R4 R5 R6 R7 ];
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attach names ri [ R0 R1 ];
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@endif
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attach names dfb [ MB0 MB1 ];
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attach names bs [ RB0 RB1 ];
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attach names pp [ BUS P1 P2 _ ];
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attach names xpp [ P4 P5 P6 P7 ];
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################################################################
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# Psuedo Instructions
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################################################################
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define pcodeop nop;
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define pcodeop enableExtInt;
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define pcodeop enableTCntInt;
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define pcodeop enableClockOutput;
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define pcodeop disableExtInt;
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define pcodeop disableTCntInt;
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define pcodeop startTimer;
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define pcodeop startEventCounter;
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define pcodeop stopTimerAndEventCounter;
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define pcodeop setTmr;
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define pcodeop getTmr;
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define pcodeop getT0;
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define pcodeop getT1;
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define pcodeop getTF;
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define pcodeop getExtInt;
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define pcodeop readPort;
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define pcodeop writePort;
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define pcodeop setBank;
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################################################################
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# Macros
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################################################################
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macro getPSW(reg) {
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local tmp:1 = 0;
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tmp[7,1] = C;
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tmp[6,1] = AC;
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tmp[5,1] = F0;
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tmp[4,1] = BS;
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tmp[3,1] = 1;
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tmp[0,3] = (SP>>1)&7;
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reg = tmp;
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}
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macro setPSW(reg) {
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local tmp:1 = reg;
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C = tmp[7,1];
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AC = tmp[6,1];
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F0 = tmp[5,1];
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BS = tmp[4,1];
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SP = 2*tmp[0,3] + 8;
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}
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macro savePSWtoPC(pc) {
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pc[15,1] = C;
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pc[14,1] = AC;
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pc[13,1] = F0;
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pc[12,1] = BS;
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}
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macro restorePSWfromPC(pc) {
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C = pc[15,1];
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AC = pc[14,1];
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F0 = pc[13,1];
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BS = pc[12,1];
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}
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macro push(v) {
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*[INTMEM]:2 SP = v;
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SP = SP + 2;
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}
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macro pop(v) {
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SP = SP - 2;
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v = *[INTMEM]:2 SP;
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}
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macro popPC(pc) {
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pop(pc);
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pc = pc & 0xfff;
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}
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macro popPCandPSW(pc) {
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pop(pc);
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restorePSWfromPC(pc);
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pc = pc & 0xfff;
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}
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macro funcall(target) {
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ret:2 = inst_next;
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savePSWtoPC(ret);
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push(ret);
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call target;
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}
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macro add(dest, op1, op2, cy_in) {
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local result:1 = op1 + op2 + cy_in;
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local half_result:1 = (op1 & 0xf) + (op2 & 0xf) + cy_in;
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C = carry(op1, op2) || carry(op1+op2, cy_in);
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AC = (half_result > 0xf);
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dest = result;
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}
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macro da(reg) {
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local tmp:1 = reg;
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local low:1 = 6*(AC || (tmp&0xf) > 9);
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local cy1:1 = C || carry(tmp, low);
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tmp = tmp + low;
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local high:1 = 0x60*(cy1 || tmp > 0x99);
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C = C || carry(tmp, high);
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tmp = tmp + high;
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reg = tmp;
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}
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macro rotc(cy, acc) {
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local tmp:1 = cy;
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A = acc;
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C = tmp;
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}
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macro xch(node1, node2) {
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local tmp:1 = node1;
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node1 = node2;
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node2 = tmp;
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}
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@ifdef SINGLE_REGISTER_BANK
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macro regbank(r) { }
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macro setbank(bs) {
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BS = bs;
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local tmp:1 = bs;
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setBank(tmp);
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}
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@else
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macro regbank(r) {
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r = r + BS*0x18;
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}
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macro setbank(bs) {
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BS = bs;
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}
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@endif
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################################################################
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Psw: "PSW" is epsilon { }
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ExtInt: "I" is epsilon { }
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TCntInt: "TCNTI" is epsilon { }
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Clk: "CLK" is epsilon { }
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Tmr: "T" is epsilon { }
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Cnt: "CNT" is epsilon { }
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TmrCnt: "TCNT" is epsilon { }
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Rn: rn is rn & rnfill=1 {
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@ifdef INTERNAL_REGISTERS
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export rn;
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@else
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local ptr:1 = rn; regbank(ptr); export *[INTMEM]:1 ptr;
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@endif
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}
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Rind: @ri is ri & rifill=0 {
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@ifdef INTERNAL_REGISTERS
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export ri;
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@else
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local ptr:1 = ri; regbank(ptr); export *[INTMEM]:1 ptr;
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@endif
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}
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Ri: Rind is Rind { export *[INTMEM]:1 Rind; }
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RiX: Rind is Rind { export *[EXTMEM]:1 Rind; }
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PData: @A is A {
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local addr:2 = inst_next; addr[0,7] = A; export *[CODE]:1 addr; }
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P3Data: @A is A {
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local addr:2 = 0x300; addr[0,7] = A; export *[CODE]:1 addr; }
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AddrInd: PData is PData {
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local addr:2 = inst_next; addr[0,7] = PData; export *[CODE]:1 addr; }
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Ab: abit is abit { local bit:1 = (A>>abit)&1; export bit; }
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Data: #data is data { export *[const]:1 data; }
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Imm: Data is oplo=3; Data { export Data; }
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Addr8: addr is addr8 [ addr = (inst_next $and 0xf00)+addr8; ] {
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export *[CODE]:1 addr; }
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Addr12: addr is aopaddr & adata [ addr = (DFB*2048)+(aopaddr*256)+adata; ] {
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export *[CODE]:1 addr; }
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Bus: "BUS" is epsilon { local tmp:1 = 0; export *[PORT]:1 tmp; }
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Pp: pp is pp & ppfill=2 { export *[PORT]:1 pp; }
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Xpp: xpp is xpp & ppfill=3 { local tmp:1 = xpp+4; export *[PORT]:1 tmp; }
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Cc: "C" is ophi=15 { export C; }
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Cc: "F0" is ophi=11 { export F0; }
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Cc: "F1" is ophi=7 { export F1; }
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Cc: "NC" is ophi=14 { tmp:1 = !C; export tmp; }
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Cc: "NI" is ophi=8 { tmp:1 = getExtInt(); tmp = !tmp; export tmp; }
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Cc: "NT0" is ophi=2 { tmp:1 = getT0(); tmp = !tmp; export tmp; }
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Cc: "NT1" is ophi=4 { tmp:1 = getT1(); tmp = !tmp; export tmp; }
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Cc: "NZ" is ophi=9 { tmp:1 = A!=0; export tmp; }
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Cc: "TF" is ophi=1 { tmp:1 = getTF(); export tmp; }
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Cc: "T0" is ophi=3 { tmp:1 = getT0(); export tmp; }
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Cc: "T1" is ophi=5 { tmp:1 = getT1(); export tmp; }
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Cc: "Z" is ophi=12 { tmp:1 = A==0; export tmp; }
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# Conventience tables for opcodes taking both Rn and Ri (and Imm)
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Rni: Rn is Rn { export Rn; }
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Rni: Ri is Ri { export Ri; }
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RniI: Rni is Rni { export Rni; }
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RniI: Imm is Imm { export Imm; }
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# These are not decoded correctly if placed alphabetically...
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:JB^Ab Addr8 is oplo=2 & abfill=1 & Ab; Addr8 { if(Ab) goto Addr8; }
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:J^Cc Addr8 is oplo=6 & Cc; Addr8 { if(Cc) goto Addr8; }
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:CALL Addr12 is aaddrfill=1 & aoplo=4 & Addr12 { funcall(Addr12); }
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:JMP Addr12 is aaddrfill=0 & aoplo=4 & Addr12 { goto Addr12; }
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:DJNZ Rn,Addr8 is ophi=14 & Rn; Addr8 { Rn = Rn - 1; if(Rn != 0) goto Addr8; }
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:ADD A,Rni is ophi=6 & A & Rni { add(A,A,Rni,0); }
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:ADD A,Imm is (ophi=0 & A)... & Imm { add(A,A,Imm,0); }
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:ADDC A,Rni is ophi=7 & A & Rni { add(A,A,Rni,C); }
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:ADDC A,Imm is (ophi=1 & A)... & Imm { add(A,A,Imm,C); }
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:ANL A,RniI is (ophi=5 & A)... & RniI { A = A & RniI; }
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:ANL Pp,Data is ophi=9 & Pp; Data { Pp = Pp & Data; }
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:ANLD Xpp,A is ophi=9 & Xpp & A { Xpp = Xpp & (A & 0xf); }
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:CLR A is ophi=2 & oplo=7 & A { A = 0; }
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:CLR C is ophi=9 & oplo=7 & C { C = 0; }
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:CLR F0 is ophi=8 & oplo=5 & F0 { F0 = 0; }
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:CLR F1 is ophi=10 & oplo=5 & F1 { F1 = 0; }
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:CPL A is ophi=3 & oplo=7 & A { A = ~A; }
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:CPL C is ophi=10 & oplo=7 & C { C = !C; }
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:CPL F0 is ophi=9 & oplo=5 & F0 { F0 = !F0; }
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:CPL F1 is ophi=11 & oplo=5 & F1 { F1 = !F1; }
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:DA A is ophi=5 & oplo=7 & A { da(A); }
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:DEC A is ophi=0 & oplo=7 & A { A = A - 1; }
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:DEC Rn is ophi=12 & Rn { Rn = Rn - 1; }
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:DIS ExtInt is ophi=1 & oplo=5 & ExtInt { disableExtInt(); }
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:DIS TCntInt is ophi=3 & oplo=5 & TCntInt { disableTCntInt(); }
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:EN ExtInt is ophi=0 & oplo=5 & ExtInt { enableExtInt(); }
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:EN TCntInt is ophi=2 & oplo=5 & TCntInt { enableTCntInt(); }
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:ENT0 Clk is ophi=7 & oplo=5 & Clk { enableClockOutput(); }
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:IN A,Pp is ophi=0 & pp!=0 & A & Pp { A = Pp; }
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:INC A is ophi=1 & oplo=7 & A { A = A + 1; }
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:INC Rni is ophi=1 & Rni { Rni = Rni + 1; }
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:INS A,Bus is ophi=0 & oplo=8 & A & Bus { A = Bus; }
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:JMPP AddrInd is ophi=11 & oplo=3 & AddrInd { goto AddrInd; }
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:MOV A,Imm is (ophi=2 & A)... & Imm { A = Imm; }
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:MOV A,Psw is ophi=12 & oplo=7 & A & Psw { getPSW(A); }
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:MOV A,Rni is ophi=15 & A & Rni { A = Rni; }
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:MOV A,Tmr is ophi=4 & oplo=2 & A & Tmr { A = getTmr(); }
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:MOV Psw,A is ophi=13 & oplo=7 & Psw & A { setPSW(A); }
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:MOV Rni,A is ophi=10 & Rni & A { Rni = A; }
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:MOV Rni,Data is ophi=11 & Rni; Data { Rni = Data; }
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:MOV Tmr,A is ophi=6 & oplo=2 & Tmr & A { setTmr(A); }
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:MOVD A,Xpp is ophi=0 & Xpp & A { A = (Xpp & 0xf); }
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:MOVD Xpp,A is ophi=3 & Xpp & A { Xpp = (A & 0xf); }
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:MOVP A,PData is ophi=10 & oplo=3 & A & PData { A = PData; }
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:MOVP3 A,P3Data is ophi=14 & oplo=3 & A & P3Data { A = P3Data; }
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:MOVX A,RiX is ophi=8 & A & RiX { A = RiX; }
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:MOVX RiX,A is ophi=9 & RiX & A { RiX = A; }
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:NOP is ophi=0 & oplo=0 { nop(); }
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:ORL A,RniI is (ophi=4 & A)... & RniI { A = A | RniI; }
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:ORL Pp,Data is ophi=8 & Pp; Data { Pp = Pp | Data; }
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:ORLD Xpp,A is ophi=8 & Xpp & A { Xpp = Xpp | (A & 0xf); }
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:OUTL Bus,A is ophi=0 & oplo=2 & Bus & A { Bus = A; }
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:OUTL Pp,A is ophi=3 & pp!=0 & Pp & A { Pp = A; }
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:RET is ophi=8 & oplo=3 { pc:2 = 0; popPC(pc); return[pc]; }
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:RETR is ophi=9 & oplo=3 { pc:2 = 0; popPCandPSW(pc); return[pc]; }
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:RL A is ophi=14 & oplo=7 & A { A = (A<<1) | (A>>7); }
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:RLC A is ophi=15 & oplo=7 & A { rotc((A&0x80)>>7, (A<<1)|C); }
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:RR A is ophi=7 & oplo=7 & A { A = (A>>1) | (A<<7); }
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:RRC A is ophi=6 & oplo=7 & A { rotc(A&1, (A>>1)|(C<<7)); }
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:SEL dfb is (ophi=14 | ophi=15) & oplo=5 & dfb { DFB = dfb; }
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:SEL bs is (ophi=12 | ophi=13) & oplo=5 & bs { setbank(bs); }
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:STOP TmrCnt is ophi=6 & oplo=5 & TmrCnt { stopTimerAndEventCounter(); }
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:STRT Cnt is ophi=4 & oplo=5 & Cnt { startEventCounter(); }
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:STRT Tmr is ophi=5 & oplo=5 & Tmr { startTimer(); }
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:SWAP A is ophi=4 & oplo=7 & A { A = (A<<4)|(A>>4); }
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:XCH A,Rni is ophi=2 & A & Rni { xch(A, Rni); }
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:XCHD A,Ri is ophi=3 & A & Ri { xch(A[0,4], Ri[0,4]); }
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:XRL A,RniI is (ophi=13 & A)... & RniI { A = A ^ RniI; }
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