mirror of
https://github.com/NationalSecurityAgency/ghidra.git
synced 2026-09-19 16:40:38 -09:00
The scalar FMADD and FMSUB constructors (FPR16/FPR32/FPR64) wrote only the result element and left the upper bits of the destination SIMD&FP register unchanged, violating the architectural zero-extension-on-write semantics. The sibling FNMADD/FNMSUB already do this correctly. Add the size-correct zero-extension after each: - FPR16 -> zext_zh - FPR32 -> zext_zs - FPR64 -> zext_zd