mirror of
https://github.com/NationalSecurityAgency/ghidra.git
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349ef0fad2
Imposed default Thumb context setting for PE and MSCoff ARM32 imports with addition of v8T ARM variant. Corrected ARM pattern alignment issues. Corrected DBViewer long value rendering.
65 lines
3.2 KiB
XML
65 lines
3.2 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<processor_spec>
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<!-- THIS PSPEC IS A COPY OF ARMt.pspec AND ONLY DIFFERS WITH ENABLEMENT OF THUMB AS DEFAULT CONTEXT -->
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<properties>
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<property key="addressesDoNotAppearDirectlyInCode" value="true"/>
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<property key="allowOffcutReferencesToFunctionStarts" value="true"/>
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<property key="useNewFunctionStackAnalysis" value="true"/>
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<property key="emulateInstructionStateModifierClass" value="ghidra.program.emulation.ARMEmulateInstructionStateModifier"/>
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<property key="assemblyRating:ARM:BE:32:v7" value="PLATINUM"/>
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<property key="assemblyRating:ARM:LE:32:v7" value="PLATINUM"/>
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</properties>
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<programcounter register="pc"/>
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<context_data>
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<context_set space="ram">
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<set name="TMode" val="1" description="0 for ARM 32-bit, 1 for THUMB 16-bit"/>
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<set name="LRset" val="0" description="0 lr reg not set, 1 for LR set, affects BX as a call"/>
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</context_set>
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<tracked_set space="ram">
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<set name="spsr" val="0"/>
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</tracked_set>
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</context_data>
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<default_symbols>
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<symbol name="Reset" address="ram:0x0" entry="true"/>
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<symbol name="UndefinedInstruction" address="ram:0x4" entry="true"/>
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<symbol name="SupervisorCall" address="ram:0x8" entry="true"/>
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<symbol name="PrefetchAbort" address="ram:0xC" entry="true"/>
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<symbol name="DataAbort" address="ram:0x10" entry="true"/>
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<symbol name="NotUsed" address="ram:0x14" entry="true"/>
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<symbol name="IRQ" address="ram:0x18" entry="true"/>
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<symbol name="FIQ" address="ram:0x1c" entry="true"/>
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<symbol name="H_Reset" address="ram:0xFFFF0000" entry="true"/>
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<symbol name="H_UndefinedInstruction" address="ram:0xFFFF0004" entry="true"/>
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<symbol name="H_SupervisorCall" address="ram:0xFFFF0008" entry="true"/>
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<symbol name="H_PrefetchAbort" address="ram:0xFFFF000C" entry="true"/>
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<symbol name="H_DataAbort" address="ram:0xFFFF0010" entry="true"/>
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<symbol name="H_NotUsed" address="ram:0xFFFF0014" entry="true"/>
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<symbol name="H_IRQ" address="ram:0xFFFF0018" entry="true"/>
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<symbol name="H_FIQ" address="ram:0xFFFF001c" entry="true"/>
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</default_symbols>
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<register_data>
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<register name="q0" group="NEON" vector_lane_sizes="1,2,4"/>
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<register name="q1" group="NEON" vector_lane_sizes="1,2,4"/>
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<register name="q2" group="NEON" vector_lane_sizes="1,2,4"/>
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<register name="q3" group="NEON" vector_lane_sizes="1,2,4"/>
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<register name="q4" group="NEON" vector_lane_sizes="1,2,4"/>
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<register name="q5" group="NEON" vector_lane_sizes="1,2,4"/>
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<register name="q6" group="NEON" vector_lane_sizes="1,2,4"/>
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<register name="q7" group="NEON" vector_lane_sizes="1,2,4"/>
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<register name="q8" group="NEON" vector_lane_sizes="1,2,4"/>
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<register name="q9" group="NEON" vector_lane_sizes="1,2,4"/>
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<register name="q10" group="NEON" vector_lane_sizes="1,2,4"/>
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<register name="q11" group="NEON" vector_lane_sizes="1,2,4"/>
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<register name="q12" group="NEON" vector_lane_sizes="1,2,4"/>
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<register name="q13" group="NEON" vector_lane_sizes="1,2,4"/>
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<register name="q14" group="NEON" vector_lane_sizes="1,2,4"/>
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<register name="q15" group="NEON" vector_lane_sizes="1,2,4"/>
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</register_data>
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</processor_spec>
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