mirror of
https://github.com/NationalSecurityAgency/ghidra.git
synced 2026-09-19 16:40:38 -09:00
b16f1556d2
Specifically: * ARPL uses CF instead of ZF for conditional RPL adjustment * DAA/DAS incorrect CF computation and missing result flags * SHR by-1 OF flag unconditionally set to 0 * RDTSCP incorrectly restricted to 64-bit mode only * SYSEXIT uses wrong register mapping * FCMOVNBE condition logic error * FYL2X/FYL2XP1 missing log2 computation * CVTPD2DQ uses trunc() instead of round() * SUBB MMX missing byte lane [8,8] * PSLLD/PSLLQ XMM use per-element shift count * PCMPxSTRx missing implicit EAX/EDX inputs and EFLAGS outputs * CET WRSSQ/WRUSSQ duplicate 0x0F byte in encoding * FMA VEX_W0 missing on PS YMM 231-form constructors * VTESTPS YMM sign bit offset errors * AVX-512 VANDPS YMM dead variable * AVX-512 VMOVHLPS copies src2 to both halves * AVX-512 VMOVHPD load form dead variable * VPSUBSW ZMM form multiple errors * CVTPD2PI uses trunc() instead of round() * PSRAD XMM uses full 128-bit shift count * VMULPS YMM missing 8th element * FPREM/FPREM1 broken remainder computation * FDECSTP clears wrong condition code bit * VMCLEAR incorrectly restricted to 64-bit mode * SYSCALL does not model RCX and R11 clobber * VRANGESS missing imm8 operand * VFPCLASSSD/VFPCLASSSS missing imm8 operand * AVX-512 VUCOMISD/VUCOMISS missing EFLAGS computation * MASKMOVDQU incorrectly assigns to XmmReg1 * DAS has same CF computation and missing flags issues as DAA * XGETBV/XSETBV ignore ECX selector
3178 lines
126 KiB
Plaintext
3178 lines
126 KiB
Plaintext
# INFO This file automatically generated by andre on Tue Apr 30 15:35:00 2024
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# INFO Direct edits to this file may be lost in future updates
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# INFO Command line arguments: ['--sinc', '--skip-sinc', '../../../../../../../ghidra/Ghidra/Processors/x86/data/languages/avx_manual.sinc', '../../../../../../../ghidra/Ghidra/Processors/x86/data/languages/ia.sinc']
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# ADDPD 3-33 PAGE 603 LINE 33405
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:VADDPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
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{
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local m:16 = XmmReg2_m128;
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XmmReg1[0,64] = vexVVVV_XmmReg[0,64] f+ m[0,64];
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XmmReg1[64,64] = vexVVVV_XmmReg[64,64] f+ m[64,64];
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ZmmReg1 = zext(XmmReg1);
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}
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# ADDPD 3-33 PAGE 603 LINE 33408
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:VADDPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x58; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
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{
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local m:32 = YmmReg2_m256;
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YmmReg1[0,64] = vexVVVV_YmmReg[0,64] f+ m[0,64];
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YmmReg1[64,64] = vexVVVV_YmmReg[64,64] f+ m[64,64];
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YmmReg1[128,64] = vexVVVV_YmmReg[128,64] f+ m[128,64];
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YmmReg1[192,64] = vexVVVV_YmmReg[192,64] f+ m[192,64];
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ZmmReg1 = zext(YmmReg1);
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}
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# ADDPS 3-36 PAGE 606 LINE 33558
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:VADDPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
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{
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local tmp:16 = XmmReg2_m128;
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XmmReg1[0,32] = vexVVVV_XmmReg[0,32] f+ tmp[0,32];
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XmmReg1[32,32] = vexVVVV_XmmReg[32,32] f+ tmp[32,32];
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XmmReg1[64,32] = vexVVVV_XmmReg[64,32] f+ tmp[64,32];
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XmmReg1[96,32] = vexVVVV_XmmReg[96,32] f+ tmp[96,32];
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ZmmReg1 = zext(XmmReg1);
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}
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# ADDPS 3-36 PAGE 606 LINE 33560
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:VADDPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x58; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
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{
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local tmp:32 = YmmReg2_m256;
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YmmReg1[0,32] = vexVVVV_YmmReg[0,32] f+ tmp[0,32];
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YmmReg1[32,32] = vexVVVV_YmmReg[32,32] f+ tmp[32,32];
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YmmReg1[64,32] = vexVVVV_YmmReg[64,32] f+ tmp[64,32];
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YmmReg1[96,32] = vexVVVV_YmmReg[96,32] f+ tmp[96,32];
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YmmReg1[128,32] = vexVVVV_YmmReg[128,32] f+ tmp[128,32];
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YmmReg1[160,32] = vexVVVV_YmmReg[160,32] f+ tmp[160,32];
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YmmReg1[192,32] = vexVVVV_YmmReg[192,32] f+ tmp[192,32];
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YmmReg1[224,32] = vexVVVV_YmmReg[224,32] f+ tmp[224,32];
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ZmmReg1 = zext(YmmReg1);
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}
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# ADDSD 3-39 PAGE 609 LINE 33718
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:VADDSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
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{
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local tmp:8 = vexVVVV_XmmReg[0,64] f+ XmmReg2_m64[0,64];
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ZmmReg1 = zext(tmp);
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}
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# ADDSS 3-41 PAGE 611 LINE 33812
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:VADDSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
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{
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local tmp:4 = vexVVVV_XmmReg[0,32] f+ XmmReg2_m32[0,32];
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ZmmReg1 = zext(tmp);
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}
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# ADDSUBPD 3-43 PAGE 613 LINE 33906
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define pcodeop vaddsubpd_avx ;
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:VADDSUBPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD0; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
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{
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local tmp:16 = vaddsubpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
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ZmmReg1 = zext(tmp);
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}
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# ADDSUBPD 3-43 PAGE 613 LINE 33909
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:VADDSUBPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD0; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
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{
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local tmp:32 = vaddsubpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );
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ZmmReg1 = zext(tmp);
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}
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# ADDSUBPS 3-45 PAGE 615 LINE 34013
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define pcodeop vaddsubps_avx ;
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:VADDSUBPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD0; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
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{
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local tmp:16 = vaddsubps_avx( vexVVVV_XmmReg, XmmReg2_m128 );
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ZmmReg1 = zext(tmp);
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}
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# ADDSUBPS 3-45 PAGE 615 LINE 34016
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:VADDSUBPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD0; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
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{
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local tmp:32 = vaddsubps_avx( vexVVVV_YmmReg, YmmReg2_m256 );
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ZmmReg1 = zext(tmp);
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}
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# ANDPD 3-64 PAGE 634 LINE 34821
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define pcodeop vandpd_avx ;
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:VANDPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
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{
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local tmp:16 = vandpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
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ZmmReg1 = zext(tmp);
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}
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# ANDPD 3-64 PAGE 634 LINE 34824
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:VANDPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
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{
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local tmp:32 = vandpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );
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ZmmReg1 = zext(tmp);
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}
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# ANDPS 3-67 PAGE 637 LINE 34947
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define pcodeop vandps_avx ;
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:VANDPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
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{
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local tmp:16 = vandps_avx( vexVVVV_XmmReg, XmmReg2_m128 );
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ZmmReg1 = zext(tmp);
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}
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# ANDPS 3-67 PAGE 637 LINE 34950
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:VANDPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
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{
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local tmp:32 = vandps_avx( vexVVVV_YmmReg, YmmReg2_m256 );
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ZmmReg1 = zext(tmp);
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}
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# ANDNPD 3-70 PAGE 640 LINE 35081
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define pcodeop vandnpd_avx ;
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:VANDNPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
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{
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local tmp:16 = vandnpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
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ZmmReg1 = zext(tmp);
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}
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# ANDNPD 3-70 PAGE 640 LINE 35084
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:VANDNPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x55; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
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{
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local tmp:32 = vandnpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );
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ZmmReg1 = zext(tmp);
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}
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# ANDNPS 3-73 PAGE 643 LINE 35207
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define pcodeop vandnps_avx ;
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:VANDNPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
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{
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local tmp:16 = vandnps_avx( vexVVVV_XmmReg, XmmReg2_m128 );
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ZmmReg1 = zext(tmp);
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}
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# ANDNPS 3-73 PAGE 643 LINE 35210
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:VANDNPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x55; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
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{
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local tmp:32 = vandnps_avx( vexVVVV_YmmReg, YmmReg2_m256 );
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ZmmReg1 = zext(tmp);
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}
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# BLENDPD 3-78 PAGE 648 LINE 35433
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define pcodeop vblendpd_avx ;
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:VBLENDPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8_3_0 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8_3_0
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{
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local tmp:16 = vblendpd_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8_3_0:1 );
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ZmmReg1 = zext(tmp);
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}
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# BLENDPD 3-78 PAGE 648 LINE 35436
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:VBLENDPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8_3_0 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x0D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8_3_0
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{
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local tmp:32 = vblendpd_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8_3_0:1 );
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ZmmReg1 = zext(tmp);
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}
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# BLENDPS 3-81 PAGE 651 LINE 35580
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define pcodeop vblendps_avx ;
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:VBLENDPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
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{
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local tmp:16 = vblendps_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 );
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ZmmReg1 = zext(tmp);
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}
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# BLENDPS 3-81 PAGE 651 LINE 35583
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:VBLENDPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x0C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8
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{
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local tmp:32 = vblendps_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 );
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ZmmReg1 = zext(tmp);
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}
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# BLENDVPD 3-83 PAGE 653 LINE 35684
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define pcodeop vblendvpd_avx ;
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:VBLENDVPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, Xmm_imm8_7_4 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x4B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; Xmm_imm8_7_4
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{
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local tmp:16 = vblendvpd_avx( vexVVVV_XmmReg, XmmReg2_m128, Xmm_imm8_7_4 );
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ZmmReg1 = zext(tmp);
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}
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# BLENDVPD 3-83 PAGE 653 LINE 35688
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:VBLENDVPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, Ymm_imm8_7_4 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x4B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; Ymm_imm8_7_4
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{
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local tmp:32 = vblendvpd_avx( vexVVVV_YmmReg, YmmReg2_m256, Ymm_imm8_7_4 );
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ZmmReg1 = zext(tmp);
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}
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# BLENDVPS 3-85 PAGE 655 LINE 35789
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define pcodeop vblendvps_avx ;
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:VBLENDVPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, Xmm_imm8_7_4 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x4A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; Xmm_imm8_7_4
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{
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local tmp:16 = vblendvps_avx( vexVVVV_XmmReg, XmmReg2_m128, Xmm_imm8_7_4 );
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ZmmReg1 = zext(tmp);
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}
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# BLENDVPS 3-85 PAGE 655 LINE 35793
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:VBLENDVPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, Ymm_imm8_7_4 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x4A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; Ymm_imm8_7_4
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{
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local tmp:32 = vblendvps_avx( vexVVVV_YmmReg, YmmReg2_m256, Ymm_imm8_7_4 );
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ZmmReg1 = zext(tmp);
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}
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# CMPPD 3-155 PAGE 725 LINE 39240
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VCMPPD_mon: "VCMPEQPD" is imm8=0x0 { }
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VCMPPD_op: "" is imm8=0x0 { export 0x0:1; }
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VCMPPD_mon: "VCMPLTPD" is imm8=0x1 { }
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VCMPPD_op: "" is imm8=0x1 { export 0x1:1; }
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VCMPPD_mon: "VCMPLEPD" is imm8=0x2 { }
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VCMPPD_op: "" is imm8=0x2 { export 0x2:1; }
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VCMPPD_mon: "VCMPUNORDPD" is imm8=0x3 { }
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VCMPPD_op: "" is imm8=0x3 { export 0x3:1; }
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VCMPPD_mon: "VCMPNEQPD" is imm8=0x4 { }
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VCMPPD_op: "" is imm8=0x4 { export 0x4:1; }
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VCMPPD_mon: "VCMPNLTPD" is imm8=0x5 { }
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VCMPPD_op: "" is imm8=0x5 { export 0x5:1; }
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VCMPPD_mon: "VCMPNLEPD" is imm8=0x6 { }
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VCMPPD_op: "" is imm8=0x6 { export 0x6:1; }
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VCMPPD_mon: "VCMPORDPD" is imm8=0x7 { }
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VCMPPD_op: "" is imm8=0x7 { export 0x7:1; }
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VCMPPD_mon: "VCMPEQ_UQPD" is imm8=0x8 { }
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VCMPPD_op: "" is imm8=0x8 { export 0x8:1; }
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VCMPPD_mon: "VCMPNGEPD" is imm8=0x9 { }
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VCMPPD_op: "" is imm8=0x9 { export 0x9:1; }
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VCMPPD_mon: "VCMPNGTPD" is imm8=0xa { }
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VCMPPD_op: "" is imm8=0xa { export 0xa:1; }
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VCMPPD_mon: "VCMPFALSEPD" is imm8=0xb { }
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VCMPPD_op: "" is imm8=0xb { export 0xb:1; }
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VCMPPD_mon: "VCMPNEQ_OQPD" is imm8=0xc { }
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VCMPPD_op: "" is imm8=0xc { export 0xc:1; }
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VCMPPD_mon: "VCMPGEPD" is imm8=0xd { }
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VCMPPD_op: "" is imm8=0xd { export 0xd:1; }
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VCMPPD_mon: "VCMPGTPD" is imm8=0xe { }
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VCMPPD_op: "" is imm8=0xe { export 0xe:1; }
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VCMPPD_mon: "VCMPTRUEPD" is imm8=0xf { }
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VCMPPD_op: "" is imm8=0xf { export 0xf:1; }
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VCMPPD_mon: "VCMPEQ_OSPD" is imm8=0x10 { }
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VCMPPD_op: "" is imm8=0x10 { export 0x10:1; }
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VCMPPD_mon: "VCMPLT_OQPD" is imm8=0x11 { }
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VCMPPD_op: "" is imm8=0x11 { export 0x11:1; }
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VCMPPD_mon: "VCMPLE_OQPD" is imm8=0x12 { }
|
|
VCMPPD_op: "" is imm8=0x12 { export 0x12:1; }
|
|
VCMPPD_mon: "VCMPUNORD_SPD" is imm8=0x13 { }
|
|
VCMPPD_op: "" is imm8=0x13 { export 0x13:1; }
|
|
VCMPPD_mon: "VCMPNEQ_USPD" is imm8=0x14 { }
|
|
VCMPPD_op: "" is imm8=0x14 { export 0x14:1; }
|
|
VCMPPD_mon: "VCMPNLT_UQPD" is imm8=0x15 { }
|
|
VCMPPD_op: "" is imm8=0x15 { export 0x15:1; }
|
|
VCMPPD_mon: "VCMPNLE_UQPD" is imm8=0x16 { }
|
|
VCMPPD_op: "" is imm8=0x16 { export 0x16:1; }
|
|
VCMPPD_mon: "VCMPORD_SPD" is imm8=0x17 { }
|
|
VCMPPD_op: "" is imm8=0x17 { export 0x17:1; }
|
|
VCMPPD_mon: "VCMPEQ_USPD" is imm8=0x18 { }
|
|
VCMPPD_op: "" is imm8=0x18 { export 0x18:1; }
|
|
VCMPPD_mon: "VCMPNGE_UQPD" is imm8=0x19 { }
|
|
VCMPPD_op: "" is imm8=0x19 { export 0x19:1; }
|
|
VCMPPD_mon: "VCMPNGT_UQPD" is imm8=0x1a { }
|
|
VCMPPD_op: "" is imm8=0x1a { export 0x1a:1; }
|
|
VCMPPD_mon: "VCMPFALSE_OSPD" is imm8=0x1b { }
|
|
VCMPPD_op: "" is imm8=0x1b { export 0x1b:1; }
|
|
VCMPPD_mon: "VCMPNEQ_OSPD" is imm8=0x1c { }
|
|
VCMPPD_op: "" is imm8=0x1c { export 0x1c:1; }
|
|
VCMPPD_mon: "VCMPGE_OQPD" is imm8=0x1d { }
|
|
VCMPPD_op: "" is imm8=0x1d { export 0x1d:1; }
|
|
VCMPPD_mon: "VCMPGT_OQPD" is imm8=0x1e { }
|
|
VCMPPD_op: "" is imm8=0x1e { export 0x1e:1; }
|
|
VCMPPD_mon: "VCMPTRUE_USPD" is imm8=0x1f { }
|
|
VCMPPD_op: "" is imm8=0x1f { export 0x1f:1; }
|
|
VCMPPD_mon: "VCMPPD" is imm8 { }
|
|
VCMPPD_op: ", "^imm8 is imm8 { export *[const]:1 imm8; }
|
|
define pcodeop vcmppd_avx ;
|
|
:^VCMPPD_mon XmmReg1, vexVVVV_XmmReg, XmmReg2_m128^VCMPPD_op is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xC2; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; VCMPPD_mon & VCMPPD_op
|
|
{
|
|
local tmp:16 = vcmppd_avx( vexVVVV_XmmReg, XmmReg2_m128, VCMPPD_op );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# CMPPD 3-155 PAGE 725 LINE 39243
|
|
:^VCMPPD_mon YmmReg1, vexVVVV_YmmReg, YmmReg2_m256^VCMPPD_op is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xC2; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; VCMPPD_mon & VCMPPD_op
|
|
{
|
|
local tmp:32 = vcmppd_avx( vexVVVV_YmmReg, YmmReg2_m256, VCMPPD_op );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# CMPPS 3-162 PAGE 732 LINE 39607
|
|
VCMPPS_mon: "VCMPEQPS" is imm8=0x0 { }
|
|
VCMPPS_op: "" is imm8=0x0 { export 0x0:1; }
|
|
VCMPPS_mon: "VCMPLTPS" is imm8=0x1 { }
|
|
VCMPPS_op: "" is imm8=0x1 { export 0x1:1; }
|
|
VCMPPS_mon: "VCMPLEPS" is imm8=0x2 { }
|
|
VCMPPS_op: "" is imm8=0x2 { export 0x2:1; }
|
|
VCMPPS_mon: "VCMPUNORDPS" is imm8=0x3 { }
|
|
VCMPPS_op: "" is imm8=0x3 { export 0x3:1; }
|
|
VCMPPS_mon: "VCMPNEQPS" is imm8=0x4 { }
|
|
VCMPPS_op: "" is imm8=0x4 { export 0x4:1; }
|
|
VCMPPS_mon: "VCMPNLTPS" is imm8=0x5 { }
|
|
VCMPPS_op: "" is imm8=0x5 { export 0x5:1; }
|
|
VCMPPS_mon: "VCMPNLEPS" is imm8=0x6 { }
|
|
VCMPPS_op: "" is imm8=0x6 { export 0x6:1; }
|
|
VCMPPS_mon: "VCMPORDPS" is imm8=0x7 { }
|
|
VCMPPS_op: "" is imm8=0x7 { export 0x7:1; }
|
|
VCMPPS_mon: "VCMPEQ_UQPS" is imm8=0x8 { }
|
|
VCMPPS_op: "" is imm8=0x8 { export 0x8:1; }
|
|
VCMPPS_mon: "VCMPNGEPS" is imm8=0x9 { }
|
|
VCMPPS_op: "" is imm8=0x9 { export 0x9:1; }
|
|
VCMPPS_mon: "VCMPNGTPS" is imm8=0xa { }
|
|
VCMPPS_op: "" is imm8=0xa { export 0xa:1; }
|
|
VCMPPS_mon: "VCMPFALSEPS" is imm8=0xb { }
|
|
VCMPPS_op: "" is imm8=0xb { export 0xb:1; }
|
|
VCMPPS_mon: "VCMPNEQ_OQPS" is imm8=0xc { }
|
|
VCMPPS_op: "" is imm8=0xc { export 0xc:1; }
|
|
VCMPPS_mon: "VCMPGEPS" is imm8=0xd { }
|
|
VCMPPS_op: "" is imm8=0xd { export 0xd:1; }
|
|
VCMPPS_mon: "VCMPGTPS" is imm8=0xe { }
|
|
VCMPPS_op: "" is imm8=0xe { export 0xe:1; }
|
|
VCMPPS_mon: "VCMPTRUEPS" is imm8=0xf { }
|
|
VCMPPS_op: "" is imm8=0xf { export 0xf:1; }
|
|
VCMPPS_mon: "VCMPEQ_OSPS" is imm8=0x10 { }
|
|
VCMPPS_op: "" is imm8=0x10 { export 0x10:1; }
|
|
VCMPPS_mon: "VCMPLT_OQPS" is imm8=0x11 { }
|
|
VCMPPS_op: "" is imm8=0x11 { export 0x11:1; }
|
|
VCMPPS_mon: "VCMPLE_OQPS" is imm8=0x12 { }
|
|
VCMPPS_op: "" is imm8=0x12 { export 0x12:1; }
|
|
VCMPPS_mon: "VCMPUNORD_SPS" is imm8=0x13 { }
|
|
VCMPPS_op: "" is imm8=0x13 { export 0x13:1; }
|
|
VCMPPS_mon: "VCMPNEQ_USPS" is imm8=0x14 { }
|
|
VCMPPS_op: "" is imm8=0x14 { export 0x14:1; }
|
|
VCMPPS_mon: "VCMPNLT_UQPS" is imm8=0x15 { }
|
|
VCMPPS_op: "" is imm8=0x15 { export 0x15:1; }
|
|
VCMPPS_mon: "VCMPNLE_UQPS" is imm8=0x16 { }
|
|
VCMPPS_op: "" is imm8=0x16 { export 0x16:1; }
|
|
VCMPPS_mon: "VCMPORD_SPS" is imm8=0x17 { }
|
|
VCMPPS_op: "" is imm8=0x17 { export 0x17:1; }
|
|
VCMPPS_mon: "VCMPEQ_USPS" is imm8=0x18 { }
|
|
VCMPPS_op: "" is imm8=0x18 { export 0x18:1; }
|
|
VCMPPS_mon: "VCMPNGE_UQPS" is imm8=0x19 { }
|
|
VCMPPS_op: "" is imm8=0x19 { export 0x19:1; }
|
|
VCMPPS_mon: "VCMPNGT_UQPS" is imm8=0x1a { }
|
|
VCMPPS_op: "" is imm8=0x1a { export 0x1a:1; }
|
|
VCMPPS_mon: "VCMPFALSE_OSPS" is imm8=0x1b { }
|
|
VCMPPS_op: "" is imm8=0x1b { export 0x1b:1; }
|
|
VCMPPS_mon: "VCMPNEQ_OSPS" is imm8=0x1c { }
|
|
VCMPPS_op: "" is imm8=0x1c { export 0x1c:1; }
|
|
VCMPPS_mon: "VCMPGE_OQPS" is imm8=0x1d { }
|
|
VCMPPS_op: "" is imm8=0x1d { export 0x1d:1; }
|
|
VCMPPS_mon: "VCMPGT_OQPS" is imm8=0x1e { }
|
|
VCMPPS_op: "" is imm8=0x1e { export 0x1e:1; }
|
|
VCMPPS_mon: "VCMPTRUE_USPS" is imm8=0x1f { }
|
|
VCMPPS_op: "" is imm8=0x1f { export 0x1f:1; }
|
|
VCMPPS_mon: "VCMPPS" is imm8 { }
|
|
VCMPPS_op: ", "^imm8 is imm8 { export *[const]:1 imm8; }
|
|
define pcodeop vcmpps_avx ;
|
|
:^VCMPPS_mon XmmReg1, vexVVVV_XmmReg, XmmReg2_m128^VCMPPS_op is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xC2; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; VCMPPS_mon & VCMPPS_op
|
|
{
|
|
local tmp:16 = vcmpps_avx( vexVVVV_XmmReg, XmmReg2_m128, VCMPPS_op );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# CMPPS 3-162 PAGE 732 LINE 39610
|
|
:^VCMPPS_mon YmmReg1, vexVVVV_YmmReg, YmmReg2_m256^VCMPPS_op is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xC2; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; VCMPPS_mon & VCMPPS_op
|
|
{
|
|
local tmp:32 = vcmpps_avx( vexVVVV_YmmReg, YmmReg2_m256, VCMPPS_op );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# CMPSD 3-173 PAGE 743 LINE 40154
|
|
VCMPSD_mon: "VCMPEQSD" is imm8=0x0 { }
|
|
VCMPSD_op: "" is imm8=0x0 { export 0x0:1; }
|
|
VCMPSD_mon: "VCMPLTSD" is imm8=0x1 { }
|
|
VCMPSD_op: "" is imm8=0x1 { export 0x1:1; }
|
|
VCMPSD_mon: "VCMPLESD" is imm8=0x2 { }
|
|
VCMPSD_op: "" is imm8=0x2 { export 0x2:1; }
|
|
VCMPSD_mon: "VCMPUNORDSD" is imm8=0x3 { }
|
|
VCMPSD_op: "" is imm8=0x3 { export 0x3:1; }
|
|
VCMPSD_mon: "VCMPNEQSD" is imm8=0x4 { }
|
|
VCMPSD_op: "" is imm8=0x4 { export 0x4:1; }
|
|
VCMPSD_mon: "VCMPNLTSD" is imm8=0x5 { }
|
|
VCMPSD_op: "" is imm8=0x5 { export 0x5:1; }
|
|
VCMPSD_mon: "VCMPNLESD" is imm8=0x6 { }
|
|
VCMPSD_op: "" is imm8=0x6 { export 0x6:1; }
|
|
VCMPSD_mon: "VCMPORDSD" is imm8=0x7 { }
|
|
VCMPSD_op: "" is imm8=0x7 { export 0x7:1; }
|
|
VCMPSD_mon: "VCMPEQ_UQSD" is imm8=0x8 { }
|
|
VCMPSD_op: "" is imm8=0x8 { export 0x8:1; }
|
|
VCMPSD_mon: "VCMPNGESD" is imm8=0x9 { }
|
|
VCMPSD_op: "" is imm8=0x9 { export 0x9:1; }
|
|
VCMPSD_mon: "VCMPNGTSD" is imm8=0xa { }
|
|
VCMPSD_op: "" is imm8=0xa { export 0xa:1; }
|
|
VCMPSD_mon: "VCMPFALSESD" is imm8=0xb { }
|
|
VCMPSD_op: "" is imm8=0xb { export 0xb:1; }
|
|
VCMPSD_mon: "VCMPNEQ_OQSD" is imm8=0xc { }
|
|
VCMPSD_op: "" is imm8=0xc { export 0xc:1; }
|
|
VCMPSD_mon: "VCMPGESD" is imm8=0xd { }
|
|
VCMPSD_op: "" is imm8=0xd { export 0xd:1; }
|
|
VCMPSD_mon: "VCMPGTSD" is imm8=0xe { }
|
|
VCMPSD_op: "" is imm8=0xe { export 0xe:1; }
|
|
VCMPSD_mon: "VCMPTRUESD" is imm8=0xf { }
|
|
VCMPSD_op: "" is imm8=0xf { export 0xf:1; }
|
|
VCMPSD_mon: "VCMPEQ_OSSD" is imm8=0x10 { }
|
|
VCMPSD_op: "" is imm8=0x10 { export 0x10:1; }
|
|
VCMPSD_mon: "VCMPLT_OQSD" is imm8=0x11 { }
|
|
VCMPSD_op: "" is imm8=0x11 { export 0x11:1; }
|
|
VCMPSD_mon: "VCMPLE_OQSD" is imm8=0x12 { }
|
|
VCMPSD_op: "" is imm8=0x12 { export 0x12:1; }
|
|
VCMPSD_mon: "VCMPUNORD_SSD" is imm8=0x13 { }
|
|
VCMPSD_op: "" is imm8=0x13 { export 0x13:1; }
|
|
VCMPSD_mon: "VCMPNEQ_USSD" is imm8=0x14 { }
|
|
VCMPSD_op: "" is imm8=0x14 { export 0x14:1; }
|
|
VCMPSD_mon: "VCMPNLT_UQSD" is imm8=0x15 { }
|
|
VCMPSD_op: "" is imm8=0x15 { export 0x15:1; }
|
|
VCMPSD_mon: "VCMPNLE_UQSD" is imm8=0x16 { }
|
|
VCMPSD_op: "" is imm8=0x16 { export 0x16:1; }
|
|
VCMPSD_mon: "VCMPORD_SSD" is imm8=0x17 { }
|
|
VCMPSD_op: "" is imm8=0x17 { export 0x17:1; }
|
|
VCMPSD_mon: "VCMPEQ_USSD" is imm8=0x18 { }
|
|
VCMPSD_op: "" is imm8=0x18 { export 0x18:1; }
|
|
VCMPSD_mon: "VCMPNGE_UQSD" is imm8=0x19 { }
|
|
VCMPSD_op: "" is imm8=0x19 { export 0x19:1; }
|
|
VCMPSD_mon: "VCMPNGT_UQSD" is imm8=0x1a { }
|
|
VCMPSD_op: "" is imm8=0x1a { export 0x1a:1; }
|
|
VCMPSD_mon: "VCMPFALSE_OSSD" is imm8=0x1b { }
|
|
VCMPSD_op: "" is imm8=0x1b { export 0x1b:1; }
|
|
VCMPSD_mon: "VCMPNEQ_OSSD" is imm8=0x1c { }
|
|
VCMPSD_op: "" is imm8=0x1c { export 0x1c:1; }
|
|
VCMPSD_mon: "VCMPGE_OQSD" is imm8=0x1d { }
|
|
VCMPSD_op: "" is imm8=0x1d { export 0x1d:1; }
|
|
VCMPSD_mon: "VCMPGT_OQSD" is imm8=0x1e { }
|
|
VCMPSD_op: "" is imm8=0x1e { export 0x1e:1; }
|
|
VCMPSD_mon: "VCMPTRUE_USSD" is imm8=0x1f { }
|
|
VCMPSD_op: "" is imm8=0x1f { export 0x1f:1; }
|
|
VCMPSD_mon: "VCMPSD" is imm8 { }
|
|
VCMPSD_op: ", "^imm8 is imm8 { export *[const]:1 imm8; }
|
|
define pcodeop vcmpsd_avx ;
|
|
:^VCMPSD_mon XmmReg1, vexVVVV_XmmReg, XmmReg2_m64^VCMPSD_op is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xC2; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64; VCMPSD_mon & VCMPSD_op
|
|
{
|
|
local tmp:16 = vcmpsd_avx( vexVVVV_XmmReg, XmmReg2_m64, VCMPSD_op );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# CMPSS 3-177 PAGE 747 LINE 40390
|
|
VCMPSS_mon: "VCMPEQSS" is imm8=0x0 { }
|
|
VCMPSS_op: "" is imm8=0x0 { export 0x0:1; }
|
|
VCMPSS_mon: "VCMPLTSS" is imm8=0x1 { }
|
|
VCMPSS_op: "" is imm8=0x1 { export 0x1:1; }
|
|
VCMPSS_mon: "VCMPLESS" is imm8=0x2 { }
|
|
VCMPSS_op: "" is imm8=0x2 { export 0x2:1; }
|
|
VCMPSS_mon: "VCMPUNORDSS" is imm8=0x3 { }
|
|
VCMPSS_op: "" is imm8=0x3 { export 0x3:1; }
|
|
VCMPSS_mon: "VCMPNEQSS" is imm8=0x4 { }
|
|
VCMPSS_op: "" is imm8=0x4 { export 0x4:1; }
|
|
VCMPSS_mon: "VCMPNLTSS" is imm8=0x5 { }
|
|
VCMPSS_op: "" is imm8=0x5 { export 0x5:1; }
|
|
VCMPSS_mon: "VCMPNLESS" is imm8=0x6 { }
|
|
VCMPSS_op: "" is imm8=0x6 { export 0x6:1; }
|
|
VCMPSS_mon: "VCMPORDSS" is imm8=0x7 { }
|
|
VCMPSS_op: "" is imm8=0x7 { export 0x7:1; }
|
|
VCMPSS_mon: "VCMPEQ_UQSS" is imm8=0x8 { }
|
|
VCMPSS_op: "" is imm8=0x8 { export 0x8:1; }
|
|
VCMPSS_mon: "VCMPNGESS" is imm8=0x9 { }
|
|
VCMPSS_op: "" is imm8=0x9 { export 0x9:1; }
|
|
VCMPSS_mon: "VCMPNGTSS" is imm8=0xa { }
|
|
VCMPSS_op: "" is imm8=0xa { export 0xa:1; }
|
|
VCMPSS_mon: "VCMPFALSESS" is imm8=0xb { }
|
|
VCMPSS_op: "" is imm8=0xb { export 0xb:1; }
|
|
VCMPSS_mon: "VCMPNEQ_OQSS" is imm8=0xc { }
|
|
VCMPSS_op: "" is imm8=0xc { export 0xc:1; }
|
|
VCMPSS_mon: "VCMPGESS" is imm8=0xd { }
|
|
VCMPSS_op: "" is imm8=0xd { export 0xd:1; }
|
|
VCMPSS_mon: "VCMPGTSS" is imm8=0xe { }
|
|
VCMPSS_op: "" is imm8=0xe { export 0xe:1; }
|
|
VCMPSS_mon: "VCMPTRUESS" is imm8=0xf { }
|
|
VCMPSS_op: "" is imm8=0xf { export 0xf:1; }
|
|
VCMPSS_mon: "VCMPEQ_OSSS" is imm8=0x10 { }
|
|
VCMPSS_op: "" is imm8=0x10 { export 0x10:1; }
|
|
VCMPSS_mon: "VCMPLT_OQSS" is imm8=0x11 { }
|
|
VCMPSS_op: "" is imm8=0x11 { export 0x11:1; }
|
|
VCMPSS_mon: "VCMPLE_OQSS" is imm8=0x12 { }
|
|
VCMPSS_op: "" is imm8=0x12 { export 0x12:1; }
|
|
VCMPSS_mon: "VCMPUNORD_SSS" is imm8=0x13 { }
|
|
VCMPSS_op: "" is imm8=0x13 { export 0x13:1; }
|
|
VCMPSS_mon: "VCMPNEQ_USSS" is imm8=0x14 { }
|
|
VCMPSS_op: "" is imm8=0x14 { export 0x14:1; }
|
|
VCMPSS_mon: "VCMPNLT_UQSS" is imm8=0x15 { }
|
|
VCMPSS_op: "" is imm8=0x15 { export 0x15:1; }
|
|
VCMPSS_mon: "VCMPNLE_UQSS" is imm8=0x16 { }
|
|
VCMPSS_op: "" is imm8=0x16 { export 0x16:1; }
|
|
VCMPSS_mon: "VCMPORD_SSS" is imm8=0x17 { }
|
|
VCMPSS_op: "" is imm8=0x17 { export 0x17:1; }
|
|
VCMPSS_mon: "VCMPEQ_USSS" is imm8=0x18 { }
|
|
VCMPSS_op: "" is imm8=0x18 { export 0x18:1; }
|
|
VCMPSS_mon: "VCMPNGE_UQSS" is imm8=0x19 { }
|
|
VCMPSS_op: "" is imm8=0x19 { export 0x19:1; }
|
|
VCMPSS_mon: "VCMPNGT_UQSS" is imm8=0x1a { }
|
|
VCMPSS_op: "" is imm8=0x1a { export 0x1a:1; }
|
|
VCMPSS_mon: "VCMPFALSE_OSSS" is imm8=0x1b { }
|
|
VCMPSS_op: "" is imm8=0x1b { export 0x1b:1; }
|
|
VCMPSS_mon: "VCMPNEQ_OSSS" is imm8=0x1c { }
|
|
VCMPSS_op: "" is imm8=0x1c { export 0x1c:1; }
|
|
VCMPSS_mon: "VCMPGE_OQSS" is imm8=0x1d { }
|
|
VCMPSS_op: "" is imm8=0x1d { export 0x1d:1; }
|
|
VCMPSS_mon: "VCMPGT_OQSS" is imm8=0x1e { }
|
|
VCMPSS_op: "" is imm8=0x1e { export 0x1e:1; }
|
|
VCMPSS_mon: "VCMPTRUE_USSS" is imm8=0x1f { }
|
|
VCMPSS_op: "" is imm8=0x1f { export 0x1f:1; }
|
|
VCMPSS_mon: "VCMPSS" is imm8 { }
|
|
VCMPSS_op: ", "^imm8 is imm8 { export *[const]:1 imm8; }
|
|
define pcodeop vcmpss_avx ;
|
|
:^VCMPSS_mon XmmReg1, vexVVVV_XmmReg, XmmReg2_m32^VCMPSS_op is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xC2; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32; VCMPSS_mon & VCMPSS_op
|
|
{
|
|
local tmp:16 = vcmpss_avx( vexVVVV_XmmReg, XmmReg2_m32, VCMPSS_op );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# COMISD 3-186 PAGE 756 LINE 40860
|
|
:VCOMISD XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x2F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
{
|
|
fucompe(XmmReg1[0,64], XmmReg2_m64[0,64]);
|
|
}
|
|
|
|
# COMISS 3-188 PAGE 758 LINE 40938
|
|
:VCOMISS XmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x2F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
|
|
{
|
|
fucompe(XmmReg1[0,32], XmmReg2_m32[0,32]);
|
|
}
|
|
|
|
# CVTDQ2PD 3-228 PAGE 798 LINE 43074
|
|
define pcodeop vcvtdq2pd_avx ;
|
|
:VCVTDQ2PD XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0xE6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
{
|
|
local tmp:16 = vcvtdq2pd_avx( XmmReg2_m64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# CVTDQ2PD 3-228 PAGE 798 LINE 43077
|
|
:VCVTDQ2PD YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0xE6; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:32 = vcvtdq2pd_avx( XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# CVTDQ2PS 3-232 PAGE 802 LINE 43242
|
|
define pcodeop vcvtdq2ps_avx ;
|
|
:VCVTDQ2PS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x5B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vcvtdq2ps_avx( XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# CVTDQ2PS 3-232 PAGE 802 LINE 43245
|
|
:VCVTDQ2PS YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x5B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vcvtdq2ps_avx( YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# CVTPD2DQ 3-235 PAGE 805 LINE 43408
|
|
define pcodeop vcvtpd2dq_avx ;
|
|
:VCVTPD2DQ XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0xE6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vcvtpd2dq_avx( XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# CVTPD2DQ 3-235 PAGE 805 LINE 43411
|
|
:VCVTPD2DQ XmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0xE6; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:16 = vcvtpd2dq_avx( YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# CVTPD2PS 3-240 PAGE 810 LINE 43643
|
|
define pcodeop vcvtpd2ps_avx ;
|
|
:VCVTPD2PS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vcvtpd2ps_avx( XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# CVTPD2PS 3-240 PAGE 810 LINE 43646
|
|
:VCVTPD2PS XmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x5A; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:16 = vcvtpd2ps_avx( YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# CVTPS2DQ 3-246 PAGE 816 LINE 43927
|
|
define pcodeop vcvtps2dq_avx ;
|
|
:VCVTPS2DQ XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x5B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vcvtps2dq_avx( XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# CVTPS2DQ 3-246 PAGE 816 LINE 43930
|
|
:VCVTPS2DQ YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x5B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vcvtps2dq_avx( YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# CVTPS2PD 3-249 PAGE 819 LINE 44098
|
|
define pcodeop vcvtps2pd_avx ;
|
|
:VCVTPS2PD XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
{
|
|
local tmp:16 = vcvtps2pd_avx( XmmReg2_m64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# CVTPS2PD 3-249 PAGE 819 LINE 44101
|
|
:VCVTPS2PD YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x5A; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:32 = vcvtps2pd_avx( XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# CVTSD2SI 3-253 PAGE 823 LINE 44315
|
|
:VCVTSD2SI Reg32, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x2D; Reg32 ... & XmmReg2_m64
|
|
{
|
|
Reg32 = trunc(round(XmmReg2_m64[0,64]));
|
|
# TODO Reg64 = zext(Reg32)
|
|
}
|
|
|
|
# CVTSD2SI 3-253 PAGE 823 LINE 44317
|
|
@ifdef IA64
|
|
:VCVTSD2SI Reg64, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x2D; Reg64 ... & XmmReg2_m64
|
|
{
|
|
Reg64 = round(XmmReg2_m64[0,64]);
|
|
}
|
|
@endif
|
|
|
|
# CVTSD2SS 3-255 PAGE 825 LINE 44414
|
|
:VCVTSD2SS XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
{
|
|
local tmp:4 = float2float(XmmReg2_m64[0,64]);
|
|
XmmReg1[0,32] = tmp;
|
|
XmmReg1[32,96] = vexVVVV_XmmReg[32,96];
|
|
ZmmReg1 = zext(XmmReg1);
|
|
}
|
|
|
|
# CVTSI2SD 3-257 PAGE 827 LINE 44516
|
|
:VCVTSI2SD XmmReg1, vexVVVV_XmmReg, rm32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2A; (XmmReg1 & ZmmReg1) ... & rm32
|
|
{
|
|
local tmp:8 = int2float(rm32);
|
|
XmmReg1[0,64] = tmp;
|
|
XmmReg1[64,64] = vexVVVV_XmmReg[64,64];
|
|
ZmmReg1 = zext(XmmReg1);
|
|
}
|
|
|
|
# CVTSI2SD 3-257 PAGE 827 LINE 44519
|
|
@ifdef IA64
|
|
:VCVTSI2SD XmmReg1, vexVVVV_XmmReg, rm64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x2A; (XmmReg1 & ZmmReg1) ... & rm64
|
|
{
|
|
local tmp:8 = int2float(rm64);
|
|
XmmReg1[0,64] = tmp;
|
|
XmmReg1[64,64] = vexVVVV_XmmReg[64,64];
|
|
ZmmReg1 = zext(XmmReg1);
|
|
}
|
|
@endif
|
|
|
|
# CVTSI2SS 3-259 PAGE 829 LINE 44632
|
|
:VCVTSI2SS XmmReg1, vexVVVV_XmmReg, rm32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2A; (XmmReg1 & ZmmReg1) ... & rm32
|
|
{
|
|
local tmp:4 = int2float( rm32 );
|
|
XmmReg1[0,32] = tmp;
|
|
XmmReg1[32,96] = vexVVVV_XmmReg[32,96];
|
|
ZmmReg1 = zext(XmmReg1);
|
|
}
|
|
|
|
# CVTSI2SS 3-259 PAGE 829 LINE 44634
|
|
@ifdef IA64
|
|
:VCVTSI2SS XmmReg1, vexVVVV_XmmReg, rm64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x2A; (XmmReg1 & ZmmReg1) ... & rm64
|
|
{
|
|
local tmp:4 = int2float( rm64 );
|
|
XmmReg1[0,32] = tmp;
|
|
XmmReg1[32,96] = vexVVVV_XmmReg[32,96];
|
|
ZmmReg1 = zext(XmmReg1);
|
|
}
|
|
@endif
|
|
|
|
# CVTSS2SD 3-261 PAGE 831 LINE 44744
|
|
:VCVTSS2SD XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
|
|
{
|
|
local tmp:8 = float2float( XmmReg2_m32[0,32] );
|
|
XmmReg1[0,64] = tmp;
|
|
XmmReg1[64,64] = vexVVVV_XmmReg[64,64];
|
|
ZmmReg1 = zext(XmmReg1);
|
|
}
|
|
|
|
# CVTSS2SI 3-263 PAGE 833 LINE 44835
|
|
:VCVTSS2SI Reg32, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x2D; Reg32 ... & XmmReg2_m32
|
|
{
|
|
Reg32 = trunc(round(XmmReg2_m32[0,32]));
|
|
}
|
|
|
|
# CVTSS2SI 3-263 PAGE 833 LINE 44837
|
|
@ifdef IA64
|
|
:VCVTSS2SI Reg64, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x2D; Reg64 ... & XmmReg2_m32
|
|
{
|
|
Reg64 = trunc(round(XmmReg2_m32[0,32]));
|
|
}
|
|
|
|
@endif
|
|
|
|
# CVTTPD2DQ 3-265 PAGE 835 LINE 44930
|
|
:VCVTTPD2DQ XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xE6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = XmmReg2_m128;
|
|
XmmReg1[0,32] = trunc(tmp[0,64]);
|
|
XmmReg1[32,32] = trunc(tmp[64,64]);
|
|
XmmReg1[64,32] = 0;
|
|
XmmReg1[96,32] = 0;
|
|
ZmmReg1 = zext(XmmReg1);
|
|
}
|
|
|
|
# CVTTPD2DQ 3-265 PAGE 835 LINE 44933
|
|
:VCVTTPD2DQ XmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xE6; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = YmmReg2_m256;
|
|
XmmReg1[0,32] = trunc(tmp[0,64]);
|
|
XmmReg1[32,32] = trunc(tmp[64,64]);
|
|
XmmReg1[64,32] = trunc(tmp[128,64]);
|
|
XmmReg1[96,32] = trunc(tmp[192,64]);
|
|
ZmmReg1 = zext(XmmReg1);
|
|
}
|
|
|
|
# CVTTPS2DQ 3-270 PAGE 840 LINE 45163
|
|
:VCVTTPS2DQ XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x5B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = XmmReg2_m128;
|
|
XmmReg1[0,32] = trunc(tmp[0,32]);
|
|
XmmReg1[32,32] = trunc(tmp[32,32]);
|
|
XmmReg1[64,32] = trunc(tmp[64,32]);
|
|
XmmReg1[96,32] = trunc(tmp[96,32]);
|
|
ZmmReg1 = zext(XmmReg1);
|
|
}
|
|
|
|
# CVTTPS2DQ 3-270 PAGE 840 LINE 45166
|
|
:VCVTTPS2DQ YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x5B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = YmmReg2_m256;
|
|
YmmReg1[0,32] = trunc(tmp[0,32]);
|
|
YmmReg1[32,32] = trunc(tmp[32,32]);
|
|
YmmReg1[64,32] = trunc(tmp[64,32]);
|
|
YmmReg1[96,32] = trunc(tmp[96,32]);
|
|
YmmReg1[128,32] = trunc(tmp[128,32]);
|
|
YmmReg1[160,32] = trunc(tmp[160,32]);
|
|
YmmReg1[192,32] = trunc(tmp[192,32]);
|
|
YmmReg1[224,32] = trunc(tmp[224,32]);
|
|
ZmmReg1 = zext(YmmReg1);
|
|
}
|
|
|
|
# CVTTSD2SI 3-274 PAGE 844 LINE 45379
|
|
:VCVTTSD2SI Reg32, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x2C; Reg32 ... & XmmReg2_m64
|
|
{
|
|
Reg32 = trunc(XmmReg2_m64[0,64]);
|
|
}
|
|
|
|
# CVTTSD2SI 3-274 PAGE 844 LINE 45382
|
|
@ifdef IA64
|
|
:VCVTTSD2SI Reg64, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x2C; Reg64 ... & XmmReg2_m64
|
|
{
|
|
Reg64 = trunc(XmmReg2_m64[0,64]);
|
|
}
|
|
|
|
@endif
|
|
|
|
# CVTTSS2SI 3-276 PAGE 846 LINE 45473
|
|
:VCVTTSS2SI Reg32, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x2C; Reg32 ... & XmmReg2_m32
|
|
{
|
|
Reg32 = trunc(XmmReg2_m32[0,32]);
|
|
}
|
|
|
|
# CVTTSS2SI 3-276 PAGE 846 LINE 45476
|
|
@ifdef IA64
|
|
:VCVTTSS2SI Reg64, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x2C; Reg64 ... & XmmReg2_m32
|
|
{
|
|
Reg64 = trunc(XmmReg2_m32[0,32]);
|
|
}
|
|
@endif
|
|
|
|
# DIVPD 3-288 PAGE 858 LINE 46023
|
|
define pcodeop vdivpd_avx ;
|
|
:VDIVPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vdivpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# DIVPD 3-288 PAGE 858 LINE 46026
|
|
:VDIVPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vdivpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# DIVPS 3-291 PAGE 861 LINE 46164
|
|
define pcodeop vdivps_avx ;
|
|
:VDIVPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vdivps_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# DIVPS 3-291 PAGE 861 LINE 46167
|
|
:VDIVPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vdivps_avx( vexVVVV_YmmReg, YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# DIVSD 3-294 PAGE 864 LINE 46312
|
|
:VDIVSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
{
|
|
XmmReg1[0,64] = vexVVVV_XmmReg[0,64] f/ XmmReg2_m64[0,64];
|
|
XmmReg1[64,64] = vexVVVV_XmmReg[64,64];
|
|
ZmmReg1 = zext(XmmReg1);
|
|
}
|
|
|
|
# DIVSS 3-296 PAGE 866 LINE 46410
|
|
:VDIVSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
|
|
{
|
|
XmmReg1[0,32] = vexVVVV_XmmReg[0,32] f/ XmmReg2_m32[0,32];
|
|
XmmReg1[32,96] = vexVVVV_XmmReg[32,96];
|
|
ZmmReg1 = zext(XmmReg1);
|
|
}
|
|
|
|
# DPPD 3-298 PAGE 868 LINE 46509
|
|
define pcodeop vdppd_avx ;
|
|
:VDPPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x41; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
|
|
{
|
|
local tmp:16 = vdppd_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# DPPS 3-300 PAGE 870 LINE 46612
|
|
define pcodeop vdpps_avx ;
|
|
:VDPPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x40; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
|
|
{
|
|
local tmp:16 = vdpps_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# DPPS 3-300 PAGE 870 LINE 46616
|
|
:VDPPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x40; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8
|
|
{
|
|
local tmp:32 = vdpps_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# EXTRACTPS 3-307 PAGE 877 LINE 46978
|
|
define pcodeop vextractps_avx ;
|
|
:VEXTRACTPS rm32, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x17; XmmReg1 ... & rm32; imm8
|
|
{
|
|
rm32 = vextractps_avx( XmmReg1, imm8:1 );
|
|
}
|
|
|
|
# HADDPD 3-427 PAGE 997 LINE 52447
|
|
:VHADDPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x7C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local m:16 = XmmReg2_m128;
|
|
XmmReg1[0,64] = vexVVVV_XmmReg[0,64] f+ vexVVVV_XmmReg[64,64];
|
|
XmmReg1[64,64] = m[0,64] f+ m[64,64];
|
|
ZmmReg1 = zext(XmmReg1);
|
|
}
|
|
|
|
# HADDPD 3-427 PAGE 997 LINE 52450
|
|
:VHADDPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x7C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local m:32 = YmmReg2_m256;
|
|
YmmReg1[0,64] = vexVVVV_YmmReg[0,64] f+ vexVVVV_YmmReg[64,64];
|
|
YmmReg1[64,64] = m[0,64] f+ m[64,64];
|
|
YmmReg1[128,64] = vexVVVV_YmmReg[128,64] f+ vexVVVV_YmmReg[192,64];
|
|
YmmReg1[192,64] = m[128,64] f+ m[192,64];
|
|
ZmmReg1 = zext(YmmReg1);
|
|
}
|
|
|
|
# HADDPS 3-430 PAGE 1000 LINE 52586
|
|
define pcodeop vhaddps_avx ;
|
|
:VHADDPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x7C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vhaddps_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# HADDPS 3-430 PAGE 1000 LINE 52589
|
|
:VHADDPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x7C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vhaddps_avx( vexVVVV_YmmReg, YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# HSUBPD 3-434 PAGE 1004 LINE 52795
|
|
define pcodeop vhsubpd_avx ;
|
|
:VHSUBPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x7D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vhsubpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# HSUBPD 3-434 PAGE 1004 LINE 52798
|
|
:VHSUBPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x7D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vhsubpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# HSUBPS 3-437 PAGE 1007 LINE 52933
|
|
define pcodeop vhsubps_avx ;
|
|
:VHSUBPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x7D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vhsubps_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# HSUBPS 3-437 PAGE 1007 LINE 52936
|
|
:VHSUBPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x7D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vhsubps_avx( vexVVVV_YmmReg, YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# INSERTPS 3-454 PAGE 1024 LINE 53780
|
|
define pcodeop vinsertps_avx ;
|
|
:VINSERTPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x21; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32; imm8
|
|
{
|
|
local tmp:16 = vinsertps_avx( vexVVVV_XmmReg, XmmReg2_m32, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# LDDQU 3-518 PAGE 1088 LINE 57123
|
|
define pcodeop vlddqu_avx ;
|
|
:VLDDQU XmmReg1, m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0xF0; (XmmReg1 & ZmmReg1) ... & m128
|
|
{
|
|
local tmp:16 = vlddqu_avx( m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# LDDQU 3-518 PAGE 1088 LINE 57126
|
|
:VLDDQU YmmReg1, m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0xF0; (YmmReg1 & ZmmReg1) ... & m256
|
|
{
|
|
local tmp:32 = vlddqu_avx( m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# LDMXCSR 3-520 PAGE 1090 LINE 57208
|
|
define pcodeop vldmxcsr_avx ;
|
|
:VLDMXCSR m32 is $(VEX_NONE) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0xAE; reg_opcode=2 ... & m32
|
|
{
|
|
vldmxcsr_avx( m32 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# MASKMOVDQU 4-8 PAGE 1128 LINE 59041
|
|
define pcodeop vmaskmovdqu_avx ;
|
|
:VMASKMOVDQU XmmReg1, XmmReg2 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xF7; XmmReg1 & (mod=0x3 & XmmReg2)
|
|
{
|
|
vmaskmovdqu_avx( XmmReg1, XmmReg2 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# MAXPD 4-12 PAGE 1132 LINE 59201
|
|
define pcodeop vmaxpd_avx ;
|
|
:VMAXPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vmaxpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MAXPD 4-12 PAGE 1132 LINE 59203
|
|
:VMAXPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vmaxpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MAXPS 4-15 PAGE 1135 LINE 59350
|
|
define pcodeop vmaxps_avx ;
|
|
:VMAXPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vmaxps_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MAXPS 4-15 PAGE 1135 LINE 59353
|
|
:VMAXPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vmaxps_avx( vexVVVV_YmmReg, YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MAXSD 4-18 PAGE 1138 LINE 59503
|
|
define pcodeop vmaxsd_avx ;
|
|
:VMAXSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
{
|
|
local tmp:16 = vmaxsd_avx( vexVVVV_XmmReg, XmmReg2_m64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MAXSS 4-20 PAGE 1140 LINE 59606
|
|
define pcodeop vmaxss_avx ;
|
|
:VMAXSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
|
|
{
|
|
local tmp:16 = vmaxss_avx( vexVVVV_XmmReg, XmmReg2_m32 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MINPD 4-23 PAGE 1143 LINE 59765
|
|
define pcodeop vminpd_avx ;
|
|
:VMINPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vminpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MINPD 4-23 PAGE 1143 LINE 59768
|
|
:VMINPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vminpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MINPS 4-26 PAGE 1146 LINE 59909
|
|
define pcodeop vminps_avx ;
|
|
:VMINPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vminps_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MINPS 4-26 PAGE 1146 LINE 59912
|
|
:VMINPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vminps_avx( vexVVVV_YmmReg, YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MINSD 4-29 PAGE 1149 LINE 60061
|
|
define pcodeop vminsd_avx ;
|
|
:VMINSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
{
|
|
local tmp:16 = vminsd_avx( vexVVVV_XmmReg, XmmReg2_m64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MINSS 4-31 PAGE 1151 LINE 60164
|
|
define pcodeop vminss_avx ;
|
|
:VMINSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
|
|
{
|
|
local tmp:16 = vminss_avx( vexVVVV_XmmReg, XmmReg2_m32 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MOVD/MOVQ 4-55 PAGE 1175 LINE 61358
|
|
:VMOVD XmmReg1, rm32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x6E; (XmmReg1 & ZmmReg1) ... & rm32
|
|
{
|
|
ZmmReg1 = zext( rm32 );
|
|
}
|
|
|
|
# MOVD/MOVQ 4-55 PAGE 1175 LINE 61360
|
|
@ifdef IA64
|
|
:VMOVQ XmmReg1, rm64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x6E; (XmmReg1 & ZmmReg1) ... & rm64
|
|
{
|
|
ZmmReg1 = zext( rm64 );
|
|
}
|
|
@endif
|
|
|
|
# MOVD/MOVQ 4-55 PAGE 1175 LINE 61362
|
|
:VMOVD rm32, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7E; XmmReg1 ... & rm32
|
|
{
|
|
rm32 = XmmReg1 [0,32];
|
|
}
|
|
|
|
# MOVD/MOVQ 4-55 PAGE 1175 LINE 61364
|
|
@ifdef IA64
|
|
:VMOVQ rm64, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x7E; XmmReg1 ... & rm64
|
|
{
|
|
rm64 = XmmReg1 [0,64];
|
|
}
|
|
@endif
|
|
|
|
# MOVDDUP 4-59 PAGE 1179 LINE 61521
|
|
:VMOVDDUP XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0x12; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
{
|
|
local tmp:8 = XmmReg2_m64[0,64];
|
|
XmmReg1[0,64] = tmp;
|
|
XmmReg1[64,64] = tmp;
|
|
ZmmReg1 = zext(XmmReg1);
|
|
}
|
|
|
|
# MOVDDUP 4-59 PAGE 1179 LINE 61523
|
|
:VMOVDDUP YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0x12; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = YmmReg2_m256;
|
|
local tmp1:8 = tmp[0,64];
|
|
local tmp2:8 = tmp[128,64];
|
|
YmmReg1[0,64] = tmp1;
|
|
YmmReg1[64,64] = tmp1;
|
|
YmmReg1[128,64] = tmp2;
|
|
YmmReg1[192,64] = tmp2;
|
|
ZmmReg1 = zext(YmmReg1);
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61930
|
|
:VMOVDQU XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x6F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = XmmReg2_m128;
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61932
|
|
:VMOVDQU XmmReg2_m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x7F; (XmmReg1 & XmmReg2_m128_extend) ... & XmmReg2_m128
|
|
{
|
|
XmmReg2_m128 = XmmReg1;
|
|
build XmmReg2_m128_extend;
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61934
|
|
:VMOVDQU YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x6F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = YmmReg2_m256;
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61936
|
|
:VMOVDQU m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x7F; YmmReg1 ... & m256
|
|
{
|
|
m256 = YmmReg1;
|
|
}
|
|
|
|
:VMOVDQU YmmReg2, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x7F; YmmReg1 & (mod=3 & ZmmReg2 & YmmReg2)
|
|
{
|
|
ZmmReg2 = zext( YmmReg1 );
|
|
}
|
|
|
|
# MOVHLPS 4-76 PAGE 1196 LINE 62410
|
|
define pcodeop vmovhlps_avx ;
|
|
:VMOVHLPS XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x12; (XmmReg1 & ZmmReg1) & (mod=0x3 & XmmReg2)
|
|
{
|
|
local tmp:16 = vmovhlps_avx( vexVVVV_XmmReg, XmmReg2 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MOVHPD 4-78 PAGE 1198 LINE 62483
|
|
define pcodeop vmovhpd_avx ;
|
|
:VMOVHPD XmmReg1, vexVVVV_XmmReg, m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x16; (XmmReg1 & ZmmReg1) ... & m64
|
|
{
|
|
local tmp:16 = vmovhpd_avx( vexVVVV_XmmReg, m64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MOVHPD 4-78 PAGE 1198 LINE 62489
|
|
:VMOVHPD m64, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x17; XmmReg1 ... & m64
|
|
{
|
|
m64 = vmovhpd_avx( XmmReg1 );
|
|
}
|
|
|
|
# MOVHPS 4-80 PAGE 1200 LINE 62570
|
|
define pcodeop vmovhps_avx ;
|
|
:VMOVHPS XmmReg1, vexVVVV_XmmReg, m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x16; (XmmReg1 & ZmmReg1) ... & m64
|
|
{
|
|
local tmp:16 = vmovhps_avx( vexVVVV_XmmReg, m64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MOVHPS 4-80 PAGE 1200 LINE 62576
|
|
:VMOVHPS m64, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x17; XmmReg1 ... & m64
|
|
{
|
|
m64 = vmovhps_avx( XmmReg1 );
|
|
}
|
|
|
|
# MOVLHPS 4-82 PAGE 1202 LINE 62658
|
|
define pcodeop vmovlhps_avx ;
|
|
:VMOVLHPS XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x16; (XmmReg1 & ZmmReg1) & (mod=0x3 & XmmReg2)
|
|
{
|
|
local tmp:16 = vmovlhps_avx( vexVVVV_XmmReg, XmmReg2 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MOVLPD 4-84 PAGE 1204 LINE 62731
|
|
define pcodeop vmovlpd_avx ;
|
|
:VMOVLPD XmmReg1, vexVVVV_XmmReg, m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x12; (XmmReg1 & ZmmReg1) ... & m64
|
|
{
|
|
local tmp:16 = vmovlpd_avx( vexVVVV_XmmReg, m64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MOVLPD 4-84 PAGE 1204 LINE 62737
|
|
:VMOVLPD m64, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x13; XmmReg1 ... & m64
|
|
{
|
|
m64 = vmovlpd_avx( XmmReg1 );
|
|
}
|
|
|
|
# MOVLPS 4-86 PAGE 1206 LINE 62816
|
|
define pcodeop vmovlps_avx ;
|
|
:VMOVLPS XmmReg1, vexVVVV_XmmReg, m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x12; (XmmReg1 & ZmmReg1) ... & m64
|
|
{
|
|
local tmp:16 = vmovlps_avx( vexVVVV_XmmReg, m64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MOVLPS 4-86 PAGE 1206 LINE 62822
|
|
:VMOVLPS m64, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x13; XmmReg1 ... & m64
|
|
{
|
|
m64 = vmovlps_avx( XmmReg1 );
|
|
}
|
|
|
|
# MOVMSKPD 4-88 PAGE 1208 LINE 62906
|
|
define pcodeop vmovmskpd_avx ;
|
|
:VMOVMSKPD Reg32, XmmReg2 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x50; Reg32 & (mod=0x3 & XmmReg2)
|
|
{
|
|
Reg32 = vmovmskpd_avx( XmmReg2 );
|
|
# TODO Reg64 = zext(Reg32)
|
|
}
|
|
|
|
# MOVMSKPD 4-88 PAGE 1208 LINE 62910
|
|
:VMOVMSKPD Reg32, YmmReg2 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x50; Reg32 & (mod=0x3 & YmmReg2)
|
|
{
|
|
Reg32 = vmovmskpd_avx( YmmReg2 );
|
|
# TODO Reg64 = zext(Reg32)
|
|
}
|
|
|
|
# MOVMSKPS 4-90 PAGE 1210 LINE 62986
|
|
define pcodeop vmovmskps_avx ;
|
|
:VMOVMSKPS Reg32, XmmReg2 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x50; Reg32 & (mod=0x3 & XmmReg2)
|
|
{
|
|
Reg32 = vmovmskps_avx( XmmReg2 );
|
|
# TODO Reg64 = zext(Reg32)
|
|
}
|
|
|
|
# MOVMSKPS 4-90 PAGE 1210 LINE 62990
|
|
:VMOVMSKPS Reg32, YmmReg2 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x50; Reg32 & (mod=0x3 & YmmReg2)
|
|
{
|
|
Reg32 = vmovmskps_avx( YmmReg2 );
|
|
# TODO Reg64 = zext(Reg32)
|
|
}
|
|
|
|
# MOVNTDQA 4-92 PAGE 1212 LINE 63084
|
|
define pcodeop vmovntdqa_avx ;
|
|
:VMOVNTDQA XmmReg1, m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x2A; (XmmReg1 & ZmmReg1) ... & m128
|
|
{
|
|
local tmp:16 = vmovntdqa_avx( m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MOVNTDQ 4-94 PAGE 1214 LINE 63187
|
|
define pcodeop vmovntdq_avx ;
|
|
:VMOVNTDQ m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xE7; XmmReg1 ... & m128
|
|
{
|
|
m128 = vmovntdq_avx( XmmReg1 );
|
|
}
|
|
|
|
# MOVNTDQ 4-94 PAGE 1214 LINE 63189
|
|
:VMOVNTDQ m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xE7; YmmReg1 ... & m256
|
|
{
|
|
m256 = vmovntdq_avx( YmmReg1 );
|
|
}
|
|
|
|
# MOVNTPD 4-98 PAGE 1218 LINE 63357
|
|
define pcodeop vmovntpd_avx ;
|
|
:VMOVNTPD m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x2B; XmmReg1 ... & m128
|
|
{
|
|
m128 = vmovntpd_avx( XmmReg1 );
|
|
}
|
|
|
|
# MOVNTPD 4-98 PAGE 1218 LINE 63359
|
|
:VMOVNTPD m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x2B; YmmReg1 ... & m256
|
|
{
|
|
m256 = vmovntpd_avx( YmmReg1 );
|
|
}
|
|
|
|
# MOVNTPS 4-100 PAGE 1220 LINE 63441
|
|
define pcodeop vmovntps_avx ;
|
|
:VMOVNTPS m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x2B; XmmReg1 ... & m128
|
|
{
|
|
m128 = vmovntps_avx( XmmReg1 );
|
|
}
|
|
|
|
# MOVNTPS 4-100 PAGE 1220 LINE 63443
|
|
:VMOVNTPS m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x2B; YmmReg1 ... & m256
|
|
{
|
|
m256 = vmovntps_avx( YmmReg1 );
|
|
}
|
|
|
|
# MOVQ 4-103 PAGE 1223 LINE 63579
|
|
:VMOVQ XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x7E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
{
|
|
ZmmReg1 = zext(XmmReg2_m64[0,64]);
|
|
}
|
|
|
|
# MOVQ 4-103 PAGE 1223 LINE 63585
|
|
:VMOVQ m64, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xD6; XmmReg1 ... & m64
|
|
{
|
|
m64 = XmmReg1[0,64];
|
|
}
|
|
|
|
:VMOVQ XmmReg2, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xD6; XmmReg1 & (mod=3 & XmmReg2 & ZmmReg2 )
|
|
{
|
|
ZmmReg2 = zext( XmmReg1[0,64] );
|
|
}
|
|
|
|
# MOVSHDUP 4-114 PAGE 1234 LINE 64126
|
|
define pcodeop vmovshdup_avx ;
|
|
:VMOVSHDUP XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x16; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vmovshdup_avx( XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MOVSHDUP 4-114 PAGE 1234 LINE 64128
|
|
:VMOVSHDUP YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x16; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vmovshdup_avx( YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MOVSLDUP 4-117 PAGE 1237 LINE 64280
|
|
define pcodeop vmovsldup_avx ;
|
|
:VMOVSLDUP XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x12; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vmovsldup_avx( XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MOVSLDUP 4-117 PAGE 1237 LINE 64282
|
|
:VMOVSLDUP YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x12; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vmovsldup_avx( YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MOVSS 4-120 PAGE 1240 LINE 64433
|
|
|
|
:VMOVSS XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x10; (XmmReg1 & ZmmReg1) & (mod=0x3 & XmmReg2)
|
|
{
|
|
XmmReg1[0,32] = XmmReg2[0,32];
|
|
XmmReg1[32,96] = vexVVVV_XmmReg[32,96];
|
|
ZmmReg1 = zext(XmmReg1);
|
|
}
|
|
|
|
# MOVSS 4-120 PAGE 1240 LINE 64435
|
|
:VMOVSS XmmReg1, m32 is $(VEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x10; (XmmReg1 & ZmmReg1) ... & m32
|
|
{
|
|
ZmmReg1 = zext( m32 );
|
|
}
|
|
|
|
# MOVSS 4-120 PAGE 1240 LINE 64439
|
|
:VMOVSS XmmReg2, vexVVVV_XmmReg, XmmReg1 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x11; XmmReg1 & (mod=0x3 & (XmmReg2 & ZmmReg2))
|
|
{
|
|
XmmReg2[0,32] = XmmReg1[0,32];
|
|
XmmReg2[32,96] = vexVVVV_XmmReg[32,96];
|
|
ZmmReg2 = zext(XmmReg2);
|
|
}
|
|
|
|
# MOVSS 4-120 PAGE 1240 LINE 64441
|
|
:VMOVSS m32, XmmReg1 is $(VEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x11; XmmReg1 ... & m32
|
|
{
|
|
m32 = XmmReg1[0,32];
|
|
}
|
|
|
|
# MOVUPD 4-126 PAGE 1246 LINE 64687
|
|
:VMOVUPD XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x10; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = XmmReg2_m128;
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MOVUPD 4-126 PAGE 1246 LINE 64689
|
|
:VMOVUPD XmmReg2_m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x11; (XmmReg1 & XmmReg2_m128_extend) ... & XmmReg2_m128
|
|
{
|
|
XmmReg2_m128 = XmmReg1;
|
|
build XmmReg2_m128_extend;
|
|
}
|
|
|
|
# MOVUPD 4-126 PAGE 1246 LINE 64691
|
|
:VMOVUPD YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x10; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = YmmReg2_m256;
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MOVUPD 4-126 PAGE 1246 LINE 64693
|
|
:VMOVUPD m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x11; YmmReg1 ... & m256
|
|
{
|
|
m256 = YmmReg1;
|
|
}
|
|
|
|
:VMOVUPD YmmReg2, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x11; YmmReg1 & ( mod=3 & YmmReg2 & ZmmReg2 )
|
|
{
|
|
local tmp:32 = YmmReg1;
|
|
ZmmReg2 = zext(tmp);
|
|
}
|
|
|
|
# MPSADBW 4-136 PAGE 1256 LINE 65135
|
|
define pcodeop vmpsadbw_avx ;
|
|
:VMPSADBW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x42; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
|
|
{
|
|
local tmp:16 = vmpsadbw_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MULPD 4-146 PAGE 1266 LINE 65682
|
|
:VMULPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local m:16 = XmmReg2_m128;
|
|
XmmReg1[0,64] = vexVVVV_XmmReg[0,64] f* m[0,64];
|
|
XmmReg1[64,64] = vexVVVV_XmmReg[64,64] f* m[64,64];
|
|
ZmmReg1 = zext(XmmReg1);
|
|
}
|
|
|
|
# MULPD 4-146 PAGE 1266 LINE 65684
|
|
:VMULPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x59; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local m:32 = YmmReg2_m256;
|
|
YmmReg1[0,64] = vexVVVV_YmmReg[0,64] f* m[0,64];
|
|
YmmReg1[64,64] = vexVVVV_YmmReg[64,64] f* m[64,64];
|
|
YmmReg1[128,64] = vexVVVV_YmmReg[128,64] f* m[128,64];
|
|
YmmReg1[192,64] = vexVVVV_YmmReg[192,64] f* m[192,64];
|
|
ZmmReg1 = zext(YmmReg1);
|
|
}
|
|
|
|
# MULPS 4-149 PAGE 1269 LINE 65813
|
|
:VMULPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local m:16 = XmmReg2_m128;
|
|
XmmReg1[0,32] = vexVVVV_XmmReg[0,32] f* m[0,32];
|
|
XmmReg1[32,32] = vexVVVV_XmmReg[32,32] f* m[32,32];
|
|
XmmReg1[64,32] = vexVVVV_XmmReg[64,32] f* m[64,32];
|
|
XmmReg1[96,32] = vexVVVV_XmmReg[96,32] f* m[96,32];
|
|
ZmmReg1 = zext(XmmReg1);
|
|
}
|
|
|
|
# MULPS 4-149 PAGE 1269 LINE 65815
|
|
:VMULPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x59; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local m:32 = YmmReg2_m256;
|
|
YmmReg1[0,32] = vexVVVV_YmmReg[0,32] f* m[0,32];
|
|
YmmReg1[32,32] = vexVVVV_YmmReg[32,32] f* m[32,32];
|
|
YmmReg1[64,32] = vexVVVV_YmmReg[64,32] f* m[64,32];
|
|
YmmReg1[96,32] = vexVVVV_YmmReg[96,32] f* m[96,32];
|
|
YmmReg1[128,32] = vexVVVV_YmmReg[128,32] f* m[128,32];
|
|
YmmReg1[160,32] = vexVVVV_YmmReg[160,32] f* m[160,32];
|
|
YmmReg1[192,32] = vexVVVV_YmmReg[192,32] f* m[192,32];
|
|
YmmReg1[224,32] = vexVVVV_YmmReg[224,32] f* m[224,32];
|
|
ZmmReg1 = zext(YmmReg1);
|
|
}
|
|
|
|
# MULSD 4-152 PAGE 1272 LINE 65956
|
|
:VMULSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
{
|
|
local tmp:8 = vexVVVV_XmmReg[0,64] f* XmmReg2_m64[0,64];
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# MULSS 4-154 PAGE 1274 LINE 66052
|
|
:VMULSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
|
|
{
|
|
local tmp:4 = vexVVVV_XmmReg[0,32] f* XmmReg2_m32[0,32];
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# ORPD 4-168 PAGE 1288 LINE 66720
|
|
define pcodeop vorpd_avx ;
|
|
:VORPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vorpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# ORPD 4-168 PAGE 1288 LINE 66722
|
|
:VORPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vorpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# ORPS 4-171 PAGE 1291 LINE 66846
|
|
define pcodeop vorps_avx ;
|
|
:VORPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vorps_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# ORPS 4-171 PAGE 1291 LINE 66848
|
|
:VORPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vorps_avx( vexVVVV_YmmReg, YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67302
|
|
define pcodeop vpabsb_avx ;
|
|
:VPABSB XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x1C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpabsb_avx( XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67305
|
|
define pcodeop vpabsw_avx ;
|
|
:VPABSW XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x1D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpabsw_avx( XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67308
|
|
define pcodeop vpabsd_avx ;
|
|
:VPABSD XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x1E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpabsd_avx( XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67629
|
|
define pcodeop vpacksswb_avx ;
|
|
:VPACKSSWB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x63; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpacksswb_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67633
|
|
define pcodeop vpackssdw_avx ;
|
|
:VPACKSSDW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x6B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpackssdw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PACKUSDW 4-194 PAGE 1314 LINE 68086
|
|
define pcodeop vpackusdw_avx ;
|
|
:VPACKUSDW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_XmmReg; byte=0x2B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpackusdw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PACKUSWB 4-199 PAGE 1319 LINE 68366
|
|
define pcodeop vpackuswb_avx ;
|
|
:VPACKUSWB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x67; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpackuswb_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68658
|
|
define pcodeop vpaddb_avx ;
|
|
:VPADDB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpaddb_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68660
|
|
define pcodeop vpaddw_avx ;
|
|
:VPADDW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpaddw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68662
|
|
define pcodeop vpaddd_avx ;
|
|
:VPADDD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpaddd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68664
|
|
define pcodeop vpaddq_avx ;
|
|
:VPADDQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD4; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpaddq_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PADDSB/PADDSW 4-211 PAGE 1331 LINE 69040
|
|
define pcodeop vpaddsb_avx ;
|
|
:VPADDSB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xEC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpaddsb_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PADDSB/PADDSW 4-211 PAGE 1331 LINE 69042
|
|
define pcodeop vpaddsw_avx ;
|
|
:VPADDSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xED; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpaddsw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69257
|
|
define pcodeop vpaddusb_avx ;
|
|
:VPADDUSB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xDC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpaddusb_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69260
|
|
define pcodeop vpaddusw_avx ;
|
|
:VPADDUSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xDD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpaddusw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PALIGNR 4-219 PAGE 1339 LINE 69485
|
|
define pcodeop vpalignr_avx ;
|
|
:VPALIGNR XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
|
|
{
|
|
local tmp:16 = vpalignr_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PAND 4-223 PAGE 1343 LINE 69678
|
|
define pcodeop vpand_avx ;
|
|
:VPAND XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xDB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpand_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PANDN 4-226 PAGE 1346 LINE 69854
|
|
define pcodeop vpandn_avx ;
|
|
:VPANDN XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xDF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpandn_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PAVGB/PAVGW 4-230 PAGE 1350 LINE 70085
|
|
define pcodeop vpavgb_avx ;
|
|
:VPAVGB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE0; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpavgb_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PAVGB/PAVGW 4-230 PAGE 1350 LINE 70088
|
|
define pcodeop vpavgw_avx ;
|
|
:VPAVGW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE3; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpavgw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PBLENDVB 4-234 PAGE 1354 LINE 70296
|
|
define pcodeop vpblendvb_avx ;
|
|
:VPBLENDVB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, Xmm_imm8_7_4 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x4C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; Xmm_imm8_7_4
|
|
{
|
|
local tmp:16 = vpblendvb_avx( vexVVVV_XmmReg, XmmReg2_m128, Xmm_imm8_7_4 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PBLENDW 4-238 PAGE 1358 LINE 70522
|
|
define pcodeop vpblendw_avx ;
|
|
:VPBLENDW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
|
|
{
|
|
local tmp:16 = vpblendw_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70821
|
|
define pcodeop vpcmpeqb_avx ;
|
|
:VPCMPEQB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x74; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpcmpeqb_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70824
|
|
define pcodeop vpcmpeqw_avx ;
|
|
:VPCMPEQW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x75; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpcmpeqw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70827
|
|
define pcodeop vpcmpeqd_avx ;
|
|
:VPCMPEQD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x76; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpcmpeqd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PCMPESTRI 4-253 PAGE 1373 LINE 71311
|
|
define pcodeop vpcmpestri_avx ;
|
|
:VPCMPESTRI XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A); byte=0x61; XmmReg1 ... & XmmReg2_m128; imm8
|
|
{
|
|
vpcmpestri_avx( XmmReg1, XmmReg2_m128, imm8:1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# PCMPESTRM 4-255 PAGE 1375 LINE 71395
|
|
define pcodeop vpcmpestrm_avx ;
|
|
:VPCMPESTRM XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A); byte=0x60; XmmReg1 ... & XmmReg2_m128; imm8
|
|
{
|
|
vpcmpestrm_avx( XmmReg1, XmmReg2_m128, imm8:1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71499
|
|
define pcodeop vpcmpgtb_avx ;
|
|
:VPCMPGTB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x64; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpcmpgtb_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71502
|
|
define pcodeop vpcmpgtw_avx ;
|
|
:VPCMPGTW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x65; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpcmpgtw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71505
|
|
define pcodeop vpcmpgtd_avx ;
|
|
:VPCMPGTD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x66; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpcmpgtd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PCMPGTQ 4-263 PAGE 1383 LINE 71833
|
|
define pcodeop vpcmpgtq_avx ;
|
|
:VPCMPGTQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x37; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpcmpgtq_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PCMPISTRI 4-266 PAGE 1386 LINE 71966
|
|
define pcodeop vpcmpistri_avx ;
|
|
:VPCMPISTRI XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x63; XmmReg1 ... & XmmReg2_m128; imm8
|
|
{
|
|
vpcmpistri_avx( XmmReg1, XmmReg2_m128, imm8:1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# PCMPISTRM 4-268 PAGE 1388 LINE 72052
|
|
define pcodeop vpcmpistrm_avx ;
|
|
:VPCMPISTRM XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x62; XmmReg1 ... & XmmReg2_m128; imm8
|
|
{
|
|
vpcmpistrm_avx( XmmReg1, XmmReg2_m128, imm8:1 );
|
|
# TODO missing destination or side effects
|
|
}
|
|
|
|
# PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72322
|
|
define pcodeop vpextrb_avx ;
|
|
:VPEXTRB Rmr32, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x14; mod=3 & XmmReg1 & Rmr32 & check_Rmr32_dest; imm8
|
|
{
|
|
local tmp8:1 = imm8;
|
|
local tmp = XmmReg1 >> (tmp8[0,3]*8);
|
|
Rmr32 = zext(tmp[0,8]);
|
|
build check_Rmr32_dest;
|
|
}
|
|
|
|
:VPEXTRB m8, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x14; (XmmReg1 ... & m8); imm8
|
|
{
|
|
local tmp8:1 = imm8;
|
|
local tmp = XmmReg1 >> (tmp8[0,3]*8);
|
|
m8 = tmp[0,8];
|
|
}
|
|
|
|
# PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72326
|
|
define pcodeop vpextrd_avx ;
|
|
:VPEXTRD Rmr32, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x16; mod=3 & XmmReg1 & Rmr32 & check_Rmr32_dest; imm8
|
|
{
|
|
local tmp = XmmReg1 >> (imm8*32);
|
|
Rmr32 = tmp(0);
|
|
build check_Rmr32_dest;
|
|
}
|
|
|
|
:VPEXTRD m32, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x16; XmmReg1 ... & m32; imm8
|
|
{
|
|
local tmp = XmmReg1 >> (imm8*32);
|
|
m32 = tmp(0);
|
|
}
|
|
|
|
# PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72330
|
|
define pcodeop vpextrq_avx ;
|
|
@ifdef IA64
|
|
:VPEXTRQ rm64, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1); byte=0x16; XmmReg1 ... & rm64; imm8
|
|
{
|
|
rm64 = vpextrq_avx( XmmReg1, imm8:1 );
|
|
}
|
|
@endif
|
|
|
|
# PEXTRW 4-277 PAGE 1397 LINE 72478
|
|
define pcodeop vpextrw_avx ;
|
|
:VPEXTRW Reg32, XmmReg2, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0xC5; Reg32 & (mod=0x3 & XmmReg2); imm8
|
|
{
|
|
Reg32 = vpextrw_avx( XmmReg2, imm8:1 );
|
|
# TODO Reg64 = zext(Reg32)
|
|
}
|
|
|
|
# PEXTRW 4-277 PAGE 1397 LINE 72483
|
|
:VPEXTRW Reg32_m16, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x15; XmmReg1 ... & Reg32_m16; imm8
|
|
{
|
|
Reg32_m16 = vpextrw_avx( XmmReg1, imm8:1 );
|
|
# TODO Reg64 = zext(Reg32)
|
|
}
|
|
|
|
# PHADDW/PHADDD 4-280 PAGE 1400 LINE 72627
|
|
define pcodeop vphaddw_avx ;
|
|
:VPHADDW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x01; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vphaddw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PHADDW/PHADDD 4-280 PAGE 1400 LINE 72630
|
|
define pcodeop vphaddd_avx ;
|
|
:VPHADDD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x02; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vphaddd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PHADDSW 4-284 PAGE 1404 LINE 72821
|
|
define pcodeop vphaddsw_avx ;
|
|
:VPHADDSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x03; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vphaddsw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PHMINPOSUW 4-286 PAGE 1406 LINE 72939
|
|
define pcodeop vphminposuw_avx ;
|
|
:VPHMINPOSUW XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x41; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vphminposuw_avx( XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PHSUBW/PHSUBD 4-288 PAGE 1408 LINE 73032
|
|
define pcodeop vphsubw_avx ;
|
|
:VPHSUBW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x05; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vphsubw_avx( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PHSUBW/PHSUBD 4-288 PAGE 1408 LINE 73035
|
|
define pcodeop vphsubd_avx ;
|
|
:VPHSUBD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x06; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vphsubd_avx( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PHSUBSW 4-291 PAGE 1411 LINE 73197
|
|
define pcodeop vphsubsw_avx ;
|
|
:VPHSUBSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x07; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vphsubsw_avx( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73321
|
|
define pcodeop vpinsrb_avx ;
|
|
:VPINSRB XmmReg1, vexVVVV_XmmReg, Reg32_m8, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x20; (XmmReg1 & ZmmReg1) ... & Reg32_m8; imm8
|
|
{
|
|
local tmp:16 = vpinsrb_avx( vexVVVV_XmmReg, Reg32_m8, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73324
|
|
define pcodeop vpinsrd_avx ;
|
|
:VPINSRD XmmReg1, vexVVVV_XmmReg, rm32, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x22; (XmmReg1 & ZmmReg1) ... & rm32; imm8
|
|
{
|
|
local tmp:16 = vpinsrd_avx( vexVVVV_XmmReg, rm32, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73327
|
|
define pcodeop vpinsrq_avx ;
|
|
@ifdef IA64
|
|
:VPINSRQ XmmReg1, vexVVVV_XmmReg, rm64, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x22; (XmmReg1 & ZmmReg1) ... & rm64; imm8
|
|
{
|
|
local tmp:16 = vpinsrq_avx( vexVVVV_XmmReg, rm64, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
@endif
|
|
|
|
# PINSRW 4-296 PAGE 1416 LINE 73446
|
|
define pcodeop vpinsrw_avx ;
|
|
:VPINSRW XmmReg1, vexVVVV_XmmReg, Reg32_m16, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xC4; (XmmReg1 & ZmmReg1) ... & Reg32_m16; imm8
|
|
{
|
|
local tmp:16 = vpinsrw_avx( vexVVVV_XmmReg, Reg32_m16, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMADDUBSW 4-298 PAGE 1418 LINE 73552
|
|
define pcodeop vpmaddubsw_avx ;
|
|
:VPMADDUBSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x04; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpmaddubsw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMADDWD 4-301 PAGE 1421 LINE 73700
|
|
define pcodeop vpmaddwd_avx ;
|
|
:VPMADDWD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF5; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpmaddwd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73882
|
|
define pcodeop vpmaxsb_avx ;
|
|
:VPMAXSB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x3C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpmaxsb_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73885
|
|
define pcodeop vpmaxsw_avx ;
|
|
:VPMAXSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xEE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpmaxsw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73888
|
|
define pcodeop vpmaxsd_avx ;
|
|
:VPMAXSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x3D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpmaxsd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74283
|
|
define pcodeop vpmaxub_avx ;
|
|
:VPMAXUB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0xDE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpmaxub_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74286
|
|
define pcodeop vpmaxuw_avx ;
|
|
:VPMAXUW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_XmmReg; byte=0x3E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpmaxuw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74534
|
|
define pcodeop vpmaxud_avx ;
|
|
:VPMAXUD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x3F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpmaxud_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMINSB/PMINSW 4-320 PAGE 1440 LINE 74736
|
|
define pcodeop vpminsb_avx ;
|
|
:VPMINSB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_XmmReg; byte=0x38; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpminsb_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMINSB/PMINSW 4-320 PAGE 1440 LINE 74739
|
|
define pcodeop vpminsw_avx ;
|
|
:VPMINSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0xEA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpminsw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMINSD/PMINSQ 4-325 PAGE 1445 LINE 74989
|
|
define pcodeop vpminsd_avx ;
|
|
:VPMINSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x39; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpminsd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMINUB/PMINUW 4-329 PAGE 1449 LINE 75195
|
|
define pcodeop vpminub_avx ;
|
|
:VPMINUB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0xDA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpminub_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMINUB/PMINUW 4-329 PAGE 1449 LINE 75198
|
|
define pcodeop vpminuw_avx ;
|
|
:VPMINUW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_XmmReg; byte=0x3A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpminuw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75445
|
|
define pcodeop vpminud_avx ;
|
|
:VPMINUD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x3B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpminud_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMOVSX 4-340 PAGE 1460 LINE 75770
|
|
define pcodeop vpmovsxbw_avx ;
|
|
:VPMOVSXBW XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x20; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
{
|
|
local tmp:16 = vpmovsxbw_avx( XmmReg2_m64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMOVSX 4-340 PAGE 1460 LINE 75772
|
|
define pcodeop vpmovsxbd_avx ;
|
|
:VPMOVSXBD XmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x21; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
|
|
{
|
|
local tmp:16 = vpmovsxbd_avx( XmmReg2_m32 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMOVSX 4-340 PAGE 1460 LINE 75774
|
|
define pcodeop vpmovsxbq_avx ;
|
|
:VPMOVSXBQ XmmReg1, XmmReg2_m16 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x22; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
local tmp:16 = vpmovsxbq_avx( XmmReg2_m16 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMOVSX 4-340 PAGE 1460 LINE 75776
|
|
define pcodeop vpmovsxwd_avx ;
|
|
:VPMOVSXWD XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x23; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
{
|
|
local tmp:16 = vpmovsxwd_avx( XmmReg2_m64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMOVSX 4-340 PAGE 1460 LINE 75778
|
|
define pcodeop vpmovsxwq_avx ;
|
|
:VPMOVSXWQ XmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x24; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
|
|
{
|
|
local tmp:16 = vpmovsxwq_avx( XmmReg2_m32 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMOVSX 4-340 PAGE 1460 LINE 75780
|
|
define pcodeop vpmovsxdq_avx ;
|
|
:VPMOVSXDQ XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x25; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
{
|
|
local tmp:16 = vpmovsxdq_avx( XmmReg2_m64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMOVZX 4-350 PAGE 1470 LINE 76285
|
|
define pcodeop vpmovzxbw_avx ;
|
|
:VPMOVZXBW XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x30; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
{
|
|
local tmp:16 = vpmovzxbw_avx( XmmReg2_m64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMOVZX 4-350 PAGE 1470 LINE 76288
|
|
define pcodeop vpmovzxbd_avx ;
|
|
:VPMOVZXBD XmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x31; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
|
|
{
|
|
local tmp:16 = vpmovzxbd_avx( XmmReg2_m32 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMOVZX 4-350 PAGE 1470 LINE 76291
|
|
define pcodeop vpmovzxbq_avx ;
|
|
:VPMOVZXBQ XmmReg1, XmmReg2_m16 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x32; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
|
|
{
|
|
local tmp:16 = vpmovzxbq_avx( XmmReg2_m16 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMOVZX 4-350 PAGE 1470 LINE 76294
|
|
define pcodeop vpmovzxwd_avx ;
|
|
:VPMOVZXWD XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x33; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
{
|
|
local tmp:16 = vpmovzxwd_avx( XmmReg2_m64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMOVZX 4-350 PAGE 1470 LINE 76297
|
|
define pcodeop vpmovzxwq_avx ;
|
|
:VPMOVZXWQ XmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x34; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
|
|
{
|
|
local tmp:16 = vpmovzxwq_avx( XmmReg2_m32 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMOVZX 4-350 PAGE 1470 LINE 76301
|
|
define pcodeop vpmovzxdq_avx ;
|
|
:VPMOVZXDQ XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x35; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
{
|
|
local tmp:16 = vpmovzxdq_avx( XmmReg2_m64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMULDQ 4-359 PAGE 1479 LINE 76788
|
|
define pcodeop vpmuldq_avx ;
|
|
:VPMULDQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x28; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpmuldq_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMULHRSW 4-362 PAGE 1482 LINE 76928
|
|
define pcodeop vpmulhrsw_avx ;
|
|
:VPMULHRSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpmulhrsw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMULHUW 4-366 PAGE 1486 LINE 77141
|
|
define pcodeop vpmulhuw_avx ;
|
|
:VPMULHUW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE4; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpmulhuw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMULHW 4-370 PAGE 1490 LINE 77370
|
|
define pcodeop vpmulhw_avx ;
|
|
:VPMULHW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE5; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpmulhw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77576
|
|
define pcodeop vpmulld_avx ;
|
|
:VPMULLD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x40; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpmulld_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMULLW 4-378 PAGE 1498 LINE 77775
|
|
define pcodeop vpmullw_avx ;
|
|
:VPMULLW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD5; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpmullw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PMULUDQ 4-382 PAGE 1502 LINE 77969
|
|
define pcodeop vpmuludq_avx ;
|
|
:VPMULUDQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF4; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpmuludq_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# POR 4-399 PAGE 1519 LINE 78850
|
|
define pcodeop vpor_avx ;
|
|
:VPOR XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xEB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpor_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSADBW 4-408 PAGE 1528 LINE 79240
|
|
define pcodeop vpsadbw_avx ;
|
|
:VPSADBW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpsadbw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSHUFB 4-412 PAGE 1532 LINE 79460
|
|
define pcodeop vpshufb_avx ;
|
|
:VPSHUFB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x00; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpshufb_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSHUFD 4-416 PAGE 1536 LINE 79651
|
|
define pcodeop vpshufd_avx ;
|
|
:VPSHUFD XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x70; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
|
|
{
|
|
local tmp:16 = vpshufd_avx( XmmReg2_m128, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSHUFHW 4-420 PAGE 1540 LINE 79857
|
|
define pcodeop vpshufhw_avx ;
|
|
:VPSHUFHW XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x70; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
|
|
{
|
|
local tmp:16 = vpshufhw_avx( XmmReg2_m128, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSHUFLW 4-423 PAGE 1543 LINE 80032
|
|
define pcodeop vpshuflw_avx ;
|
|
:VPSHUFLW XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0x70; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
|
|
{
|
|
local tmp:16 = vpshuflw_avx( XmmReg2_m128, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSIGNB/PSIGNW/PSIGND 4-427 PAGE 1547 LINE 80269
|
|
define pcodeop vpsignb_avx ;
|
|
:VPSIGNB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x08; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpsignb_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSIGNB/PSIGNW/PSIGND 4-427 PAGE 1547 LINE 80272
|
|
define pcodeop vpsignw_avx ;
|
|
:VPSIGNW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x09; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpsignw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSIGNB/PSIGNW/PSIGND 4-427 PAGE 1547 LINE 80275
|
|
define pcodeop vpsignd_avx ;
|
|
:VPSIGND XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpsignd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSLLDQ 4-431 PAGE 1551 LINE 80485
|
|
define pcodeop vpslldq_avx ;
|
|
:VPSLLDQ vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x73; reg_opcode=7 & (mod=0x3 & XmmReg2); imm8
|
|
{
|
|
vexVVVV_XmmReg = vpslldq_avx( XmmReg2, imm8:1 );
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-433 PAGE 1553 LINE 80620
|
|
define pcodeop vpsllw_avx ;
|
|
:VPSLLW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF1; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpsllw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-433 PAGE 1553 LINE 80623
|
|
:VPSLLW vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x71; reg_opcode=6 & (mod=0x3 & XmmReg2); imm8
|
|
{
|
|
vexVVVV_XmmReg = vpsllw_avx( XmmReg2, imm8:1 );
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-433 PAGE 1553 LINE 80626
|
|
define pcodeop vpslld_avx ;
|
|
:VPSLLD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF2; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpslld_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-433 PAGE 1553 LINE 80629
|
|
:VPSLLD vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x72; reg_opcode=6 & (mod=0x3 & XmmReg2); imm8
|
|
{
|
|
vexVVVV_XmmReg = vpslld_avx( XmmReg2, imm8:1 );
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-433 PAGE 1553 LINE 80632
|
|
define pcodeop vpsllq_avx ;
|
|
:VPSLLQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF3; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpsllq_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSLLW/PSLLD/PSLLQ 4-433 PAGE 1553 LINE 80635
|
|
:VPSLLQ vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x73; reg_opcode=6 & (mod=0x3 & XmmReg2); imm8
|
|
{
|
|
vexVVVV_XmmReg = vpsllq_avx( XmmReg2, imm8:1 );
|
|
}
|
|
|
|
# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81305
|
|
define pcodeop vpsraw_avx ;
|
|
:VPSRAW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE1; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpsraw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81308
|
|
:VPSRAW vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x71; reg_opcode=4 & (mod=0x3 & XmmReg2); imm8
|
|
{
|
|
vexVVVV_XmmReg = vpsraw_avx( XmmReg2, imm8:1 );
|
|
}
|
|
|
|
# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81311
|
|
define pcodeop vpsrad_avx ;
|
|
:VPSRAD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE2; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpsrad_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81314
|
|
:VPSRAD vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x72; reg_opcode=4 & (mod=0x3 & XmmReg2); imm8
|
|
{
|
|
vexVVVV_XmmReg = vpsrad_avx( XmmReg2, imm8:1 );
|
|
}
|
|
|
|
# PSRLDQ 4-455 PAGE 1575 LINE 81873
|
|
define pcodeop vpsrldq_avx ;
|
|
:VPSRLDQ vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x73; reg_opcode=3 & (mod=0x3 & XmmReg2); imm8
|
|
{
|
|
vexVVVV_XmmReg = vpsrldq_avx( XmmReg2, imm8:1 );
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-457 PAGE 1577 LINE 82012
|
|
define pcodeop vpsrlw_avx ;
|
|
:VPSRLW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD1; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpsrlw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-457 PAGE 1577 LINE 82015
|
|
:VPSRLW vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x71; reg_opcode=2 & (mod=0x3 & XmmReg2); imm8
|
|
{
|
|
vexVVVV_XmmReg = vpsrlw_avx( XmmReg2, imm8:1 );
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-457 PAGE 1577 LINE 82018
|
|
define pcodeop vpsrld_avx ;
|
|
:VPSRLD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD2; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpsrld_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-457 PAGE 1577 LINE 82021
|
|
:VPSRLD vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x72; reg_opcode=2 & (mod=0x3 & XmmReg2); imm8
|
|
{
|
|
vexVVVV_XmmReg = vpsrld_avx( XmmReg2, imm8:1 );
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-457 PAGE 1577 LINE 82024
|
|
define pcodeop vpsrlq_avx ;
|
|
:VPSRLQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD3; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpsrlq_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSRLW/PSRLD/PSRLQ 4-457 PAGE 1577 LINE 82027
|
|
:VPSRLQ vexVVVV_XmmReg, XmmReg2, imm8 is $(VEX_NDD) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x73; reg_opcode=2 & (mod=0x3 & XmmReg2); imm8
|
|
{
|
|
vexVVVV_XmmReg = vpsrlq_avx( XmmReg2, imm8:1 );
|
|
}
|
|
|
|
# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82689
|
|
define pcodeop vpsubb_avx ;
|
|
:VPSUBB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpsubb_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82691
|
|
define pcodeop vpsubw_avx ;
|
|
:VPSUBW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpsubw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82694
|
|
define pcodeop vpsubd_avx ;
|
|
:VPSUBD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpsubd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSUBQ 4-476 PAGE 1596 LINE 83101
|
|
define pcodeop vpsubq_avx ;
|
|
:VPSUBQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpsubq_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83258
|
|
define pcodeop vpsubsb_avx ;
|
|
:VPSUBSB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpsubsb_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83261
|
|
define pcodeop vpsubsw_avx ;
|
|
:VPSUBSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpsubsw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83498
|
|
define pcodeop vpsubusb_avx ;
|
|
:VPSUBUSB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpsubusb_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83501
|
|
define pcodeop vpsubusw_avx ;
|
|
:VPSUBUSW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpsubusw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PTEST 4-487 PAGE 1607 LINE 83728
|
|
define pcodeop vptest_avx ;
|
|
:VPTEST XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x17; XmmReg1 ... & XmmReg2_m128
|
|
{
|
|
local val1 = XmmReg2_m128;
|
|
local val2 = XmmReg1;
|
|
ZF = (val1 & val2) == 0;
|
|
CF = (val1 & ~val2) == 0;
|
|
AF = 0;
|
|
OF = 0;
|
|
PF = 0;
|
|
SF = 0;
|
|
}
|
|
|
|
# PTEST 4-487 PAGE 1607 LINE 83730
|
|
:VPTEST YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x17; YmmReg1 ... & YmmReg2_m256
|
|
{
|
|
local val1 = YmmReg2_m256;
|
|
local val2 = YmmReg1;
|
|
ZF = (val1 & val2) == 0;
|
|
CF = (val1 & ~val2) == 0;
|
|
AF = 0;
|
|
OF = 0;
|
|
PF = 0;
|
|
SF = 0;
|
|
}
|
|
|
|
# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83929
|
|
define pcodeop vpunpckhbw_avx ;
|
|
:VPUNPCKHBW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x68; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpunpckhbw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83932
|
|
define pcodeop vpunpckhwd_avx ;
|
|
:VPUNPCKHWD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x69; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpunpckhwd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83935
|
|
define pcodeop vpunpckhdq_avx ;
|
|
:VPUNPCKHDQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x6A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpunpckhdq_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83938
|
|
define pcodeop vpunpckhqdq_avx ;
|
|
:VPUNPCKHQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x6D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpunpckhqdq_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84529
|
|
define pcodeop vpunpcklbw_avx ;
|
|
:VPUNPCKLBW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x60; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpunpcklbw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84532
|
|
define pcodeop vpunpcklwd_avx ;
|
|
:VPUNPCKLWD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x61; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpunpcklwd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84535
|
|
define pcodeop vpunpckldq_avx ;
|
|
:VPUNPCKLDQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x62; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpunpckldq_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84538
|
|
define pcodeop vpunpcklqdq_avx ;
|
|
:VPUNPCKLQDQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x6C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpunpcklqdq_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# PXOR 4-518 PAGE 1638 LINE 85495
|
|
:VPXOR XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vexVVVV_XmmReg ^ XmmReg2_m128;
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# RCPPS 4-526 PAGE 1646 LINE 85950
|
|
define pcodeop vrcpps_avx ;
|
|
:VRCPPS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x53; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vrcpps_avx( XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# RCPPS 4-526 PAGE 1646 LINE 85953
|
|
:VRCPPS YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x53; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vrcpps_avx( YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# RCPSS 4-528 PAGE 1648 LINE 86052
|
|
define pcodeop vrcpss_avx ;
|
|
:VRCPSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x53; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
|
|
{
|
|
local tmp:16 = vrcpss_avx( vexVVVV_XmmReg, XmmReg2_m32 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# ROUNDPD 4-564 PAGE 1684 LINE 87791
|
|
define pcodeop vroundpd_avx ;
|
|
:VROUNDPD XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x09; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
|
|
{
|
|
local tmp:16 = vroundpd_avx( XmmReg2_m128, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# ROUNDPD 4-564 PAGE 1684 LINE 87795
|
|
:VROUNDPD YmmReg1, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x09; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8
|
|
{
|
|
local tmp:32 = vroundpd_avx( YmmReg2_m256, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# ROUNDPS 4-567 PAGE 1687 LINE 87934
|
|
define pcodeop vroundps_avx ;
|
|
:VROUNDPS XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x08; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
|
|
{
|
|
local tmp:16 = vroundps_avx( XmmReg2_m128, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# ROUNDPS 4-567 PAGE 1687 LINE 87938
|
|
:VROUNDPS YmmReg1, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x08; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8
|
|
{
|
|
local tmp:32 = vroundps_avx( YmmReg2_m256, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# ROUNDSD 4-570 PAGE 1690 LINE 88058
|
|
define pcodeop vroundsd_avx ;
|
|
:VROUNDSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64, imm8 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64; imm8
|
|
{
|
|
local tmp:16 = vroundsd_avx( vexVVVV_XmmReg, XmmReg2_m64, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# ROUNDSS 4-572 PAGE 1692 LINE 88145
|
|
define pcodeop vroundss_avx ;
|
|
:VROUNDSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32, imm8 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32; imm8
|
|
{
|
|
local tmp:16 = vroundss_avx( vexVVVV_XmmReg, XmmReg2_m32, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# RSQRTPS 4-576 PAGE 1696 LINE 88301
|
|
define pcodeop vrsqrtps_avx ;
|
|
:VRSQRTPS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x52; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vrsqrtps_avx( XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# RSQRTPS 4-576 PAGE 1696 LINE 88304
|
|
:VRSQRTPS YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x52; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vrsqrtps_avx( YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# RSQRTSS 4-578 PAGE 1698 LINE 88399
|
|
define pcodeop vrsqrtss_avx ;
|
|
:VRSQRTSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x52; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
|
|
{
|
|
local tmp:16 = vrsqrtss_avx( vexVVVV_XmmReg, XmmReg2_m32 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# SHUFPD 4-617 PAGE 1737 LINE 90223
|
|
define pcodeop vshufpd_avx ;
|
|
:VSHUFPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xC6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
|
|
{
|
|
local tmp:16 = vshufpd_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# SHUFPD 4-617 PAGE 1737 LINE 90227
|
|
:VSHUFPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xC6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8
|
|
{
|
|
local tmp:32 = vshufpd_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# SHUFPS 4-622 PAGE 1742 LINE 90483
|
|
define pcodeop vshufps_avx ;
|
|
:VSHUFPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xC6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
|
|
{
|
|
local tmp:16 = vshufps_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# SHUFPS 4-622 PAGE 1742 LINE 90486
|
|
:VSHUFPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xC6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8
|
|
{
|
|
local tmp:32 = vshufps_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# SQRTPD 4-632 PAGE 1752 LINE 91001
|
|
define pcodeop vsqrtpd_avx ;
|
|
:VSQRTPD XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vsqrtpd_avx( XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# SQRTPD 4-632 PAGE 1752 LINE 91004
|
|
:VSQRTPD YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x51; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vsqrtpd_avx( YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# SQRTPS 4-635 PAGE 1755 LINE 91133
|
|
define pcodeop vsqrtps_avx ;
|
|
:VSQRTPS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vsqrtps_avx( XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# SQRTPS 4-635 PAGE 1755 LINE 91136
|
|
:VSQRTPS YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x51; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vsqrtps_avx( YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# SQRTSD 4-638 PAGE 1758 LINE 91272
|
|
define pcodeop vsqrtsd_avx ;
|
|
:VSQRTSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
{
|
|
local tmp:16 = vsqrtsd_avx( vexVVVV_XmmReg, XmmReg2_m64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# SQRTSS 4-640 PAGE 1760 LINE 91367
|
|
define pcodeop vsqrtss_avx ;
|
|
:VSQRTSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
|
|
{
|
|
local tmp:16 = vsqrtss_avx( vexVVVV_XmmReg, XmmReg2_m32 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# STMXCSR 4-647 PAGE 1767 LINE 91697
|
|
define pcodeop vstmxcsr_avx ;
|
|
:VSTMXCSR m32 is $(VEX_NONE) & $(VEX_LZ) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0xAE; reg_opcode=3 ... & m32
|
|
{
|
|
m32 = vstmxcsr_avx( );
|
|
}
|
|
|
|
# SUBPD 4-656 PAGE 1776 LINE 92116
|
|
define pcodeop vsubpd_avx ;
|
|
:VSUBPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vsubpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# SUBPD 4-656 PAGE 1776 LINE 92118
|
|
:VSUBPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vsubpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# SUBPS 4-659 PAGE 1779 LINE 92265
|
|
define pcodeop vsubps_avx ;
|
|
:VSUBPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vsubps_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# SUBPS 4-659 PAGE 1779 LINE 92267
|
|
:VSUBPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x5C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vsubps_avx( vexVVVV_YmmReg, YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# SUBSD 4-662 PAGE 1782 LINE 92419
|
|
:VSUBSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
{
|
|
local tmp:8 = vexVVVV_XmmReg[0,64] f- XmmReg2_m64[0,64];
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# SUBSS 4-664 PAGE 1784 LINE 92512
|
|
:VSUBSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
|
|
{
|
|
local tmp:4 = vexVVVV_XmmReg[0,32] f- XmmReg2_m32[0,32];
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# UCOMISD 4-683 PAGE 1803 LINE 93421
|
|
:VUCOMISD XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x2E; XmmReg1 ... & XmmReg2_m64
|
|
{
|
|
val1:8 = XmmReg1[0,64];
|
|
val2:8 = XmmReg2_m64[0,64];
|
|
fucompe(val1, val2);
|
|
}
|
|
|
|
# UCOMISS 4-685 PAGE 1805 LINE 93504
|
|
:VUCOMISS XmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x2E; XmmReg1 ... & XmmReg2_m32
|
|
{
|
|
val1:4 = XmmReg1[0,32];
|
|
val2:4 = XmmReg2_m32[0,32];
|
|
fucompe(val1, val2);
|
|
}
|
|
|
|
# UNPCKHPD 4-688 PAGE 1808 LINE 93623
|
|
define pcodeop vunpckhpd_avx ;
|
|
:VUNPCKHPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vunpckhpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# UNPCKHPD 4-688 PAGE 1808 LINE 93626
|
|
:VUNPCKHPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vunpckhpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# UNPCKHPS 4-692 PAGE 1812 LINE 93807
|
|
define pcodeop vunpckhps_avx ;
|
|
:VUNPCKHPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vunpckhps_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# UNPCKHPS 4-692 PAGE 1812 LINE 93810
|
|
:VUNPCKHPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vunpckhps_avx( vexVVVV_YmmReg, YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# UNPCKLPD 4-696 PAGE 1816 LINE 94039
|
|
define pcodeop vunpcklpd_avx ;
|
|
:VUNPCKLPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vunpcklpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# UNPCKLPD 4-696 PAGE 1816 LINE 94042
|
|
:VUNPCKLPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vunpcklpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# UNPCKLPS 4-700 PAGE 1820 LINE 94225
|
|
define pcodeop vunpcklps_avx ;
|
|
:VUNPCKLPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vunpcklps_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# UNPCKLPS 4-700 PAGE 1820 LINE 94228
|
|
:VUNPCKLPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vunpcklps_avx( vexVVVV_YmmReg, YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VBROADCAST 5-12 PAGE 1836 LINE 94909
|
|
:VBROADCASTSS XmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x18; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
|
|
{
|
|
local val:4 = XmmReg2_m32[0,32];
|
|
XmmReg1[0,32] = val;
|
|
XmmReg1[32,32] = val;
|
|
XmmReg1[64,32] = val;
|
|
XmmReg1[96,32] = val;
|
|
ZmmReg1 = zext(XmmReg1);
|
|
}
|
|
|
|
# VBROADCAST 5-12 PAGE 1836 LINE 94911
|
|
:VBROADCASTSS YmmReg1, XmmReg2_m32 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x18; (YmmReg1 & ZmmReg1) ... & XmmReg2_m32
|
|
{
|
|
local val:4 = XmmReg2_m32[0,32];
|
|
YmmReg1[0,32] = val;
|
|
YmmReg1[32,32] = val;
|
|
YmmReg1[64,32] = val;
|
|
YmmReg1[96,32] = val;
|
|
YmmReg1[128,32] = val;
|
|
YmmReg1[160,32] = val;
|
|
YmmReg1[192,32] = val;
|
|
YmmReg1[224,32] = val;
|
|
ZmmReg1 = zext(YmmReg1);
|
|
}
|
|
|
|
# VBROADCAST 5-12 PAGE 1836 LINE 94913
|
|
:VBROADCASTSD YmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x19; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
{
|
|
local val:8 = XmmReg2_m64[0,64];
|
|
YmmReg1[0,64] = val;
|
|
YmmReg1[64,64] = val;
|
|
YmmReg1[128,64] = val;
|
|
YmmReg1[192,64] = val;
|
|
ZmmReg1 = zext(YmmReg1);
|
|
}
|
|
|
|
# VBROADCAST 5-12 PAGE 1836 LINE 94915
|
|
:VBROADCASTF128 YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1A; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local val:16 = XmmReg2_m128;
|
|
YmmReg1[0,128] = val;
|
|
YmmReg1[128,128] = val;
|
|
ZmmReg1 = zext(YmmReg1);
|
|
}
|
|
|
|
# VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99102
|
|
:VEXTRACTF128 XmmReg2_m128, YmmReg1, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x19; (YmmReg1 & XmmReg2_m128_extend) ... & XmmReg2_m128; imm8
|
|
{
|
|
local ext:1 = (imm8:1 & 1) == 1;
|
|
|
|
local val:16 = YmmReg1[0,128];
|
|
|
|
if (ext == 0) goto <assign>;
|
|
|
|
val = YmmReg1[128,128];
|
|
|
|
<assign>
|
|
XmmReg2_m128 = val;
|
|
build XmmReg2_m128_extend;
|
|
}
|
|
|
|
# VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109703
|
|
:VINSERTF128 YmmReg1, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x18; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
|
|
{
|
|
local ext:1 = (imm8:1 & 1) == 1;
|
|
local src1_0 = vexVVVV_YmmReg[0, 128];
|
|
local src1_1 = vexVVVV_YmmReg[128, 128];
|
|
|
|
src2:16 = XmmReg2_m128;
|
|
|
|
YmmReg1[0,128] = src2;
|
|
YmmReg1[128,128] = src1_1;
|
|
|
|
if (ext == 0) goto <extend>;
|
|
|
|
YmmReg1[0,128] = src1_0;
|
|
YmmReg1[128,128] = src2;
|
|
|
|
<extend>
|
|
ZmmReg1 = zext(YmmReg1);
|
|
}
|
|
|
|
# VMASKMOV 5-318 PAGE 2142 LINE 110151
|
|
define pcodeop vmaskmovps_avx ;
|
|
:VMASKMOVPS XmmReg1, vexVVVV_XmmReg, m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2C; (XmmReg1 & ZmmReg1) ... & m128
|
|
{
|
|
local tmp:16 = vmaskmovps_avx( vexVVVV_XmmReg, m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VMASKMOV 5-318 PAGE 2142 LINE 110154
|
|
:VMASKMOVPS YmmReg1, vexVVVV_YmmReg, m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x2C; (YmmReg1 & ZmmReg1) ... & m256
|
|
{
|
|
local tmp:32 = vmaskmovps_avx( vexVVVV_YmmReg, m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VMASKMOV 5-318 PAGE 2142 LINE 110157
|
|
define pcodeop vmaskmovpd_avx ;
|
|
:VMASKMOVPD XmmReg1, vexVVVV_XmmReg, m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2D; (XmmReg1 & ZmmReg1) ... & m128
|
|
{
|
|
local tmp:16 = vmaskmovpd_avx( vexVVVV_XmmReg, m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VMASKMOV 5-318 PAGE 2142 LINE 110160
|
|
:VMASKMOVPD YmmReg1, vexVVVV_YmmReg, m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x2D; (YmmReg1 & ZmmReg1) ... & m256
|
|
{
|
|
local tmp:32 = vmaskmovpd_avx( vexVVVV_YmmReg, m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VMASKMOV 5-318 PAGE 2142 LINE 110163
|
|
:VMASKMOVPS m128, vexVVVV_XmmReg, XmmReg1 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2E; XmmReg1 ... & m128
|
|
{
|
|
m128 = vmaskmovps_avx( vexVVVV_XmmReg, XmmReg1 );
|
|
}
|
|
|
|
# VMASKMOV 5-318 PAGE 2142 LINE 110166
|
|
:VMASKMOVPS m256, vexVVVV_YmmReg, YmmReg1 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x2E; YmmReg1 ... & m256
|
|
{
|
|
m256 = vmaskmovps_avx( vexVVVV_YmmReg, YmmReg1 );
|
|
}
|
|
|
|
# VMASKMOV 5-318 PAGE 2142 LINE 110168
|
|
:VMASKMOVPD m128, vexVVVV_XmmReg, XmmReg1 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2F; XmmReg1 ... & m128
|
|
{
|
|
m128 = vmaskmovpd_avx( vexVVVV_XmmReg, XmmReg1 );
|
|
}
|
|
|
|
# VMASKMOV 5-318 PAGE 2142 LINE 110171
|
|
:VMASKMOVPD m256, vexVVVV_YmmReg, YmmReg1 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x2F; YmmReg1 ... & m256
|
|
{
|
|
m256 = vmaskmovpd_avx( vexVVVV_YmmReg, YmmReg1 );
|
|
}
|
|
|
|
# VPERM2F128 5-358 PAGE 2182 LINE 112216
|
|
define pcodeop vperm2f128_avx ;
|
|
:VPERM2F128 YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x06; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8
|
|
{
|
|
local tmp:32 = vperm2f128_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VPERMILPD 5-371 PAGE 2195 LINE 112860
|
|
define pcodeop vpermilpd_avx ;
|
|
:VPERMILPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x0D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpermilpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VPERMILPD 5-371 PAGE 2195 LINE 112863
|
|
:VPERMILPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x0D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vpermilpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VPERMILPD 5-371 PAGE 2195 LINE 112875
|
|
:VPERMILPD XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x05; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
|
|
{
|
|
local tmp:16 = vpermilpd_avx( XmmReg2_m128, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VPERMILPD 5-371 PAGE 2195 LINE 112877
|
|
:VPERMILPD YmmReg1, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x05; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8
|
|
{
|
|
local tmp:32 = vpermilpd_avx( YmmReg2_m256, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VPERMILPS 5-376 PAGE 2200 LINE 113158
|
|
define pcodeop vpermilps_avx ;
|
|
:VPERMILPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x0C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:16 = vpermilps_avx( vexVVVV_XmmReg, XmmReg2_m128 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VPERMILPS 5-376 PAGE 2200 LINE 113161
|
|
:VPERMILPS XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x04; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
|
|
{
|
|
local tmp:16 = vpermilps_avx( XmmReg2_m128, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VPERMILPS 5-376 PAGE 2200 LINE 113164
|
|
:VPERMILPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x0C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
local tmp:32 = vpermilps_avx( vexVVVV_YmmReg, YmmReg2_m256 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VPERMILPS 5-376 PAGE 2200 LINE 113167
|
|
:VPERMILPS YmmReg1, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x04; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8
|
|
{
|
|
local tmp:32 = vpermilps_avx( YmmReg2_m256, imm8:1 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VTESTPD/VTESTPS 5-560 PAGE 2384 LINE 122257
|
|
define pcodeop vtestps_avx ;
|
|
:VTESTPS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x0E; XmmReg1 ... & XmmReg2_m128
|
|
{
|
|
local val1 = XmmReg2_m128;
|
|
local val2 = XmmReg1;
|
|
local ztest = val1 & val2;
|
|
ZF = (ztest[31,1] | ztest[63,1] | ztest[95,1] | ztest[127,1]) == 0;
|
|
local ctest = val1 & ~val2;
|
|
CF = (ctest[31,1] | ctest[63,1] | ctest[95,1] | ctest[127,1]) == 0;
|
|
AF = 0;
|
|
OF = 0;
|
|
PF = 0;
|
|
SF = 0;
|
|
}
|
|
|
|
# VTESTPD/VTESTPS 5-560 PAGE 2384 LINE 122260
|
|
:VTESTPS YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x0E; YmmReg1 ... & YmmReg2_m256
|
|
{
|
|
local val1 = YmmReg2_m256;
|
|
local val2 = YmmReg1;
|
|
local ztest = val1 & val2;
|
|
ZF = (ztest[31,1] | ztest[63,1] | ztest[95,1] | ztest[127,1] | ztest[159,1] | ztest[191,1] | ztest[223,1] | ztest[255,1]) == 0;
|
|
local ctest = val1 & ~val2;
|
|
CF = (ctest[31,1] | ctest[63,1] | ctest[95,1] | ctest[127,1] | ctest[159,1] | ctest[191,1] | ctest[223,1] | ctest[255,1]) == 0;
|
|
AF = 0;
|
|
OF = 0;
|
|
PF = 0;
|
|
SF = 0;
|
|
}
|
|
|
|
# VTESTPD/VTESTPS 5-560 PAGE 2384 LINE 122263
|
|
define pcodeop vtestpd_avx ;
|
|
:VTESTPD XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x0F; XmmReg1 ... & XmmReg2_m128
|
|
{
|
|
local val1 = XmmReg2_m128;
|
|
local val2 = XmmReg1;
|
|
local ztest = val1 & val2;
|
|
ZF = (ztest[63,1] | ztest[127,1]) == 0;
|
|
local ctest = val1 & ~val2;
|
|
CF = (ctest[63,1] | ctest[127,1]) == 0;
|
|
AF = 0;
|
|
OF = 0;
|
|
PF = 0;
|
|
SF = 0;
|
|
}
|
|
|
|
# VTESTPD/VTESTPS 5-560 PAGE 2384 LINE 122266
|
|
:VTESTPD YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x0F; YmmReg1 ... & YmmReg2_m256
|
|
{
|
|
local val1 = YmmReg2_m256;
|
|
local val2 = YmmReg1;
|
|
local ztest = val1 & val2;
|
|
ZF = (ztest[63,1] | ztest[127,1] | ztest[191,1] | ztest[255,1]) == 0;
|
|
local ctest = val1 & ~val2;
|
|
CF = (ctest[63,1] | ctest[127,1] | ctest[191,1] | ctest[255,1]) == 0;
|
|
AF = 0;
|
|
OF = 0;
|
|
PF = 0;
|
|
SF = 0;
|
|
}
|
|
|
|
# XORPD 5-596 PAGE 2420 LINE 123828
|
|
:VXORPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
tmp:16 = XmmReg2_m128;
|
|
XmmReg1[0,64] = ( vexVVVV_XmmReg[0,64] ^ tmp[0,64] );
|
|
XmmReg1[64,64] = ( vexVVVV_XmmReg[64,64] ^ tmp[64,64] );
|
|
ZmmReg1 = zext(XmmReg1);
|
|
}
|
|
|
|
# XORPD 5-596 PAGE 2420 LINE 123831
|
|
:VXORPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x57; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
tmp:32 = YmmReg2_m256;
|
|
YmmReg1[0,64] = ( vexVVVV_YmmReg[0,64] ^ tmp[0,64] );
|
|
YmmReg1[64,64] = ( vexVVVV_YmmReg[64,64] ^ tmp[64,64] );
|
|
YmmReg1[128,64] = ( vexVVVV_YmmReg[128,64] ^ tmp[128,64] );
|
|
YmmReg1[192,64] = ( vexVVVV_YmmReg[192,64] ^ tmp[192,64] );
|
|
ZmmReg1 = zext(YmmReg1);
|
|
}
|
|
|
|
# XORPS 5-599 PAGE 2423 LINE 123953
|
|
:VXORPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
tmp:16 = XmmReg2_m128;
|
|
XmmReg1[0,32] = ( vexVVVV_XmmReg[0,32] ^ tmp[0,32] );
|
|
XmmReg1[32,32] = ( vexVVVV_XmmReg[32,32] ^ tmp[32,32] );
|
|
XmmReg1[64,32] = ( vexVVVV_XmmReg[64,32] ^ tmp[64,32] );
|
|
XmmReg1[96,32] = ( vexVVVV_XmmReg[96,32] ^ tmp[96,32] );
|
|
ZmmReg1 = zext(XmmReg1);
|
|
}
|
|
|
|
# XORPS 5-599 PAGE 2423 LINE 123956
|
|
:VXORPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x57; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
|
|
{
|
|
tmp:32 = YmmReg2_m256;
|
|
YmmReg1[0,32] = ( vexVVVV_YmmReg[0,32] ^ tmp[0,32] );
|
|
YmmReg1[32,32] = ( vexVVVV_YmmReg[32,32] ^ tmp[32,32] );
|
|
YmmReg1[64,32] = ( vexVVVV_YmmReg[64,32] ^ tmp[64,32] );
|
|
YmmReg1[96,32] = ( vexVVVV_YmmReg[96,32] ^ tmp[96,32] );
|
|
YmmReg1[128,32] = ( vexVVVV_YmmReg[128,32] ^ tmp[128,32] );
|
|
YmmReg1[160,32] = ( vexVVVV_YmmReg[160,32] ^ tmp[160,32] );
|
|
YmmReg1[192,32] = ( vexVVVV_YmmReg[192,32] ^ tmp[192,32] );
|
|
YmmReg1[224,32] = ( vexVVVV_YmmReg[224,32] ^ tmp[224,32] );
|
|
ZmmReg1 = zext(YmmReg1);
|
|
}
|
|
|
|
# INFO This file automatically generated by andre on Tue Apr 30 16:08:43 2024
|
|
# INFO Direct edits to this file may be lost in future updates
|
|
# INFO Command line arguments: ['--cpuid-match', 'F16C', '--sinc', '--skip-sinc', '../../../../../../../ghidra/Ghidra/Processors/x86/data/languages/avx_manual.sinc', '../../../../../../../ghidra/Ghidra/Processors/x86/data/languages/ia.sinc']
|
|
|
|
# VCVTPH2PS 5-34 PAGE 1858 LINE 95957
|
|
define pcodeop vcvtph2ps_f16c ;
|
|
:VCVTPH2PS XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x13; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
|
|
{
|
|
local tmp:16 = vcvtph2ps_f16c( XmmReg2_m64 );
|
|
ZmmReg1 = zext(tmp);
|
|
}
|
|
|
|
# VCVTPH2PS 5-34 PAGE 1858 LINE 95960
|
|
:VCVTPH2PS YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x13; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128
|
|
{
|
|
local tmp:32 = vcvtph2ps_f16c( XmmReg2_m128 );
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ZmmReg1 = zext(tmp);
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}
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# VCVTPS2PH 5-37 PAGE 1861 LINE 96110
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define pcodeop vcvtps2ph_f16c ;
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:VCVTPS2PH XmmReg2_m64, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x1D; XmmReg1 ... & XmmReg2_m64; imm8
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{
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XmmReg2_m64 = vcvtps2ph_f16c( XmmReg1, imm8:1 );
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}
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# VCVTPS2PH 5-37 PAGE 1861 LINE 96113
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:VCVTPS2PH XmmReg2_m128, YmmReg1, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x1D; (YmmReg1 & XmmReg2_m128_extend) ... & XmmReg2_m128; imm8
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{
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XmmReg2_m128 = vcvtps2ph_f16c( YmmReg1, imm8:1 );
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build XmmReg2_m128_extend;
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}
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