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board/spike/riscv64/readme.txt: remove obsolete comment

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At the time the spike_riscv64_defconfig was introduced in commit [1], it
was not possible to have a console input using Spike and OpenSBI for
RISC-V 32 bits. This limitation no longer applies, as upstream
components now implements support for this.

Buildroot commit [2] updated riscv-isa-sim (Spike), which now includes a
NS16550 uart emulation. This can be used by RV32 Linux Kernel. Finally,
a spike_riscv32_defconfig was added in [3].

This commit removes the comment about this limitation, since it no
longer applies.

[1] 24d07fdc14
[2] 853b7661bf
[3] a83ab3f4c8

Signed-off-by: Julien Olivain <ju.o@free.fr>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
This commit is contained in:
Julien Olivain
2024-07-12 20:33:18 +02:00
committed by Thomas Petazzoni
parent f6d9fa3692
commit 38d84178ce
1 changed files with 0 additions and 8 deletions
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8
board/spike/riscv64/readme.txt
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@@ -20,11 +20,6 @@ The boot is made with the standard RISC-V OpenSBI boot loader. In
order to keep the simulation simple, the rootfs is passed as an initrd order to keep the simulation simple, the rootfs is passed as an initrd
ramfs. ramfs.
Note: at the time of this writing, Spike v1.1.0 and OpenSBI v1.0 does
not support console input emulation for 32bit RISC-V systems. A 32bit
Linux system can boot and reach the login, but it's not possible to
login. See [4].
[1]. [1].
https://github.com/riscv-software-src/riscv-isa-sim/tree/v1.1.0#simulating-a-new-instruction https://github.com/riscv-software-src/riscv-isa-sim/tree/v1.1.0#simulating-a-new-instruction
@@ -34,6 +29,3 @@ https://github.com/riscv-software-src/riscv-isa-sim/tree/v1.1.0#debugging-with-g
[3]. [3].
https://github.com/riscv/riscv-openocd https://github.com/riscv/riscv-openocd
[4].
https://github.com/riscv-software-src/opensbi/blob/v1.0/lib/utils/sys/htif.c#L127