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Add TSTR synthetic opcode.

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This commit is contained in:
Alessandro Gatti
2020-05-07 03:32:38 +02:00
parent ee59487205
commit 07cc606f7c
1 changed files with 5 additions and 0 deletions
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5
Ghidra/Processors/CP1600/data/languages/CP1600.slaspec
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@@ -10,6 +10,7 @@ define register offset=0x20 size=4 [ contextreg ];
define token opcode_word (16)
target3_5 = (3, 5)
reg3_5 = (3, 5)
target0_2 = (0, 2)
reg0_2 = (0, 2)
reg0_1 = (0, 1)
operation_size = (2, 2)
@@ -368,6 +369,10 @@ define pcodeop SoftwareInterrupt;
TerminateCurrentInterrupt();
}
:TSTR reg0_2 is opcode6_9=0x0002 & reg0_2 & ((target0_2=0 & target3_5=0) | (target0_2=1 & target3_5=1) | (target0_2=2 & target3_5=2) | (target0_2=3 & target3_5=3) | (target0_2=4 & target3_5=4) | (target0_2=5 & target3_5=5) | (target0_2=6 & target3_5=6) | (target0_2=7 & target3_5=7)) {
resultFlags(reg0_2);
}
:XOR addr16, reg0_2 is opcode3_9=0x0078 & reg0_2 ; addr16 {
local ptr:2 = addr16;
reg0_2 = reg0_2 ^ *:2 ptr;