mirror/ghidra
1
0
Fork 0
mirror of https://github.com/NationalSecurityAgency/ghidra.git synced 2026-09-19 16:40:38 -09:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'GP-2162_ghidorahrex_mips_zeroreg_fix'

Browse Source
This commit is contained in:
ghidra1
2022-10-14 10:52:44 -04:00
parent 970c09a47d 8e2a52b756
commit 0b17f7d095
3 changed files with 43 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
Ghidra/Processors/MIPS/data/languages/mips.ldefs
View File

@@ -4,7 +4,7 @@
endian="big"
size="32"
variant="default"
version="1.6"
version="1.7"
slafile="mips32be.sla"
processorspec="mips32.pspec"
manualindexfile="../manuals/mipsM16.idx"
@@ -20,7 +20,7 @@
endian="little"
size="32"
variant="default"
version="1.6"
version="1.7"
slafile="mips32le.sla"
processorspec="mips32.pspec"
manualindexfile="../manuals/mipsM16.idx"
@@ -36,7 +36,7 @@
endian="big"
size="32"
variant="R6"
version="1.6"
version="1.7"
slafile="mips32R6be.sla"
processorspec="mips32R6.pspec"
manualindexfile="../manuals/mipsMic.idx"
@@ -50,7 +50,7 @@
endian="little"
size="32"
variant="R6"
version="1.6"
version="1.7"
slafile="mips32R6le.sla"
processorspec="mips32R6.pspec"
manualindexfile="../manuals/mipsMic.idx"
@@ -64,7 +64,7 @@
endian="big"
size="64"
variant="default"
version="1.6"
version="1.7"
slafile="mips64be.sla"
processorspec="mips64.pspec"
manualindexfile="../manuals/mipsM16.idx"
@@ -80,7 +80,7 @@
endian="little"
size="64"
variant="default"
version="1.6"
version="1.7"
slafile="mips64le.sla"
processorspec="mips64.pspec"
manualindexfile="../manuals/mipsM16.idx"
@@ -97,7 +97,7 @@
endian="big"
size="64"
variant="micro"
version="1.6"
version="1.7"
slafile="mips64be.sla"
processorspec="mips64micro.pspec"
manualindexfile="../manuals/mipsMic.idx"
@@ -112,7 +112,7 @@
endian="little"
size="64"
variant="micro"
version="1.6"
version="1.7"
slafile="mips64le.sla"
processorspec="mips64micro.pspec"
manualindexfile="../manuals/mipsMic.idx"
@@ -128,7 +128,7 @@
endian="big"
size="64"
variant="R6"
version="1.6"
version="1.7"
slafile="mips64be.sla"
processorspec="mips64R6.pspec"
manualindexfile="../manuals/mipsMic.idx"
@@ -143,7 +143,7 @@
endian="little"
size="64"
variant="R6"
version="1.6"
version="1.7"
slafile="mips64le.sla"
processorspec="mips64R6.pspec"
manualindexfile="../manuals/mipsMic.idx"
@@ -159,7 +159,7 @@
endian="big"
size="32"
variant="64-32addr"
version="1.6"
version="1.7"
slafile="mips64be.sla"
processorspec="mips64.pspec"
manualindexfile="../manuals/mipsM16.idx"
@@ -179,7 +179,7 @@
endian="little"
size="32"
variant="64-32addr"
version="1.6"
version="1.7"
slafile="mips64le.sla"
processorspec="mips64.pspec"
manualindexfile="../manuals/mipsM16.idx"
@@ -200,7 +200,7 @@
endian="little"
size="32"
variant="64-32addr-micro"
version="1.6"
version="1.7"
slafile="mips64le.sla"
processorspec="mips64micro.pspec"
manualindexfile="../manuals/mipsMic.idx"
@@ -220,7 +220,7 @@
endian="big"
size="32"
variant="64-32addr-micro"
version="1.6"
version="1.7"
slafile="mips64be.sla"
processorspec="mips64micro.pspec"
manualindexfile="../manuals/mipsMic.idx"
@@ -239,7 +239,7 @@
endian="big"
size="32"
variant="64-32addr-R6"
version="1.6"
version="1.7"
slafile="mips64be.sla"
processorspec="mips64R6.pspec"
manualindexfile="../manuals/mipsMic.idx"
@@ -258,7 +258,7 @@
endian="little"
size="32"
variant="64-32addr-R6"
version="1.6"
version="1.7"
slafile="mips64le.sla"
processorspec="mips64R6.pspec"
manualindexfile="../manuals/mipsMic.idx"
@@ -278,7 +278,7 @@
endian="big"
size="32"
variant="micro"
version="1.6"
version="1.7"
slafile="mips32be.sla"
processorspec="mips32micro.pspec"
manualindexfile="../manuals/mipsMic.idx"
@@ -293,7 +293,7 @@
endian="little"
size="32"
variant="micro"
version="1.6"
version="1.7"
slafile="mips32le.sla"
processorspec="mips32micro.pspec"
manualindexfile="../manuals/mipsMic.idx"

7
Ghidra/Processors/MIPS/data/languages/mips16.sinc
View File

@@ -76,7 +76,7 @@ attach variables [ ext_m16r32 m16_i8_r32 ] [
@ifdef MIPS64
attach variables [ m16_rxa m16_rya m16_rza m16_mv_rza]
[ s0_lo s1_lo v0_lo v1_lo a0_lo a1_lo a2_lo a3_lo ];
[ s0_lo s1_lo v0_lo v1_lo a0_lo a1_lo a2_lo a3_lo ];
attach variables [ ext_m16r32a m16_i8_r32a ] [
zero_lo at_lo v0_lo v1_lo a0_lo a1_lo a2_lo a3_lo
@@ -85,7 +85,7 @@ attach variables [ ext_m16r32a m16_i8_r32a ] [
t8_lo t9_lo k0_lo k1_lo gp_lo sp_lo s8_lo ra_lo
];
RZ: m16_rz is m16_rz { export m16_rz; }
RZ: m16_rz is m16_rz { export m16_rz; }
@else # !MIPS64
attach variables [ m16_rxa m16_rya m16_rza m16_mv_rza ]
@@ -106,10 +106,7 @@ RX: m16_rx is m16_rx { export m16_rx; }
RX32: m16_rx is m16_rx & m16_rxa { export m16_rxa; }
RY32: m16_ry is m16_ry & m16_rya { export m16_rya; }
RZ32: m16_rz is m16_rz & m16_rza { export m16_rza; }
#RMZ32: m16_mv_rz is m16_mv_rz & m16_mv_rza { export m16_mv_rza; }
#R32M: ext_m16r32 is ext_m16r32 & ext_m16r32a { export ext_m16r32a; }
#R32I: m16_i8_r32 is m16_i8_r32 & m16_i8_r32a { export m16_i8_r32a; }
attach names [ ext_svrs_sreg][
_ "s0" "s1" "s0-s1"

30
Ghidra/Processors/MIPS/data/languages/mipsmicro.sinc
View File

@@ -269,39 +269,55 @@ attach names [ ext_t4_name][
];
RD5L: mic_rd32_5 is mic_rd32_5 & mic_rd32_5lo { export mic_rd32_5lo; }
RD5L: mic_rd32_5 is mic_rd32_5 & mic_rd32_5lo=0 { tmp:4 = 0; export tmp; }
RD7R1: mic_rd7 is mic_rd7 & REL6=0 { export mic_rd7; }
RD7R1: mic_rd1 is mic_rd1 & REL6=1 { export mic_rd1; }
RSEXTL: ext_32_rs1 is ext_32_rs1 & ext_32_rs1lo { export ext_32_rs1lo; }
RS0L: mic_rs32_0 is mic_rs32_0 & mic_rs32_0lo { export mic_rs32_0lo; }
RS4L: mic_rs4 is mic_rs4 & mic_rs4lo { export mic_rs4lo; }
RSEXTL: ext_32_rs1 is ext_32_rs1 & ext_32_rs1lo=0 { tmp:4 = 0; export tmp; }
RS0R4: mic_rs0 is mic_rs0 & REL6=0 { export mic_rs0; }
RS0R4: mic_rs4 is mic_rs4 & REL6=1 { export mic_rs4; }
RS0R5: mic_rs32_0 is mic_rs32_0 & REL6=0 { export mic_rs32_0; }
RS0R5: mic_rs32_5 is mic_rs32_5 & REL6=1 { export mic_rs32_5; }
RS0L: mic_rs32_0 is mic_rs32_0 & mic_rs32_0lo { export mic_rs32_0lo; }
RS0L: mic_rs32_0 is mic_rs32_0 & mic_rs32_0lo=0 { tmp:4 = 0; export tmp; }
RS4L: mic_rs4 is mic_rs4 & mic_rs4lo { export mic_rs4lo; }
RS0R4: mic_rs0 is mic_rs0 & REL6=0 { export mic_rs0; }
RS0R4: mic_rs4 is mic_rs4 & REL6=1 { export mic_rs4; }
RS0R5: mic_rs32_0 is mic_rs32_0 & REL6=0 { export mic_rs32_0; }
RS0R5: mic_rs32_0 is mic_rs32_0 & mic_rs32_0=0 & REL6=0 { tmp:$(REGSIZE) = 0; export tmp; }
RS0R5: mic_rs32_5 is mic_rs32_5 & REL6=1 { export mic_rs32_5; }
RS0R5: mic_rs32_5 is mic_rs32_5 & mic_rs32_5=0 & REL6=1 { tmp:$(REGSIZE) = 0; export tmp; }
RS1R7L: mic_rs1 is mic_rs1 & mic_rs1lo & REL6=0 { export mic_rs1lo; }
RS1R7L: mic_rs7 is mic_rs7 & mic_rs7lo & REL6=1 { export mic_rs7lo; }
RT4L: mic_rt4 is mic_rt4 & mic_rt4lo { export mic_rt4lo; }
RT5L: mic_rt32_5 is mic_rt32_5 & mic_rt32_5lo { export mic_rt32_5lo; }
RT5L: mic_rt32_5 is mic_rt32_5 & mic_rt32_5lo=0 { tmp:4 = 0; export tmp; }
RT3R7: mic_rt3 is mic_rt3 & REL6=0 { export mic_rt3; }
RT3R7: mic_rt7 is mic_rt7 & REL6=1 { export mic_rt7; }
RST7R5: mic_rs7 is mic_rs7 & REL6=0 { export mic_rs7; }
RST7R5: mic_rt32_5 is mic_rt32_5 & REL6=1 { export mic_rt32_5; }
RST7R5: mic_rt32_5 is mic_rt32_5 & mic_rt32_5=0 & REL6=1 { tmp:$(REGSIZE) = 0; export tmp; }
RT5RD5: ext_32_rd is ext_32_rd & REL6=0 { export ext_32_rd; }
RT5RD5: ext_32_rd is ext_32_rd & REL6=0 { export ext_32_rd; }
RT5RD5: ext_32_rd is ext_32_rd & ext_32_rd=0 & REL6=0 { tmp:$(REGSIZE) = 0; export tmp; }
RT5RD5: micb_rd32 is micb_rd32 & REL6=1 { export micb_rd32; }
RT5RD5: micb_rd32 is micb_rd32 & micb_rd32=0 & REL6=1 { tmp:$(REGSIZE) = 0; export tmp; }
RS0RT5: mic_rs32_0 is mic_rs32_0 & REL6=0 { export mic_rs32_0; }
RS0RT5: mic_rs32_0 is mic_rs32_0 & mic_rs32_0=0 & REL6=0 { tmp:$(REGSIZE) = 0; export tmp; }
RS0RT5: mic_rt32_5 is mic_rt32_5 & REL6=1 { export mic_rt32_5; }
RS0RT5: mic_rt32_5 is mic_rt32_5 & mic_rt32_5=0 & REL6=1 { tmp:$(REGSIZE) = 0; export tmp; }
ENCRS: mic_encrs is mic_encrs & REL6=0 { export mic_encrs; }
ENCRS: mic_encrs is mic_encrs & mic_encrs=0 & REL6=0 { tmp:$(REGSIZE) = 0; export tmp; }
ENCRS: ext_16_rs is ext_16_rs & REL6=1 { export ext_16_rs; }
ENCRS: ext_16_rs is ext_16_rs & ext_16_rs=0 & REL6=1 { tmp:$(REGSIZE) = 0; export tmp; }
Abs26_mic1: reloc is ext_32_code & micb_imm16 [ reloc=((inst_start+4) $and 0xfffffffff8000000)+2*(micb_imm16 | (ext_32_code << 16)); ] { export *:$(ADDRSIZE) reloc; }
Abs26_mic2: reloc is ext_32_code & micb_imm16 [ reloc=((inst_start+4) $and 0xfffffffff0000000)+4*(micb_imm16 | (ext_32_code << 16)); ] { export *:$(ADDRSIZE) reloc; }