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GP-3083: Fixed ARM thumb constructor ordering issues

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This commit is contained in:
ghidorahrex
2023-02-07 18:40:19 +00:00
parent d9fb11af79
commit 37ccf381fd
2 changed files with 148 additions and 130 deletions
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38
Ghidra/Processors/ARM/data/languages/ARM.ldefs
View File

@@ -5,7 +5,7 @@
endian="little"
size="32"
variant="v8"
version="1.106"
version="1.107"
slafile="ARM8_le.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
@@ -29,7 +29,7 @@
endian="little"
size="32"
variant="v8T"
version="1.106"
version="1.107"
slafile="ARM8_le.sla"
processorspec="ARMtTHUMB.pspec"
manualindexfile="../manuals/ARM.idx"
@@ -49,7 +49,7 @@
instructionEndian="little"
size="32"
variant="v8LEInstruction"
version="1.106"
version="1.107"
slafile="ARM8_le.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
@@ -64,7 +64,7 @@
endian="big"
size="32"
variant="v8"
version="1.106"
version="1.107"
slafile="ARM8_be.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
@@ -87,7 +87,7 @@
endian="big"
size="32"
variant="v8T"
version="1.106"
version="1.107"
slafile="ARM8_be.sla"
processorspec="ARMtTHUMB.pspec"
manualindexfile="../manuals/ARM.idx"
@@ -104,7 +104,7 @@
endian="little"
size="32"
variant="v7"
version="1.106"
version="1.107"
slafile="ARM7_le.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
@@ -124,7 +124,7 @@
instructionEndian="little"
size="32"
variant="v7LEInstruction"
version="1.106"
version="1.107"
slafile="ARM7_le.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
@@ -139,7 +139,7 @@
endian="big"
size="32"
variant="v7"
version="1.106"
version="1.107"
slafile="ARM7_be.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
@@ -157,7 +157,7 @@
endian="little"
size="32"
variant="Cortex"
version="1.106"
version="1.107"
slafile="ARM7_le.sla"
processorspec="ARMCortex.pspec"
manualindexfile="../manuals/ARM.idx"
@@ -177,7 +177,7 @@
endian="big"
size="32"
variant="Cortex"
version="1.106"
version="1.107"
slafile="ARM7_be.sla"
processorspec="ARMCortex.pspec"
manualindexfile="../manuals/ARM.idx"
@@ -196,7 +196,7 @@
endian="little"
size="32"
variant="v6"
version="1.106"
version="1.107"
slafile="ARM6_le.sla"
processorspec="ARMt_v6.pspec"
manualindexfile="../manuals/ARM.idx"
@@ -216,7 +216,7 @@
endian="big"
size="32"
variant="v6"
version="1.106"
version="1.107"
slafile="ARM6_be.sla"
processorspec="ARMt_v6.pspec"
manualindexfile="../manuals/ARM.idx"
@@ -236,7 +236,7 @@
endian="little"
size="32"
variant="v5t"
version="1.106"
version="1.107"
slafile="ARM5t_le.sla"
processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx"
@@ -254,7 +254,7 @@
endian="big"
size="32"
variant="v5t"
version="1.106"
version="1.107"
slafile="ARM5t_be.sla"
processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx"
@@ -272,7 +272,7 @@
endian="little"
size="32"
variant="v5"
version="1.106"
version="1.107"
slafile="ARM5_le.sla"
processorspec="ARM_v45.pspec"
manualindexfile="../manuals/ARM.idx"
@@ -304,7 +304,7 @@
endian="little"
size="32"
variant="v4t"
version="1.106"
version="1.107"
slafile="ARM4t_le.sla"
processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx"
@@ -321,7 +321,7 @@
endian="big"
size="32"
variant="v4t"
version="1.106"
version="1.107"
slafile="ARM4t_be.sla"
processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx"
@@ -338,7 +338,7 @@
endian="little"
size="32"
variant="v4"
version="1.106"
version="1.107"
slafile="ARM4_le.sla"
processorspec="ARM_v45.pspec"
manualindexfile="../manuals/ARM.idx"
@@ -358,7 +358,7 @@
endian="big"
size="32"
variant="v4"
version="1.106"
version="1.107"
slafile="ARM4_be.sla"
processorspec="ARM_v45.pspec"
manualindexfile="../manuals/ARM.idx"

240
Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
View File

@@ -2114,6 +2114,22 @@ define pcodeop ExclusiveAccess;
Rt1215 = *tmp;
}
# overlaps patterns with the other ldr intructions when Rn==1111, therefore it must occur first
:ldr^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf85 & sop0003=15; Rt1215 & RtGotoCheck) & PcrelOffset12
{
build ItCond;
build PcrelOffset12;
Rt1215 = PcrelOffset12:4;
build RtGotoCheck;
}
:ldr^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf8d & sop0003=15; Rt1215 & RtGotoCheck) & PcrelOffset12
{
build ItCond;
build PcrelOffset12;
Rt1215 = PcrelOffset12:4;
build RtGotoCheck;
}
:ldr^ItCond^".w" Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf8d; Rt1215 & RtGotoCheck) & RnIndirect12
{
@@ -2131,23 +2147,6 @@ define pcodeop ExclusiveAccess;
build RtGotoCheck;
}
:ldr^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf8d & sop0003=15; Rt1215 & RtGotoCheck) & PcrelOffset12
{
build ItCond;
build PcrelOffset12;
Rt1215 = PcrelOffset12:4;
build RtGotoCheck;
}
# overlaps pattern with next ldr intruction, must occur first
:ldr^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf85 & sop0003=15; Rt1215 & RtGotoCheck) & PcrelOffset12
{
build ItCond;
build PcrelOffset12;
Rt1215 = PcrelOffset12:4;
build RtGotoCheck;
}
:ldr^ItCond^".w" Rt1215,[Rn0003,Rm0003] is TMode=1 & ItCond & op4=0xf85 & Rn0003; Rt1215 & RtGotoCheck & thc1111=0 & sop0610=0 & thc0405=0 & Rm0003
{
build ItCond;
@@ -2164,6 +2163,23 @@ define pcodeop ExclusiveAccess;
build RtGotoCheck;
}
:ldrb^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf81 & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
build PcrelOffset12;
tmp:1 = PcrelOffset12:1;
Rt1215 = zext(tmp);
}
# overlaps patterns with the other ldrb intructions when Rn==1111, therefore it must occur first
:ldrb^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf89 & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
build PcrelOffset12;
tmp:1 = PcrelOffset12:1;
Rt1215 = zext(tmp);
}
:ldrb^ItCond^".w" Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf89; Rt1215) & RnIndirect12
{
build ItCond;
@@ -2180,21 +2196,6 @@ define pcodeop ExclusiveAccess;
Rt1215 = zext(tmp);
}
:ldrb^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf89 & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
build PcrelOffset12;
tmp:1 = PcrelOffset12:1;
Rt1215 = zext(tmp);
}
:ldrb^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf81 & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
build PcrelOffset12;
tmp:1 = PcrelOffset12:1;
Rt1215 = zext(tmp);
}
:ldrb^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf81 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003
{
build ItCond;
@@ -2203,6 +2204,7 @@ define pcodeop ExclusiveAccess;
Rt1215 = zext(val);
}
:ldrbt^ItCond^".w" Rt1215,[Rn0003,"#"^Immed8] is TMode=1 & ItCond & op4=0xf81 & Rn0003; Rt1215 & thc0811=14 & Immed8
{
build ItCond;
@@ -2211,6 +2213,17 @@ define pcodeop ExclusiveAccess;
Rt1215 = zext(val);
}
# overlaps patterns with the other ldrd intructions when Rn==1111, therefore it must occur first
:ldrd^ItCond Rt1215,Rt0811,Pcrel8_s8 is TMode=1 & ItCond & op9=0x74 & thc0606=1 & thc0404=1 & sop0003=15; Rt1215 & Rt0811 & Pcrel8_s8
{
build ItCond;
build Pcrel8_s8;
local val = Pcrel8_s8;
Rt1215 = val(4);
Rt0811 = val(0);
}
:ldrd^ItCond Rt1215,Rt0811,RnIndirectPUW1 is TMode=1 & ItCond & (op9=0x74 & thc0606=1 & thc0404=1 & Rn0003; Rt1215 & Rt0811) & $(RN_INDIRECT_PUW1)
{
build ItCond;
@@ -2219,13 +2232,42 @@ define pcodeop ExclusiveAccess;
Rt0811 = *(RnIndirectPUW1+4);
}
:ldrd^ItCond Rt1215,Rt0811,Pcrel8_s8 is TMode=1 & ItCond & op9=0x74 & thc0606=1 & thc0404=1 & sop0003=15; Rt1215 & Rt0811 & Pcrel8_s8
# pldw must come before ldrh.w because of overlap of Rt != 1111 in ldrh.w
:pldw^ItCond Rn0003,"#"^offset12 is TMode=1 & ItCond & op6=0x3e2 & thwbit=1 & thc0404=1 & Rn0003; op12=0xf & offset12
{
build ItCond;
addr:4 = Rn0003 + offset12;
HintPreloadDataForWrite(addr);
}
:pldw^ItCond Rn0003,"#-"^immed8 is TMode=1 & ItCond & op6=0x3e0 & thwbit=1 & thc0404=1 & Rn0003; op8=0xfc & immed8
{
build ItCond;
addr:4 = Rn0003 - immed8;
HintPreloadDataForWrite(addr);
}
:pldw^ItCond Rn0003,Rm0003,"lsl #"^thc0405 is TMode=1 & ItCond & op6=0x3e0 & thwbit=1 & thc0404=1 & Rn0003; op8=0xf0 & thc0607=0 & thc0405 & Rm0003
{
build ItCond;
addr:4 = Rn0003 + (Rm0003 << thc0405);
HintPreloadDataForWrite(addr);
}
# overlaps patterns with the other ldrh intructions when Rn==1111, therefore it must occur first
:ldrh^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf83 & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
build Pcrel8_s8;
local val = Pcrel8_s8;
Rt1215 = val(4);
Rt0811 = val(0);
local tmp = PcrelOffset12:2;
Rt1215 = zext(tmp);
}
:ldrh^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf8b & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
tmp:2 = PcrelOffset12:2;
Rt1215 = zext(tmp);
}
:ldrh.w^ItCond Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf8B; Rt1215) & RnIndirect12
@@ -2244,19 +2286,6 @@ define pcodeop ExclusiveAccess;
Rt1215 = zext(tmp);
}
:ldrh^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf83 & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
local tmp = PcrelOffset12:2;
Rt1215 = zext(tmp);
}
:ldrh^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op4=0xf8b & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
tmp:2 = PcrelOffset12:2;
Rt1215 = zext(tmp);
}
:ldrh^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf83 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003
{
build ItCond;
@@ -2273,6 +2302,44 @@ define pcodeop ExclusiveAccess;
Rt1215 = zext(val);
}
# pli moevd above ldrsb to avoid conflict for ldrsb when Rt == 1111
:pli^ItCond Rn0003,"#"^offset12 is TMode=1 & ItCond & op4=0xf99 & Rn0003; op12=0xf & offset12
{
build ItCond;
addr:4 = Rn0003 + offset12;
HintPreloadInstruction(addr);
}
:pli^ItCond Rn0003,"#-"^immed8 is TMode=1 & ItCond & op4=0xf91 & Rn0003; op8=0xfc & immed8
{
build ItCond;
addr:4 = Rn0003 - immed8;
HintPreloadInstruction(addr);
}
:pli^ItCond PcrelOffset12 is TMode=1 & ItCond & (op8=0xf9 & thc0506=0 & thc0004=0x1f; thc1215=0xf) & PcrelOffset12
{
build ItCond;
HintPreloadInstruction(PcrelOffset12);
}
:pli^ItCond Rn0003,Rm0003"lsl #"^thc0405 is TMode=1 & ItCond & op4=0xf91 & Rn0003; op6=0x3c0 & thc0405 & Rm0003
{
build ItCond;
addr:4 = Rn0003 + (Rm0003 << thc0405);
HintPreloadInstruction(addr);
}
# overlaps patterns with the other ldrsb intructions when Rn==1111, therefore it must occur first
:ldrsb^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op8=0xf9 & thc0506=0 & thc0404=1 & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
tmp:1 = *PcrelOffset12;
Rt1215 = sext(tmp);
}
:ldrsb^ItCond^".w" Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf99; Rt1215) & RnIndirect12
{
build ItCond;
@@ -2288,13 +2355,6 @@ define pcodeop ExclusiveAccess;
Rt1215 = sext(tmp);
}
:ldrsb^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op8=0xf9 & thc0506=0 & thc0404=1 & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
tmp:1 = *PcrelOffset12;
Rt1215 = sext(tmp);
}
:ldrsb^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf91 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003
{
build ItCond;
@@ -2311,6 +2371,16 @@ define pcodeop ExclusiveAccess;
Rt1215 = sext(val);
}
# overlaps patterns with the other ldr intructions when Rn==1111, therefore it must occur first
:ldrsh^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op8=0xf9 & thc0506=1 & thc0404=1 & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
build PcrelOffset12;
tmp:2 = *PcrelOffset12;
Rt1215 = sext(tmp);
}
:ldrsh^ItCond^".w" Rt1215,RnIndirect12 is TMode=1 & ItCond & (op4=0xf9B; Rt1215) & RnIndirect12
{
build ItCond;
@@ -2326,14 +2396,6 @@ define pcodeop ExclusiveAccess;
Rt1215 = sext(tmp);
}
:ldrsh^ItCond^".w" Rt1215,PcrelOffset12 is TMode=1 & ItCond & (op8=0xf9 & thc0506=1 & thc0404=1 & sop0003=15; Rt1215) & PcrelOffset12
{
build ItCond;
build PcrelOffset12;
tmp:2 = *PcrelOffset12;
Rt1215 = sext(tmp);
}
:ldrsh^ItCond^".w" Rt1215,[Rn0003,Rm0003,"lsl #"^thc0405] is TMode=1 & ItCond & op4=0xf93 & Rn0003; Rt1215 & thc1111=0 & sop0610=0 & thc0405 & Rm0003
{
build ItCond;
@@ -3023,12 +3085,6 @@ thspsrmask: spsr^thpsrmask is thpsrmask & spsr { export thpsrmask; }
HintPreloadData(addr);
}
:pldw^ItCond Rn0003,"#"^offset12 is TMode=1 & ItCond & op6=0x3e2 & thwbit=1 & thc0404=1 & Rn0003; op12=0xf & offset12
{
build ItCond;
addr:4 = Rn0003 + offset12;
HintPreloadDataForWrite(addr);
}
:pld^ItCond Rn0003,"#-"^immed8 is TMode=1 & ItCond & op6=0x3e0 & thwbit=0 & thc0404=1 & Rn0003; op8=0xfc & immed8
{
@@ -3037,13 +3093,6 @@ thspsrmask: spsr^thpsrmask is thpsrmask & spsr { export thpsrmask; }
HintPreloadData(addr);
}
:pldw^ItCond Rn0003,"#-"^immed8 is TMode=1 & ItCond & op6=0x3e0 & thwbit=1 & thc0404=1 & Rn0003; op8=0xfc & immed8
{
build ItCond;
addr:4 = Rn0003 - immed8;
HintPreloadDataForWrite(addr);
}
:pld^ItCond PcrelOffset12 is TMode=1 & ItCond & (op8=0xf8 & thc0506=0 & thc0004=0x1f; thc1215=0xf) & PcrelOffset12
{
build ItCond;
@@ -3057,40 +3106,9 @@ thspsrmask: spsr^thpsrmask is thpsrmask & spsr { export thpsrmask; }
HintPreloadData(addr);
}
:pldw^ItCond Rn0003,Rm0003,"lsl #"^thc0405 is TMode=1 & ItCond & op6=0x3e0 & thwbit=1 & thc0404=1 & Rn0003; op8=0xf0 & thc0607=0 & thc0405 & Rm0003
{
build ItCond;
addr:4 = Rn0003 + (Rm0003 << thc0405);
HintPreloadDataForWrite(addr);
}
# pld.w moved above ldrh to avoid conflicts
:pli^ItCond Rn0003,"#"^offset12 is TMode=1 & ItCond & op4=0xf99 & Rn0003; op12=0xf & offset12
{
build ItCond;
addr:4 = Rn0003 + offset12;
HintPreloadInstruction(addr);
}
:pli^ItCond Rn0003,"#-"^immed8 is TMode=1 & ItCond & op4=0xf91 & Rn0003; op8=0xfc & immed8
{
build ItCond;
addr:4 = Rn0003 - immed8;
HintPreloadInstruction(addr);
}
:pli^ItCond PcrelOffset12 is TMode=1 & ItCond & (op8=0xf9 & thc0506=0 & thc0004=0x1f; thc1215=0xf) & PcrelOffset12
{
build ItCond;
HintPreloadInstruction(PcrelOffset12);
}
:pli^ItCond Rn0003,Rm0003"lsl #"^thc0405 is TMode=1 & ItCond & op4=0xf91 & Rn0003; op6=0x3c0 & thc0405 & Rm0003
{
build ItCond;
addr:4 = Rn0003 + (Rm0003 << thc0405);
HintPreloadInstruction(addr);
}
#pli moved above ldrsb
@endif # VERSION_6T2 || VERSION_7