mirror/ghidra
1
0
Fork 0
mirror of https://github.com/NationalSecurityAgency/ghidra.git synced 2026-09-25 17:00:36 -09:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'GP-2905_emteere_spacebaseissue' into patch (#4770)

Browse Source
This commit is contained in:
Ryan Kurtz
2023-02-07 10:54:56 -05:00
parent 65f20da73c 93c291ba72
commit d9fb11af79
18 changed files with 43 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
Ghidra/Framework/SoftwareModeling/src/main/java/ghidra/program/model/pcode/LocalSymbolMap.java
View File

@@ -26,6 +26,7 @@ import ghidra.program.model.data.DataType;
import ghidra.program.model.data.Undefined;
import ghidra.program.model.listing.*;
import ghidra.program.model.symbol.*;
import ghidra.util.Msg;
import ghidra.util.SystemUtilities;
/**
@@ -576,9 +577,20 @@ public class LocalSymbolMap {
}
public MappedVarKey(VariableStorage store, Address pcad) {
addr = store.getFirstVarnode().getAddress();
if (!addr.isStackAddress()) {
// first use not supported for stack
Varnode first = store.getFirstVarnode();
if (first != null) {
addr = first.getAddress();
if (!addr.isStackAddress()) {
// first use not supported for stack
pcaddr = pcad;
}
}
else {
// Hack: first can come back as null if something has gone wrong, such as a
// spacebase without a range.
Msg.warn(this, "First use is null, possible spacebase/global range issue." +
"There will be variable rename issues");
pcaddr = pcad;
}
}
@@ -589,12 +601,14 @@ public class LocalSymbolMap {
if (!SystemUtilities.isEqual(pcaddr, op.pcaddr)) {
return false;
}
return addr.equals(op.addr);
return SystemUtilities.isEqual(addr, op.addr);
}
@Override
public int hashCode() {
int hash1 = addr.hashCode();
// Hack: addr should not be null, but can be if something in decompiler went wrong
// most likely a spacebase without a corresponding global register range entry
int hash1 = addr != null ? addr.hashCode() : 0;
int hash2 = pcaddr != null ? pcaddr.hashCode() : 0;
return (hash1 << 4) ^ hash2;
}

2
Ghidra/Processors/MIPS/data/languages/mips32_fp64.cspec
View File

@@ -16,9 +16,7 @@
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="gp"/>
<range space="ram"/>
<range space="register" first="0x2000" last="0x2fff"/>
</global>

2
Ghidra/Processors/MIPS/data/languages/mips32be.cspec
View File

@@ -16,9 +16,7 @@
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="gp"/>
<range space="ram"/>
<range space="register" first="0x2000" last="0x2fff"/>
</global>

2
Ghidra/Processors/MIPS/data/languages/mips32be_eabi.cspec
View File

@@ -16,9 +16,7 @@
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="gp"/>
<range space="ram"/>
<range space="register" first="0x2000" last="0x2fff"/>
</global>

2
Ghidra/Processors/MIPS/data/languages/mips32le.cspec
View File

@@ -16,9 +16,7 @@
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="gp"/>
<range space="ram"/>
<range space="register" first="0x2000" last="0x2fff"/>
</global>

2
Ghidra/Processors/MIPS/data/languages/mips32le_eabi.cspec
View File

@@ -16,9 +16,7 @@
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="gp"/>
<range space="ram"/>
<range space="register" first="0x2000" last="0x2fff"/>
</global>

2
Ghidra/Processors/MIPS/data/languages/mips64.cspec
View File

@@ -14,9 +14,7 @@
</data_organization>
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="gp"/>
<range space="ram"/>
<range space="register" first="0x2000" last="0x2fff"/>
</global>

2
Ghidra/Processors/MIPS/data/languages/mips64_32_n32.cspec
View File

@@ -35,9 +35,7 @@
</data_organization>
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="gp"/>
<range space="ram"/>
<range space="register" first="0x2000" last="0x2fff"/>
</global>

2
Ghidra/Processors/MIPS/data/languages/mips64_32_o32.cspec
View File

@@ -40,9 +40,7 @@
</data_organization>
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="gp"/>
<range space="ram"/>
<range space="register" first="0x2000" last="0x2fff"/>
</global>

2
Ghidra/Processors/MIPS/data/languages/mips64_32_o64.cspec
View File

@@ -25,9 +25,7 @@
</data_organization>
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="gp"/>
<range space="ram"/>
<range space="register" first="0x2000" last="0x2fff"/>
</global>

6
Ghidra/Processors/MIPS/src/main/java/ghidra/app/plugin/core/analysis/MipsAddressAnalyzer.java
View File

@@ -477,6 +477,12 @@ public class MipsAddressAnalyzer extends ConstantPropagationAnalyzer {
coveredSet.add(func.getBody());
amgr.codeDefined(coveredSet);
}
else {
// else T9 was set at the beginning of the function
// something within the function must have set it to
// an unknown value, so can continue
return null;
}
}
catch (ContextChangeException e) {
throw new AssertException("Unexpected Exception", e);

1
Ghidra/Processors/RISCV/data/languages/riscv32-fp.cspec
View File

@@ -20,7 +20,6 @@
<entry size="8" alignment="4" />
</size_alignment_map>
</data_organization>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="ram"/>
<register name="gp"/>

1
Ghidra/Processors/RISCV/data/languages/riscv32.cspec
View File

@@ -18,7 +18,6 @@
<entry size="8" alignment="4" />
</size_alignment_map>
</data_organization>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="ram"/>
<register name="gp"/>

1
Ghidra/Processors/RISCV/data/languages/riscv64-fp.cspec
View File

@@ -20,7 +20,6 @@
<entry size="8" alignment="8" />
</size_alignment_map>
</data_organization>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="ram"/>
<register name="gp"/>

1
Ghidra/Processors/RISCV/data/languages/riscv64.cspec
View File

@@ -18,7 +18,6 @@
<entry size="8" alignment="8" />
</size_alignment_map>
</data_organization>
<spacebase name="gp" register="gp" space="ram"/>
<global>
<range space="ram"/>
<register name="gp"/>

8
Ghidra/Processors/tricore/data/languages/tricore.cspec
View File

@@ -20,12 +20,12 @@
<entry size="8" alignment="4" />
</size_alignment_map>
</data_organization>
<spacebase name="a0_" register="a0" space="ram"/>
<spacebase name="a1_" register="a1" space="ram"/>
<spacebase name="a8_" register="a8" space="ram"/>
<spacebase name="a9_" register="a9" space="ram"/>
<global>
<range space="ram"/>
<register name="a0"/>
<register name="a1"/>
<register name="a8"/>
<register name="a9"/>
</global>
<returnaddress>

8
Ghidra/Processors/tricore/data/languages/tricore.ldefs
View File

@@ -6,7 +6,7 @@
endian="little"
size="32"
variant="default"
version="1.6"
version="1.7"
slafile="tricore.sla"
processorspec="tricore.pspec"
manualindexfile="../manuals/tricore2.idx"
@@ -19,7 +19,7 @@
endian="little"
size="32"
variant="TC29x"
version="1.6"
version="1.7"
slafile="tricore.sla"
processorspec="tc29x.pspec"
manualindexfile="../manuals/tricore2.idx"
@@ -32,7 +32,7 @@
endian="little"
size="32"
variant="TC172x"
version="1.3"
version="1.7"
slafile="tricore.sla"
processorspec="tc172x.pspec"
manualindexfile="../manuals/tricore.idx"
@@ -45,7 +45,7 @@
endian="little"
size="32"
variant="TC176x"
version="1.3"
version="1.7"
slafile="tricore.sla"
processorspec="tc176x.pspec"
manualindexfile="../manuals/tricore.idx"

12
Ghidra/Processors/tricore/data/languages/tricore.sinc
View File

@@ -2893,6 +2893,10 @@ SC: [a10]const0815Z10zz is PCPMode=0 & a10 & const0815Z10zz & op0003=8 & op0404=
tmp[0,1] = 0;
goto [tmp];
}
:ji a11 is PCPMode=0 & op0811=11 & op0007=0xdc & op1215=0x0 & a11
{
return [a11];
}
@endif
@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)
@@ -2903,13 +2907,17 @@ SC: [a10]const0815Z10zz is PCPMode=0 & a10 & const0815Z10zz & op0003=8 & op0404=
tmp[0,1] = 0;
goto [tmp];
}
:ji a11 is PCPMode=0 & op0811=11 & op0007=0x2d & op1215=0x0 & a11; op1631=0x30
{
return [a11];
}
@endif
# JL disp24 (B)
:jl off24pc is PCPMode=0 & ( op0007=0x5d ) ... & off24pc
{
#TODO is this just a call w/o context switching?
a11 = inst_start + 4;
a11 = inst_next;
call off24pc;
}
@@ -2917,7 +2925,7 @@ SC: [a10]const0815Z10zz is PCPMode=0 & a10 & const0815Z10zz & op0003=8 & op0404=
:jla off24abs is PCPMode=0 & ( op0007=0xdd ) ... & off24abs
{
#TODO is this just a call w/o context switching?
a11 = inst_start + 4;
a11 = inst_next;
call off24abs;
}