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'origin/GP-3787_ghidorahrex_PowerPC_VLE_branch_CR_operand--SQUASHED'
into patch (Closes #5246)
This commit is contained in:
Ryan Kurtz
2024-01-19 14:49:50 -05:00
parent 45b0d98108 8371098d19
commit 4f4933843a
2 changed files with 17 additions and 6 deletions
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4
Ghidra/Processors/PowerPC/data/languages/ppc.ldefs
View File

@@ -210,7 +210,7 @@
endian="big"
size="32"
variant="PowerQUICC-III-e500mc"
version="1.5"
version="1.6"
slafile="ppc_32_be.sla"
processorspec="ppc_32.pspec"
manualindexfile="../manuals/PowerPC.idx"
@@ -225,7 +225,7 @@
endian="little"
size="32"
variant="PowerQUICC-III-e500mc"
version="1.5"
version="1.6"
slafile="ppc_32_le.sla"
processorspec="ppc_32.pspec"
manualindexfile="../manuals/PowerPC.idx"

19
Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc
View File

@@ -21,7 +21,7 @@ CC32: "dnz" is BO_VLE=2 {CTR = CTR-1; tmp:1 = (CTR != 0); export tmp; }
CC32: "dz" is BO_VLE=3 {CTR = CTR-1; tmp:1 = (CTR == 0); export tmp; }
addrBD8: reloc is BD8_VLE [ reloc = inst_start + (BD8_VLE << 1);] { export *[ram]:4 reloc; }
addrBD15: reloc is BD15_VLE [ reloc = inst_start + (BD15_VLE << 1);] { export *[ram]:4 reloc; }
addrBD15: reloc is BD15_VLE [ reloc = inst_start + (BD15_VLE << 1);] { export *[ram]:4 reloc; }
addrBD24: reloc is BD24_VLE [ reloc = inst_start + (BD24_VLE << 1);] { export *[ram]:4 reloc; }
d8PlusRaAddress: S8IMM(A) is S8IMM & A {tmp:$(REGISTER_SIZE) = A+S8IMM; export tmp; }
@@ -70,18 +70,29 @@ IMM16B: val is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
# NOTE: For the conditional branches, the "official" mnemonics have just bc and bcl.
# We use extended mnemonics so the display is understandable without having to cross-
# reference multiple tables.
:e_b^CC32 addrBD15 is $(ISVLE) & OP=30 & XOP_VLE=8 & LK=0 & addrBD15 & CC32 {
:e_b^CC32 BI_CR_VLE, addrBD15 is $(ISVLE) & OP=30 & XOP_VLE=8 & LK=0 & addrBD15 & BIT_L=0 & BI_CR_VLE & CC32 {
if (CC32 == 0) goto inst_next;
goto addrBD15;
}
:e_b^CC32^"l" addrBD15 is $(ISVLE) & OP=30 & XOP_VLE=8 & LK=1 & addrBD15 & CC32 {
:e_b^CC32^"l" BI_CR_VLE, addrBD15 is $(ISVLE) & OP=30 & XOP_VLE=8 & LK=1 & addrBD15 & BIT_L=0 & BI_CR_VLE & CC32 {
if (CC32 == 0) goto inst_next;
LR= inst_next;
call [addrBD15];
}
:se_b^CC16 addrBD8 is $(ISVLE) & OP5_VLE=28 & addrBD8 & CC16 {
:e_b^CC32 addrBD15 is $(ISVLE) & OP=30 & XOP_VLE=8 & LK=0 & addrBD15 & BIT_L=1 & CC32 {
if (CC32 == 0) goto inst_next;
goto addrBD15;
}
:e_b^CC32^"l" addrBD15 is $(ISVLE) & OP=30 & XOP_VLE=8 & LK=1 & addrBD15 & BIT_L=1 & CC32 {
if (CC32 == 0) goto inst_next;
LR= inst_next;
call [addrBD15];
}
:se_b^CC16 cr0, addrBD8 is $(ISVLE) & OP5_VLE=28 & addrBD8 & cr0 & CC16 {
if (CC16 == 0) goto inst_next;
goto addrBD8;
}