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Merge remote-tracking branch 'origin/patch'

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This commit is contained in:
Ryan Kurtz
2019-11-13 08:37:23 -05:00
parent 6bac1a8712 074e3ca869
commit 55dfda10ba
7 changed files with 34 additions and 35 deletions
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2
Ghidra/Processors/HCS12/data/languages/XGATE.sinc
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@@ -592,7 +592,7 @@ rd_hi: reg8 is reg8 & reg8_hi { export reg8_hi; }
# Load Immediate 8-bit constant (high byte)
:LDH rd, ximm8 is opcode=0x1f & rd & ximm8 & rd_hi
{
rd_hi = ximm8 << 8;
rd_hi = ximm8;
}

26
Ghidra/Processors/MCS96/data/languages/MCS96.cspec
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@@ -6,26 +6,26 @@
</global>
<stackpointer register="SP" space="RAM" growth="negative"/>
<returnaddress>
<varnode space="stack" offset="0" size="2"/>
<varnode space="stack" offset="0" size="2"/>
</returnaddress>
<default_proto>
<prototype name="__stdcall" extrapop="2" stackshift="2">
<input>
<pentry minsize="1" maxsize="500" align="2">
<addr offset="2" space="stack"/>
</pentry>
<pentry minsize="1" maxsize="500" align="2">
<addr offset="2" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="2">
<register name="RW1C"/>
</pentry>
<output>
<unaffected>
<register name="SP"/>
</unaffected>
<localrange>
<range space="stack" first="0xffff" last="0xf000" />
</localrange>
<register name="RW1C"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
</unaffected>
<localrange>
<range space="stack" first="0xffff" last="0xf000" />
</localrange>
</prototype>
</default_proto>
</compiler_spec>

2
Ghidra/Processors/MCS96/data/languages/MCS96.pspec
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@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="PC"/
<programcounter register="PC"/>
<default_symbols>
<symbol name="VECTOR_Reset" address="0x2080" entry="true"/>
</default_symbols>

1
Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc
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@@ -1002,7 +1002,6 @@ define token instr(32)
IMM_11_15_VLE=(11,14)
IMM_16_20_VLE=(16,20)
IMM_21_25_VLE=(21,25)
SIMM_0_10_VLE=(0,10) signed
SIMM_11_14_VLE=(11,14) signed
SIMM_21_25_VLE=(21,25) signed
SCL_VLE=(8,9)

2
Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc
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@@ -44,7 +44,7 @@ SCALE: val is BIT_10 & SCL_VLE & IMM8 [ val = (((0xFFFFFFFF << ((SCL_VLE*8)
SCALE: val is BIT_10 & SCL_VLE & IMM8 [ val = (((0xFFFFFFFFFFFFFFFF << ((SCL_VLE*8) + 8)) | (0x7FFFFFFFFFFFFFFF >> (63 - (SCL_VLE*8)))) * BIT_10) | (IMM8 << (SCL_VLE*8)); ] { export *[const]:8 val;}
@endif
SIMM16: val is SIMM_0_10_VLE & SIMM_21_25_VLE [ val = (SIMM_21_25_VLE << 11) | SIMM_0_10_VLE ;] { export *[const]:2 val; }
SIMM16: val is IMM_0_10_VLE & SIMM_21_25_VLE [ val = (SIMM_21_25_VLE << 11) | IMM_0_10_VLE ;] { export *[const]:2 val; }
SIMM20: val is IMM_0_10_VLE & IMM_16_20_VLE & SIMM_11_14_VLE [ val = (SIMM_11_14_VLE << 16 ) | (IMM_16_20_VLE << 11) | IMM_0_10_VLE ;] { export *[const]:2 val; }
IMM16: val is IMM_0_10_VLE & IMM_21_25_VLE [ val = (IMM_21_25_VLE << 11) | IMM_0_10_VLE ;] { export *[const]:2 val; }
IMM16B: val is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) | IMM_0_10_VLE ;] { export *[const]:2 val; }

26
Ghidra/Processors/x86/data/languages/ia.sinc
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@@ -4687,7 +4687,7 @@ define pcodeop fcos;
:FICOM spec_m16 is vexMode=0 & byte=0xDE; reg_opcode=2 ... & spec_m16 { local tmp = int2float(spec_m16); fcom(tmp); }
:FICOM spec_m32 is vexMode=0 & byte=0xDA; reg_opcode=2 ... & spec_m32 { local tmp = int2float(spec_m32); fcom(tmp); }
:FICOMP spec_m16 is vexMode=0 & byte=0xDE; reg_opcode=3 ... & spec_m16 { local tmp = int2float(spec_m16); fcom(tmp); fpop(); }
:FICOMP spec_m16 is vexMode=0 & byte=0xDE; (mod != 0b11 & reg_opcode=3) ... & spec_m16 { local tmp = int2float(spec_m16); fcom(tmp); fpop(); }
:FICOMP spec_m32 is vexMode=0 & byte=0xDA; reg_opcode=3 ... & spec_m32 { local tmp = int2float(spec_m32); fcom(tmp); fpop(); }
:FILD spec_m16 is vexMode=0 & byte=0xDF; reg_opcode=0 ... & spec_m16 { fdec(); ST0 = int2float(spec_m16); }
@@ -4709,8 +4709,8 @@ define pcodeop fcos;
:FNINIT is vexMode=0 & byte=0xDB; byte=0xE3 { }
:FIST spec_m16 is vexMode=0 & byte=0xDF; reg_opcode=2 ... & spec_m16 { tmp:10 = round(ST0); spec_m16 = trunc(tmp); }
:FIST spec_m32 is vexMode=0 & byte=0xDB; reg_opcode=2 ... & spec_m32 { tmp:10 = round(ST0); spec_m32 = trunc(tmp); }
:FIST spec_m16 is vexMode=0 & byte=0xDF; (mod != 0b11 & reg_opcode=2) ... & spec_m16 { tmp:10 = round(ST0); spec_m16 = trunc(tmp); }
:FIST spec_m32 is vexMode=0 & byte=0xDB; (mod != 0b11 & reg_opcode=2) ... & spec_m32 { tmp:10 = round(ST0); spec_m32 = trunc(tmp); }
:FISTP spec_m16 is vexMode=0 & byte=0xDF; reg_opcode=3 ... & spec_m16 { tmp:10 = round(ST0); fpop(); spec_m16 = trunc(tmp); }
:FISTP spec_m32 is vexMode=0 & byte=0xDB; reg_opcode=3 ... & spec_m32 { tmp:10 = round(ST0); fpop(); spec_m32 = trunc(tmp); }
:FISTP spec_m64 is vexMode=0 & byte=0xDF; reg_opcode=7 ... & spec_m64 { tmp:10 = round(ST0); fpop(); spec_m64 = trunc(tmp); }
@@ -4719,7 +4719,7 @@ define pcodeop fcos;
:FISTTP spec_m32 is vexMode=0 & byte=0xDB; reg_opcode=1 ... & spec_m32 { spec_m32 = trunc(ST0); fpop(); }
:FISTTP spec_m64 is vexMode=0 & byte=0xDD; reg_opcode=1 ... & spec_m64 { spec_m64 = trunc(ST0); fpop(); }
:FLD spec_m32 is vexMode=0 & byte=0xD9; reg_opcode=0 ... & spec_m32 { fdec(); ST0 = float2float(spec_m32); }
:FLD spec_m32 is vexMode=0 & byte=0xD9; (mod != 0b11 & reg_opcode=0) ... & spec_m32 { fdec(); ST0 = float2float(spec_m32); }
:FLD spec_m64 is vexMode=0 & byte=0xDD; reg_opcode=0 ... & spec_m64 { fdec(); ST0 = float2float(spec_m64);}
:FLD spec_m80 is vexMode=0 & byte=0xDB; reg_opcode=5 ... & spec_m80 { fpushv(spec_m80); }
@@ -4734,10 +4734,10 @@ define pcodeop fcos;
:FLDLN2 is vexMode=0 & byte=0xD9; byte=0xED { src:8 = 0x3fe62e42fefa39ef; tmp:10 = float2float(src); fpushv(tmp); }
:FLDZ is vexMode=0 & byte=0xD9; byte=0xEE { zero:4 = 0; tmp:10 = int2float(zero); fpushv(tmp); }
:FLDCW m16 is vexMode=0 & byte=0xD9; reg_opcode=5 ... & m16 { FPUControlWord = m16; }
:FLDCW m16 is vexMode=0 & byte=0xD9; (mod != 0b11 & reg_opcode=5) ... & m16 { FPUControlWord = m16; }
define pcodeop fldenv;
:FLDENV Mem is vexMode=0 & byte=0xD9; reg_opcode=4 ... & Mem
:FLDENV Mem is vexMode=0 & byte=0xD9; (mod != 0b11 & reg_opcode=4) ... & Mem
{
FPUControlWord = *:2 (Mem);
FPUStatusWord = *:2 (Mem + 4);
@@ -4849,18 +4849,18 @@ define pcodeop fsin;
:FSINCOS is vexMode=0 & byte=0xD9; byte=0xFB { tmp:10 = fcos(ST0); ST0 = fsin(ST0); fpushv(tmp); }
:FSQRT is vexMode=0 & byte=0xD9; byte=0xFA { ST0 = sqrt(ST0); }
:FST spec_m32 is vexMode=0 & byte=0xD9; reg_opcode=2 ... & spec_m32 { spec_m32 = float2float(ST0); }
:FST spec_m32 is vexMode=0 & byte=0xD9; (mod != 0b11 & reg_opcode=2) ... & spec_m32 { spec_m32 = float2float(ST0); }
:FST spec_m64 is vexMode=0 & byte=0xDD; reg_opcode=2 ... & spec_m64 { spec_m64 = float2float(ST0); }
:FST freg is vexMode=0 & byte=0xDD; frow=13 & fpage=0 & freg { ST0 = freg; }
:FSTP spec_m32 is vexMode=0 & byte=0xD9; reg_opcode=3 ... & spec_m32 { spec_m32 = float2float(ST0); fpop(); }
:FSTP spec_m32 is vexMode=0 & byte=0xD9; (mod != 0b11 & reg_opcode=3) ... & spec_m32 { spec_m32 = float2float(ST0); fpop(); }
:FSTP spec_m64 is vexMode=0 & byte=0xDD; reg_opcode=3 ... & spec_m64 { spec_m64 = float2float(ST0); fpop(); }
:FSTP spec_m80 is vexMode=0 & byte=0xDB; reg_opcode=7 ... & spec_m80 { fpopv(spec_m80); }
:FSTP freg is vexMode=0 & byte=0xDD; frow=13 & fpage=1 & freg { fpopv(freg); }
:FSTCW m16 is vexMode=0 & byte=0x9B; byte=0xD9; reg_opcode=7 ... & m16 { m16 = FPUControlWord; }
:FNSTCW m16 is vexMode=0 & byte=0xD9; reg_opcode=7 ... & m16 { m16 = FPUControlWord; }
:FSTCW m16 is vexMode=0 & byte=0x9B; byte=0xD9; (mod != 0b11 & reg_opcode=7) ... & m16 { m16 = FPUControlWord; }
:FNSTCW m16 is vexMode=0 & byte=0xD9; (mod != 0b11 & reg_opcode=7) ... & m16 { m16 = FPUControlWord; }
:FSTENV Mem is vexMode=0 & byte=0x9B; byte=0xD9; reg_opcode=6 ... & Mem
:FSTENV Mem is vexMode=0 & byte=0x9B; byte=0xD9; (mod != 0b11 & reg_opcode=6) ... & Mem
{
*:2 (Mem) = FPUControlWord;
*:2 (Mem + 4) = FPUStatusWord;
@@ -4870,7 +4870,7 @@ define pcodeop fsin;
*:2 (Mem + 18) = FPULastInstructionOpcode;
}
:FNSTENV Mem is vexMode=0 & byte=0xD9; reg_opcode=6 ... & Mem
:FNSTENV Mem is vexMode=0 & byte=0xD9; (mod != 0b11 & reg_opcode=6) ... & Mem
{
*:2 (Mem) = FPUControlWord;
*:2 (Mem + 4) = FPUStatusWord;
@@ -4891,7 +4891,7 @@ define pcodeop fsin;
:FSUB freg,ST0 is vexMode=0 & byte=0xDC; frow=14 & fpage=1 & freg & ST0 { freg = freg f- ST0; }
:FSUBP is vexMode=0 & byte=0xDE; byte=0xE9 { ST1 = ST1 f- ST0; fpop(); }
:FSUBP freg,ST0 is vexMode=0 & byte=0xDE; frow=14 & fpage=1 & freg & ST0 { freg = freg f- ST0; fpop(); }
:FISUB spec_m32 is vexMode=0 & byte=0xDA; reg_opcode=4 ... & spec_m32 { ST0 = ST0 f- int2float(spec_m32); }
:FISUB spec_m32 is vexMode=0 & byte=0xDA; (mod != 0b11 & reg_opcode=4) ... & spec_m32 { ST0 = ST0 f- int2float(spec_m32); }
:FISUB spec_m16 is vexMode=0 & byte=0xDE; reg_opcode=4 ... & spec_m16 { ST0 = ST0 f- int2float(spec_m16); }
:FSUBR spec_m32 is vexMode=0 & byte=0xD8; reg_opcode=5 ... & spec_m32 { ST0 = float2float(spec_m32) f- ST0; }

10
Ghidra/Processors/x86/data/languages/x86.ldefs
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@@ -5,7 +5,7 @@
endian="little"
size="32"
variant="default"
version="2.8"
version="2.9"
slafile="x86.sla"
processorspec="x86.pspec"
manualindexfile="../manuals/x86.idx"
@@ -32,7 +32,7 @@
endian="little"
size="32"
variant="System Management Mode"
version="2.8"
version="2.9"
slafile="x86.sla"
processorspec="x86-16.pspec"
manualindexfile="../manuals/x86.idx"
@@ -45,7 +45,7 @@
endian="little"
size="16"
variant="Real Mode"
version="2.8"
version="2.9"
slafile="x86.sla"
processorspec="x86-16-real.pspec"
manualindexfile="../manuals/x86.idx"
@@ -63,7 +63,7 @@
endian="little"
size="16"
variant="Protected Mode"
version="2.8"
version="2.9"
slafile="x86.sla"
processorspec="x86-16.pspec"
manualindexfile="../manuals/x86.idx"
@@ -76,7 +76,7 @@
endian="little"
size="64"
variant="default"
version="2.8"
version="2.9"
slafile="x86-64.sla"
processorspec="x86-64.pspec"
manualindexfile="../manuals/x86.idx"