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Merge remote-tracking branch 'origin/patch'

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Ryan Kurtz
2026-07-21 13:04:25 -04:00
parent 95456a8e64 052eaddf41
commit 73cf8100b9
4 changed files with 5 additions and 9 deletions
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2
Ghidra/Features/Base/src/main/java/ghidra/app/util/bin/format/pe/ExportDataDirectory.java
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@@ -314,7 +314,7 @@ public class ExportDataDirectory extends DataDirectory implements StructConverte
// See if this function has an associated name exported for it. // See if this function has an associated name exported for it.
for (int j = 0; j < numberOfNames; ++j) { for (int j = 0; j < numberOfNames; ++j) {
int jthOrdinalVal = reader.readShort(pointerToOrdinals + (j * 2)); int jthOrdinalVal = reader.readUnsignedShort(pointerToOrdinals + (j * 2));
if (jthOrdinalVal == i) { if (jthOrdinalVal == i) {
int jthNameRVA = reader.readInt(pointerToNames + (j * 4)); int jthNameRVA = reader.readInt(pointerToNames + (j * 4));
int jthNamePtr = ntHeader.rvaToPointer(jthNameRVA); int jthNamePtr = ntHeader.rvaToPointer(jthNameRVA);

6
Ghidra/Processors/MCS96/data/languages/MCS96.sinc
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@@ -617,11 +617,7 @@ macro setSignedShiftRightCarryFlag(shiftee,amount) {
:CMPL dlreg, lreg is op8=0xc5; lreg; dlreg { :CMPL dlreg, lreg is op8=0xc5; lreg; dlreg {
op1:4 = lreg; op1:4 = lreg;
tmp:4 = dlreg - op1; tmp:4 = dlreg - op1;
$(N) = (tmp s< 0); subtractFlags(dlreg, op1, tmp);
$(Z) = (tmp == 0);
$(C) = scarry(dlreg, op1);
$(V) = (((dlreg & ~op1 & ~tmp) | (~dlreg & op1 & tmp)) & 0x80000000 ) != 0;
$(VT) = $(VT) | $(V);
} }
@endif @endif

4
Ghidra/Processors/x86/data/languages/avx.sinc
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@@ -1871,14 +1871,14 @@ define pcodeop vpextrq_avx ;
# PEXTRW 4-277 PAGE 1397 LINE 72478 # PEXTRW 4-277 PAGE 1397 LINE 72478
define pcodeop vpextrw_avx ; define pcodeop vpextrw_avx ;
:VPEXTRW Reg32, XmmReg2, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0xC5; Reg32 & (mod=0x3 & XmmReg2); imm8 :VPEXTRW Reg32, XmmReg2, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xC5; Reg32 & (mod=0x3 & XmmReg2); imm8
{ {
Reg32 = vpextrw_avx( XmmReg2, imm8:1 ); Reg32 = vpextrw_avx( XmmReg2, imm8:1 );
# TODO Reg64 = zext(Reg32) # TODO Reg64 = zext(Reg32)
} }
# PEXTRW 4-277 PAGE 1397 LINE 72483 # PEXTRW 4-277 PAGE 1397 LINE 72483
:VPEXTRW Reg32_m16, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x15; XmmReg1 ... & Reg32_m16; imm8 :VPEXTRW Reg32_m16, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x15; XmmReg1 ... & Reg32_m16; imm8
{ {
Reg32_m16 = vpextrw_avx( XmmReg1, imm8:1 ); Reg32_m16 = vpextrw_avx( XmmReg1, imm8:1 );
# TODO Reg64 = zext(Reg32) # TODO Reg64 = zext(Reg32)

2
Ghidra/Processors/x86/data/languages/ia.sinc
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@@ -4215,7 +4215,7 @@ define pcodeop swap_bytes;
:NEG Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf7; mod=3 & Rmr64 & reg_opcode=3 { negflags(Rmr64); Rmr64 = -Rmr64; resultflags(Rmr64); } :NEG Rmr64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xf7; mod=3 & Rmr64 & reg_opcode=3 { negflags(Rmr64); Rmr64 = -Rmr64; resultflags(Rmr64); }
@endif @endif
:NOP is vexMode=0 & byte=0x90 & (mandover=0 | mandover=4 | mandover=1) & (rexprefix=0 | rexWRXBprefix=8) { } :NOP is vexMode=0 & byte=0x90 & (mandover=0 | mandover=4 | mandover=1) & (rexprefix=0 | rexWRXBprefix=8 | rexWRXBprefix=0) { }
:NOP rm16 is vexMode=0 & mandover & opsize=0 & byte=0x0f; high5=3; rm16 ... { } :NOP rm16 is vexMode=0 & mandover & opsize=0 & byte=0x0f; high5=3; rm16 ... { }
:NOP rm32 is vexMode=0 & mandover & opsize=1 & byte=0x0f; high5=3; rm32 ... { } :NOP rm32 is vexMode=0 & mandover & opsize=1 & byte=0x0f; high5=3; rm32 ... { }
:NOP^"/reserved" rm16 is vexMode=0 & mandover & opsize=0 & byte=0x0f; byte=0x18; rm16 & reg_opcode_hb=1 ... { } :NOP^"/reserved" rm16 is vexMode=0 & mandover & opsize=0 & byte=0x0f; byte=0x18; rm16 & reg_opcode_hb=1 ... { }