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se_cmpli fix

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Previous attempt at se_cmpli fix incorrectly applied a 5 bit mask
OIMM = UI5_VLE + 1, resulting in values 1-32
This commit is contained in:
mumbel
2019-09-12 17:30:40 -05:00
parent 2f3eeed8ca
commit 9d03c3a5f7
1 changed files with 1 additions and 1 deletions
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2
Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc
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@@ -591,7 +591,7 @@ IMM16B: val is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
:se_cmpli RX_VLE,OIMM is $(ISVLE) & OP6_VLE=8 & BIT9_VLE=1 & RX_VLE & OIMM {
tmpA:4 = RX_VLE:4;
tmpB:4 = OIMM:4 & 0x1f;
tmpB:4 = OIMM:4;
cr0 = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);
}