mirror/ghidra
1
0
Fork 0
mirror of https://github.com/NationalSecurityAgency/ghidra.git synced 2026-09-25 17:00:36 -09:00
Code Issues Packages Projects Releases Wiki Activity

Opinion fix

Browse Source 
Does not handle all the cases it can, add in size IMAFC and
generic cases for GC.
This commit is contained in:
mumbel
2020-10-28 21:46:09 -05:00
committed by ghidra1
parent c9ae8bdd8d
commit a487f77918
1 changed files with 12 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
Ghidra/Processors/RISCV/data/languages/riscv.opinion
View File

@@ -11,15 +11,18 @@
<!-- EF_RISCV_ABI_QUAD 0x0006 -->
<!-- EF_RISCV_RVE 0x0008 -->
<!-- EF_RISCV_TSO 0x0010 -->
<constraint primary="243" secondary="0" processor="RISCV" endian="little" variant="RV32I"/>
<constraint primary="243" secondary="0" processor="RISCV" endian="little" variant="RV64I"/>
<constraint primary="243" secondary="1" processor="RISCV" endian="little" variant="RV32IMC"/>
<constraint primary="243" secondary="1" processor="RISCV" endian="little" variant="RV64IC"/>
<constraint primary="243" secondary="2" processor="RISCV" endian="little" variant="RV32IF"/>
<constraint primary="243" secondary="4" processor="RISCV" endian="little" variant="RV32G"/>
<constraint primary="243" secondary="4" processor="RISCV" endian="little" variant="RV64G"/>
<constraint primary="243" secondary="5" processor="RISCV" endian="little" variant="RV32GC"/>
<constraint primary="243" secondary="5" processor="RISCV" endian="little" variant="RV64GC"/>
<constraint primary="243" secondary="0" processor="RISCV" endian="little" size="32" variant="RV32I"/>
<constraint primary="243" secondary="0" processor="RISCV" endian="little" size="64" variant="RV64I"/>
<constraint primary="243" secondary="1" processor="RISCV" endian="little" size="32" variant="RV32IMC"/>
<constraint primary="243" secondary="1" processor="RISCV" endian="little" size="64" variant="RV64IC"/>
<constraint primary="243" secondary="2" processor="RISCV" endian="little" size="32" variant="RV32IF"/>
<constraint primary="243" secondary="3" processor="RISCV" endian="little" size="32" variant="RV32GC"/> <!-- RV32IMAFC -->
<constraint primary="243" secondary="4" processor="RISCV" endian="little" size="32" variant="RV32G"/>
<constraint primary="243" secondary="4" processor="RISCV" endian="little" size="64" variant="RV64G"/>
<constraint primary="243" secondary="5" processor="RISCV" endian="little" size="32" variant="RV32GC"/>
<constraint primary="243" secondary="5" processor="RISCV" endian="little" size="64" variant="RV64GC"/>
<constraint primary="243" processor="RISCV" endian="little" size="32" variant="RV32GC"/>
<constraint primary="243" processor="RISCV" endian="little" size="64" variant="RV64GC"/>
</constraint>
</constraint>
</opinions>