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PowerPC VLE: Fix se_blrl flow

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Opcode se_blrl is branch link register and link. Treating it as a return break flow and is wrong. Non VLE is already correct.
This commit is contained in:
Goatman13
2024-02-08 10:19:47 +01:00
committed by ghidorahrex
parent 0d6588d68b
commit c0bc9a882b
1 changed files with 1 additions and 1 deletions
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Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc
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@@ -114,7 +114,7 @@ IMM16B: val is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
:se_blrl is $(ISVLE) & OP15_VLE=2 & LK0_VLE=1 {
tmp:$(REGISTER_SIZE) = LR & ~1;
LR = inst_next;
return [tmp];
call [tmp];
}
:se_sc is $(ISVLE) & OP16_VLE=2 {