mirror/ghidra
1
0
Fork 0
mirror of https://github.com/NationalSecurityAgency/ghidra.git synced 2026-09-28 17:11:11 -09:00
Code Issues Packages Projects Releases Wiki Activity

Merge remote-tracking branch 'origin/Ghidra_11.1'

Browse Source
This commit is contained in:
Ryan Kurtz
2024-06-04 13:00:32 -04:00
parent 127f5679d1 c5e0bfed77
commit c19facf226
12 changed files with 1298 additions and 1316 deletions
Download Patch File Download Diff File Expand all files Collapse all files

BIN
Ghidra/Features/Base/data/typeinfo/generic/generic_clib.gdt
View File

Binary file not shown.

BIN
Ghidra/Features/Base/data/typeinfo/generic/generic_clib_64.gdt
View File

Binary file not shown.

BIN
Ghidra/Features/Base/data/typeinfo/golang/golang_1.21_anybit_any.gdt
View File

Binary file not shown.

BIN
Ghidra/Features/Base/data/typeinfo/golang/golang_1.22_anybit_any.gdt
View File

Binary file not shown.

BIN
Ghidra/Features/Base/data/typeinfo/rust/rust-common.gdt
View File

Binary file not shown.

BIN
Ghidra/Features/Base/data/typeinfo/win32/windows_vs12_32.gdt
View File

Binary file not shown.

BIN
Ghidra/Features/Base/data/typeinfo/win32/windows_vs12_64.gdt
View File

Binary file not shown.

29
Ghidra/Features/Base/src/main/java/ghidra/app/util/bin/format/golang/rtti/GoRttiMapper.java
View File

@@ -22,8 +22,6 @@ import java.io.IOException;
import java.util.*;
import java.util.Map.Entry;
import javax.help.UnsupportedOperationException;
import generic.jar.ResourceFile;
import ghidra.app.plugin.core.analysis.AutoAnalysisManager;
import ghidra.app.plugin.core.analysis.TransientProgramProperties;
@@ -37,13 +35,13 @@ import ghidra.app.util.bin.format.golang.structmapping.*;
import ghidra.app.util.importer.MessageLog;
import ghidra.app.util.opinion.*;
import ghidra.framework.Platform;
import ghidra.framework.store.LockException;
import ghidra.program.model.address.*;
import ghidra.program.model.data.*;
import ghidra.program.model.data.DataTypeConflictHandler.ConflictResult;
import ghidra.program.model.data.StandAloneDataTypeManager.LanguageUpdateOption;
import ghidra.program.model.lang.*;
import ghidra.program.model.listing.*;
import ghidra.program.model.lang.Endian;
import ghidra.program.model.lang.LanguageID;
import ghidra.program.model.listing.Function;
import ghidra.program.model.listing.Program;
import ghidra.program.model.mem.MemoryBlock;
import ghidra.program.model.symbol.Symbol;
import ghidra.program.model.symbol.SymbolType;
@@ -843,8 +841,7 @@ public class GoRttiMapper extends DataTypeMapper implements DataTypeMapperContex
// to avoid traces of the original program name as a deleted source archive link in the
// gdt data base. This method only leaves the target gdt filename + ".step1" in the db.
File tmpGDTFile = new File(gdtFile.getParentFile(), gdtFile.getName() + ".step1.gdt");
FileDataTypeManager tmpFdtm = createFileArchive(tmpGDTFile, program.getLanguage(),
program.getCompilerSpec().getCompilerSpecID(), monitor);
FileDataTypeManager tmpFdtm = FileDataTypeManager.createFileArchive(tmpGDTFile);
int tx = -1;
try {
tx = tmpFdtm.startTransaction("Import");
@@ -889,8 +886,7 @@ public class GoRttiMapper extends DataTypeMapper implements DataTypeMapperContex
tmpFdtm.save();
FileDataTypeManager fdtm = createFileArchive(gdtFile, program.getLanguage(),
program.getCompilerSpec().getCompilerSpecID(), monitor);
FileDataTypeManager fdtm = FileDataTypeManager.createFileArchive(gdtFile);
tx = -1;
try {
tx = fdtm.startTransaction("Import");
@@ -915,19 +911,6 @@ public class GoRttiMapper extends DataTypeMapper implements DataTypeMapperContex
tmpGDTFile.delete();
}
private FileDataTypeManager createFileArchive(File gdtFile, Language lang,
CompilerSpecID compilerId, TaskMonitor monitor) throws IOException {
try {
FileDataTypeManager fdtm = FileDataTypeManager.createFileArchive(gdtFile);
fdtm.setProgramArchitecture(lang, compilerId, LanguageUpdateOption.CLEAR, monitor);
return fdtm;
}
catch (IOException | CancelledException | LockException | UnsupportedOperationException
| IncompatibleLanguageException e) {
throw new IOException("Failed to create file data type manager: " + gdtFile, e);
}
}
private DataType structMappingInfoToDataType(StructureMappingInfo<?> smi) {
if (smi.getStructureDataType() == null) {
return null;

2
Ghidra/Features/Base/src/test.slow/java/ghidra/app/plugin/core/datamgr/DataTypeArchiveIDTest.java
View File

@@ -67,7 +67,7 @@ public class DataTypeArchiveIDTest extends AbstractGenericTest {
FileDataTypeManager dtm = null;
try {
dtm = FileDataTypeManager.openFileArchive(gdtFile, false);
assertEquals(ArchiveWarning.NONE, dtm.getWarning());
assertEquals(dtm.getWarningMessage(true), ArchiveWarning.NONE, dtm.getWarning());
return dtm.getUniversalID().toString();
}
catch (IOException e) {

2290
Ghidra/Processors/x86/data/languages/avx512.sinc
View File

File diff suppressed because it is too large Load Diff

228
Ghidra/Processors/x86/data/languages/avx512_manual.sinc
View File

@@ -110,27 +110,27 @@ define pcodeop kmovd_avx512bw ;
# VCVTPS2PH 5-37 PAGE 1861 LINE 96116
define pcodeop vcvtps2ph_avx512vl ;
:VCVTPS2PH XmmReg2 KWriteMask, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2; imm8
:VCVTPS2PH XmmReg2^KWriteMask, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2; imm8
{
XmmReg2 = vcvtps2ph_avx512vl( XmmReg1, imm8:1 );
ZmmReg2 = zext(XmmReg2);
}
:VCVTPS2PH m64 KWriteMask, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; XmmReg1 ... & m64; imm8
:VCVTPS2PH m64^KWriteMask, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; XmmReg1 ... & m64; imm8
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m64 = vcvtps2ph_avx512vl( XmmReg1, imm8:1 );
}
# VCVTPS2PH 5-37 PAGE 1861 LINE 96119
:VCVTPS2PH XmmReg2 KWriteMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2; imm8
:VCVTPS2PH XmmReg2^KWriteMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2; imm8
{
XmmReg2 = vcvtps2ph_avx512vl( YmmReg1, imm8:1 );
ZmmReg2 = zext(XmmReg2);
}
# VCVTPS2PH 5-37 PAGE 1861 LINE 96119
:VCVTPS2PH m128 KWriteMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; YmmReg1 ... & m128; imm8
:VCVTPS2PH m128^KWriteMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; YmmReg1 ... & m128; imm8
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m128 = vcvtps2ph_avx512vl( YmmReg1, imm8:1 );
@@ -138,13 +138,13 @@ define pcodeop vcvtps2ph_avx512vl ;
# VCVTPS2PH 5-37 PAGE 1861 LINE 96122
define pcodeop vcvtps2ph_avx512f ;
:VCVTPS2PH YmmReg2 KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2; imm8
:VCVTPS2PH YmmReg2^KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2; imm8
{
YmmReg2 = vcvtps2ph_avx512f( ZmmReg1, imm8:1 );
ZmmReg2 = zext(YmmReg2);
}
:VCVTPS2PH m256 KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; ZmmReg1 ... & m256; imm8
:VCVTPS2PH m256^KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; ZmmReg1 ... & m256; imm8
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m256 = vcvtps2ph_avx512f( ZmmReg1, imm8:1 );
@@ -152,13 +152,13 @@ define pcodeop vcvtps2ph_avx512f ;
# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115319
define pcodeop vpmovdb_avx512vl ;
:VPMOVDB XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVDB XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovdb_avx512vl( XmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVDB m32 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; XmmReg1 ... & m32
:VPMOVDB m32^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; XmmReg1 ... & m32
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
m32 = vpmovdb_avx512vl( XmmReg1 );
@@ -166,65 +166,65 @@ define pcodeop vpmovdb_avx512vl ;
# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115322
define pcodeop vpmovsdb_avx512vl ;
:VPMOVSDB XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSDB XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovsdb_avx512vl( XmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVSDB m32 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; XmmReg1 ... & m32
:VPMOVSDB m32^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; XmmReg1 ... & m32
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
m32 = vpmovsdb_avx512vl( XmmReg1 );
}
# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115326
define pcodeop vpmovusdb_avx512vl ;
:VPMOVUSDB XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSDB XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovusdb_avx512vl( XmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVUSDB m32 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; XmmReg1 ... & m32
:VPMOVUSDB m32^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; XmmReg1 ... & m32
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
m32 = vpmovusdb_avx512vl( XmmReg1 );
}
# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115330
:VPMOVDB XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVDB XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovdb_avx512vl( YmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVDB m64 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; YmmReg1 ... & m64
:VPMOVDB m64^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; YmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
m64 = vpmovdb_avx512vl( YmmReg1 );
}
# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115333
:VPMOVSDB XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSDB XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovsdb_avx512vl( YmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVSDB m64 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; YmmReg1 ... & m64
:VPMOVSDB m64^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; YmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
m64 = vpmovsdb_avx512vl( YmmReg1 );
}
# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115337
:VPMOVUSDB XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSDB XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovusdb_avx512vl( YmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVUSDB m64 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; YmmReg1 ... & m64
:VPMOVUSDB m64^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; YmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
m64 = vpmovusdb_avx512vl( YmmReg1 );
@@ -232,13 +232,13 @@ define pcodeop vpmovusdb_avx512vl ;
# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115341
define pcodeop vpmovdb_avx512f ;
:VPMOVDB XmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
:VPMOVDB XmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovdb_avx512f( ZmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVDB m128 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; ZmmReg1 ... & m128
:VPMOVDB m128^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; ZmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
m128 = vpmovdb_avx512f( ZmmReg1 );
@@ -246,13 +246,13 @@ define pcodeop vpmovdb_avx512f ;
# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115344
define pcodeop vpmovsdb_avx512f ;
:VPMOVSDB XmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSDB XmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovsdb_avx512f( ZmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVSDB m128 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; ZmmReg1 ... & m128
:VPMOVSDB m128^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; ZmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
m128 = vpmovsdb_avx512f( ZmmReg1 );
@@ -260,13 +260,13 @@ define pcodeop vpmovsdb_avx512f ;
# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115348
define pcodeop vpmovusdb_avx512f ;
:VPMOVUSDB XmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSDB XmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovusdb_avx512f( ZmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVUSDB m128 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; ZmmReg1 ... & m128
:VPMOVUSDB m128^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; ZmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
m128 = vpmovusdb_avx512f( ZmmReg1 );
@@ -274,13 +274,13 @@ define pcodeop vpmovusdb_avx512f ;
# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115532
define pcodeop vpmovdw_avx512vl ;
:VPMOVDW XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVDW XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovdw_avx512vl( XmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVDW m64 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; XmmReg1 ... & m64
:VPMOVDW m64^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; XmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m64 = vpmovdw_avx512vl( XmmReg1 );
@@ -288,13 +288,13 @@ define pcodeop vpmovdw_avx512vl ;
# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115535
define pcodeop vpmovsdw_avx512vl ;
:VPMOVSDW XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSDW XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovsdw_avx512vl( XmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVSDW m64 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; XmmReg1 ... & m64
:VPMOVSDW m64^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; XmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m64 = vpmovsdw_avx512vl( XmmReg1 );
@@ -302,52 +302,52 @@ define pcodeop vpmovsdw_avx512vl ;
# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115539
define pcodeop vpmovusdw_avx512vl ;
:VPMOVUSDW XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSDW XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovusdw_avx512vl( XmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVUSDW m64 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; XmmReg1 ... & m64
:VPMOVUSDW m64^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; XmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m64 = vpmovusdw_avx512vl( XmmReg1 );
}
# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115543
:VPMOVDW XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVDW XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovdw_avx512vl( YmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVDW m128 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; YmmReg1 ... & m128
:VPMOVDW m128^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; YmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m128 = vpmovdw_avx512vl( YmmReg1 );
}
# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115546
:VPMOVSDW XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSDW XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovsdw_avx512vl( YmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVSDW m128 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; YmmReg1 ... & m128
:VPMOVSDW m128^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; YmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m128 = vpmovsdw_avx512vl( YmmReg1 );
}
# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115550
:VPMOVUSDW XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSDW XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovusdw_avx512vl( YmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVUSDW m128 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; YmmReg1 ... & m128
:VPMOVUSDW m128^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; YmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m128 = vpmovusdw_avx512vl( YmmReg1 );
@@ -355,13 +355,13 @@ define pcodeop vpmovusdw_avx512vl ;
# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115554
define pcodeop vpmovdw_avx512f ;
:VPMOVDW YmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
:VPMOVDW YmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
{
YmmReg2 = vpmovdw_avx512f( ZmmReg1 );
ZmmReg2 = zext(YmmReg2);
}
:VPMOVDW m256 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; ZmmReg1 ... & m256
:VPMOVDW m256^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; ZmmReg1 ... & m256
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m256 = vpmovdw_avx512f( ZmmReg1 );
@@ -369,13 +369,13 @@ define pcodeop vpmovdw_avx512f ;
# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115557
define pcodeop vpmovsdw_avx512f ;
:VPMOVSDW YmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
:VPMOVSDW YmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
{
YmmReg2 = vpmovsdw_avx512f( ZmmReg1 );
ZmmReg2 = zext(YmmReg2);
}
:VPMOVSDW m256 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; ZmmReg1 ... & m256
:VPMOVSDW m256^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; ZmmReg1 ... & m256
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m256 = vpmovsdw_avx512f( ZmmReg1 );
@@ -383,13 +383,13 @@ define pcodeop vpmovsdw_avx512f ;
# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115561
define pcodeop vpmovusdw_avx512f ;
:VPMOVUSDW YmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
:VPMOVUSDW YmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
{
YmmReg2 = vpmovusdw_avx512f( ZmmReg1 );
ZmmReg2 = zext(YmmReg2);
}
:VPMOVUSDW m256 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; ZmmReg1 ... & m256
:VPMOVUSDW m256^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; ZmmReg1 ... & m256
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m256 = vpmovusdw_avx512f( ZmmReg1 );
@@ -397,13 +397,13 @@ define pcodeop vpmovusdw_avx512f ;
# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114671
define pcodeop vpmovqb_avx512vl ;
:VPMOVQB XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVQB XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovqb_avx512vl( XmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVQB m16 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; XmmReg1 ... & m16
:VPMOVQB m16^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; XmmReg1 ... & m16
[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)
{
m16 = vpmovqb_avx512vl( XmmReg1 );
@@ -411,13 +411,13 @@ define pcodeop vpmovqb_avx512vl ;
# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114674
define pcodeop vpmovsqb_avx512vl ;
:VPMOVSQB XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSQB XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovsqb_avx512vl( XmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVSQB m16 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; XmmReg1 ... & m16
:VPMOVSQB m16^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; XmmReg1 ... & m16
[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)
{
m16 = vpmovsqb_avx512vl( XmmReg1 );
@@ -425,52 +425,52 @@ define pcodeop vpmovsqb_avx512vl ;
# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114678
define pcodeop vpmovusqb_avx512vl ;
:VPMOVUSQB XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSQB XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovusqb_avx512vl( XmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVUSQB m16 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; XmmReg1 ... & m16
:VPMOVUSQB m16^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; XmmReg1 ... & m16
[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)
{
m16 = vpmovusqb_avx512vl( XmmReg1 );
}
# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114682
:VPMOVQB XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVQB XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovqb_avx512vl( YmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVQB m32 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; YmmReg1 ... & m32
:VPMOVQB m32^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; YmmReg1 ... & m32
[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)
{
m32 = vpmovqb_avx512vl( YmmReg1 );
}
# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114685
:VPMOVSQB XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSQB XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovsqb_avx512vl( YmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVSQB m32 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; YmmReg1 ... & m32
:VPMOVSQB m32^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; YmmReg1 ... & m32
[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)
{
m32 = vpmovsqb_avx512vl( YmmReg1 );
}
# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114689
:VPMOVUSQB XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSQB XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovusqb_avx512vl( YmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVUSQB m32 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; YmmReg1 ... & m32
:VPMOVUSQB m32^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; YmmReg1 ... & m32
[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)
{
m32 = vpmovusqb_avx512vl( YmmReg1 );
@@ -478,13 +478,13 @@ define pcodeop vpmovusqb_avx512vl ;
# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114693
define pcodeop vpmovqb_avx512f ;
:VPMOVQB XmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
:VPMOVQB XmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovqb_avx512f( ZmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVQB m64 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; ZmmReg1 ... & m64
:VPMOVQB m64^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; ZmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)
{
m64 = vpmovqb_avx512f( ZmmReg1 );
@@ -492,13 +492,13 @@ define pcodeop vpmovqb_avx512f ;
# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114696
define pcodeop vpmovsqb_avx512f ;
:VPMOVSQB XmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSQB XmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovsqb_avx512f( ZmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVSQB m64 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; ZmmReg1 ... & m64
:VPMOVSQB m64^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; ZmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)
{
m64 = vpmovsqb_avx512f( ZmmReg1 );
@@ -506,13 +506,13 @@ define pcodeop vpmovsqb_avx512f ;
# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114700
define pcodeop vpmovusqb_avx512f ;
:VPMOVUSQB XmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSQB XmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovusqb_avx512f( ZmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVUSQB m64 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; ZmmReg1 ... & m64
:VPMOVUSQB m64^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; ZmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)
{
m64 = vpmovusqb_avx512f( ZmmReg1 );
@@ -520,13 +520,13 @@ define pcodeop vpmovusqb_avx512f ;
# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114887
define pcodeop vpmovqw_avx512vl ;
:VPMOVQW XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVQW XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovqw_avx512vl( XmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVQW m32 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; XmmReg1 ... & m32
:VPMOVQW m32^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; XmmReg1 ... & m32
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
m32 = vpmovqw_avx512vl( XmmReg1 );
@@ -534,13 +534,13 @@ define pcodeop vpmovqw_avx512vl ;
# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114890
define pcodeop vpmovsqw_avx512vl ;
:VPMOVSQW XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSQW XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovsqw_avx512vl( XmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVSQW m32 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; XmmReg1 ... & m32
:VPMOVSQW m32^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; XmmReg1 ... & m32
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
m32 = vpmovsqw_avx512vl( XmmReg1 );
@@ -548,52 +548,52 @@ define pcodeop vpmovsqw_avx512vl ;
# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114894
define pcodeop vpmovusqw_avx512vl ;
:VPMOVUSQW XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSQW XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovusqw_avx512vl( XmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVUSQW m32 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; XmmReg1 ... & m32
:VPMOVUSQW m32^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; XmmReg1 ... & m32
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
m32 = vpmovusqw_avx512vl( XmmReg1 );
}
# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114898
:VPMOVQW XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVQW XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovqw_avx512vl( YmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVQW m64 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; YmmReg1 ... & m64
:VPMOVQW m64^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; YmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
m64 = vpmovqw_avx512vl( YmmReg1 );
}
# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114901
:VPMOVSQW XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSQW XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovsqw_avx512vl( YmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVSQW m64 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; YmmReg1 ... & m64
:VPMOVSQW m64^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; YmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
m64 = vpmovsqw_avx512vl( YmmReg1 );
}
# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114905
:VPMOVUSQW XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSQW XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovusqw_avx512vl( YmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVUSQW m64 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; YmmReg1 ... & m64
:VPMOVUSQW m64^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; YmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
m64 = vpmovusqw_avx512vl( YmmReg1 );
@@ -601,13 +601,13 @@ define pcodeop vpmovusqw_avx512vl ;
# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114909
define pcodeop vpmovqw_avx512f ;
:VPMOVQW XmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
:VPMOVQW XmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovqw_avx512f( ZmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVQW m128 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; ZmmReg1 ... & m128
:VPMOVQW m128^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; ZmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
m128 = vpmovqw_avx512f( ZmmReg1 );
@@ -615,13 +615,13 @@ define pcodeop vpmovqw_avx512f ;
# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114912
define pcodeop vpmovsqw_avx512f ;
:VPMOVSQW XmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSQW XmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovsqw_avx512f( ZmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVSQW m128 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; ZmmReg1 ... & m128
:VPMOVSQW m128^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; ZmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
m128 = vpmovsqw_avx512f( ZmmReg1 );
@@ -629,13 +629,13 @@ define pcodeop vpmovsqw_avx512f ;
# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114916
define pcodeop vpmovusqw_avx512f ;
:VPMOVUSQW XmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSQW XmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovusqw_avx512f( ZmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVUSQW m128 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; ZmmReg1 ... & m128
:VPMOVUSQW m128^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; ZmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
m128 = vpmovusqw_avx512f( ZmmReg1 );
@@ -643,13 +643,13 @@ define pcodeop vpmovusqw_avx512f ;
# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115104
define pcodeop vpmovqd_avx512vl ;
:VPMOVQD XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVQD XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovqd_avx512vl( XmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVQD m128 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; XmmReg1 ... & m128
:VPMOVQD m128^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; XmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m128 = vpmovqd_avx512vl( XmmReg1 );
@@ -657,13 +657,13 @@ define pcodeop vpmovqd_avx512vl ;
# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115108
define pcodeop vpmovsqd_avx512vl ;
:VPMOVSQD XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSQD XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovsqd_avx512vl( XmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVSQD m64 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; XmmReg1 ... & m64
:VPMOVSQD m64^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; XmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m64 = vpmovsqd_avx512vl( XmmReg1 );
@@ -671,13 +671,13 @@ define pcodeop vpmovsqd_avx512vl ;
# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115113
define pcodeop vpmovusqd_avx512vl ;
:VPMOVUSQD XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSQD XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovusqd_avx512vl( XmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVUSQD m64 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; XmmReg1 ... & m64
:VPMOVUSQD m64^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; XmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m64 = vpmovusqd_avx512vl( XmmReg1 );
@@ -685,39 +685,39 @@ define pcodeop vpmovusqd_avx512vl ;
# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115118
:VPMOVQD XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVQD XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovqd_avx512vl( YmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVQD m128 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; YmmReg1 ... & m128
:VPMOVQD m128^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; YmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m128 = vpmovqd_avx512vl( YmmReg1 );
}
# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115122
:VPMOVSQD XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSQD XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovsqd_avx512vl( YmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVSQD m128 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; YmmReg1 ... & m128
:VPMOVSQD m128^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; YmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m128 = vpmovsqd_avx512vl( YmmReg1 );
}
# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115127
:VPMOVUSQD XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSQD XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovusqd_avx512vl( YmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVUSQD m128 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; YmmReg1 ... & m128
:VPMOVUSQD m128^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; YmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m128 = vpmovusqd_avx512vl( YmmReg1 );
@@ -725,13 +725,13 @@ define pcodeop vpmovusqd_avx512vl ;
# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115131
define pcodeop vpmovqd_avx512f ;
:VPMOVQD YmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
:VPMOVQD YmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
{
YmmReg2 = vpmovqd_avx512f( ZmmReg1 );
ZmmReg2 = zext(YmmReg2);
}
:VPMOVQD m256 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; ZmmReg1 ... & m256
:VPMOVQD m256^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; ZmmReg1 ... & m256
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m256 = vpmovqd_avx512f( ZmmReg1 );
@@ -739,13 +739,13 @@ define pcodeop vpmovqd_avx512f ;
# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115134
define pcodeop vpmovsqd_avx512f ;
:VPMOVSQD YmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
:VPMOVSQD YmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
{
YmmReg2 = vpmovsqd_avx512f( ZmmReg1 );
ZmmReg2 = zext(YmmReg2);
}
:VPMOVSQD m256 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; ZmmReg1 ... & m256
:VPMOVSQD m256^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; ZmmReg1 ... & m256
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m256 = vpmovsqd_avx512f( ZmmReg1 );
@@ -753,13 +753,13 @@ define pcodeop vpmovsqd_avx512f ;
# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115138
define pcodeop vpmovusqd_avx512f ;
:VPMOVUSQD YmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
:VPMOVUSQD YmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
{
YmmReg2 = vpmovusqd_avx512f( ZmmReg1 );
ZmmReg2 = zext(YmmReg2);
}
:VPMOVUSQD m256 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; ZmmReg1 ... & m256
:VPMOVUSQD m256^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; ZmmReg1 ... & m256
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m256 = vpmovusqd_avx512f( ZmmReg1 );
@@ -767,13 +767,13 @@ define pcodeop vpmovusqd_avx512f ;
# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115748
define pcodeop vpmovwb_avx512vl ;
:VPMOVWB XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVWB XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovwb_avx512vl( XmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVWB m64 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; XmmReg1 ... & m64
:VPMOVWB m64^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; XmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m64 = vpmovwb_avx512vl( XmmReg1 );
@@ -781,13 +781,13 @@ define pcodeop vpmovwb_avx512vl ;
# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115751
define pcodeop vpmovswb_avx512vl ;
:VPMOVSWB XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSWB XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovswb_avx512vl( XmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVSWB m64 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; XmmReg1 ... & m64
:VPMOVSWB m64^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; XmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m64 = vpmovswb_avx512vl( XmmReg1 );
@@ -795,52 +795,52 @@ define pcodeop vpmovswb_avx512vl ;
# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115754
define pcodeop vpmovuswb_avx512vl ;
:VPMOVUSWB XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSWB XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovuswb_avx512vl( XmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVUSWB m64 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; XmmReg1 ... & m64
:VPMOVUSWB m64^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; XmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m64 = vpmovuswb_avx512vl( XmmReg1 );
}
# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115757
:VPMOVWB XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVWB XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovwb_avx512vl( YmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVWB m128 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; YmmReg1 ... & m128
:VPMOVWB m128^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; YmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m128 = vpmovwb_avx512vl( YmmReg1 );
}
# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115760
:VPMOVSWB XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSWB XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovswb_avx512vl( YmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVSWB m128 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; YmmReg1 ... & m128
:VPMOVSWB m128^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; YmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m128 = vpmovswb_avx512vl( YmmReg1 );
}
# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115763
:VPMOVUSWB XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSWB XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmReg2 = vpmovuswb_avx512vl( YmmReg1 );
ZmmReg2 = zext(XmmReg2);
}
:VPMOVUSWB m128 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; YmmReg1 ... & m128
:VPMOVUSWB m128^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; YmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m128 = vpmovuswb_avx512vl( YmmReg1 );
@@ -848,13 +848,13 @@ define pcodeop vpmovuswb_avx512vl ;
# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115766
define pcodeop vpmovwb_avx512bw ;
:VPMOVWB YmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
:VPMOVWB YmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
{
YmmReg2 = vpmovwb_avx512bw( ZmmReg1 );
ZmmReg2 = zext(YmmReg2);
}
:VPMOVWB m256 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; ZmmReg1 ... & m256
:VPMOVWB m256^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; ZmmReg1 ... & m256
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m256 = vpmovwb_avx512bw( ZmmReg1 );
@@ -862,13 +862,13 @@ define pcodeop vpmovwb_avx512bw ;
# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115769
define pcodeop vpmovswb_avx512bw ;
:VPMOVSWB YmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
:VPMOVSWB YmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
{
YmmReg2 = vpmovswb_avx512bw( ZmmReg1 );
ZmmReg2 = zext(YmmReg2);
}
:VPMOVSWB m256 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; ZmmReg1 ... & m256
:VPMOVSWB m256^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; ZmmReg1 ... & m256
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m256 = vpmovswb_avx512bw( ZmmReg1 );
@@ -876,13 +876,13 @@ define pcodeop vpmovswb_avx512bw ;
# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115772
define pcodeop vpmovuswb_avx512bw ;
:VPMOVUSWB YmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
:VPMOVUSWB YmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
{
YmmReg2 = vpmovuswb_avx512bw( ZmmReg1 );
ZmmReg2 = zext(YmmReg2);
}
:VPMOVUSWB m256 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; ZmmReg1 ... & m256
:VPMOVUSWB m256^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; ZmmReg1 ... & m256
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m256 = vpmovuswb_avx512bw( ZmmReg1 );

65
Ghidra/Processors/x86/data/languages/ia.sinc
View File

@@ -424,8 +424,7 @@ define context contextreg
rexprefix=(19,19) # True if the Rex prefix is present - note, if present, vex_mode is not supported
# rexWRXB bits can be re-used since they are incompatible.
evexMode=(20,21) # 2 for evex instruction, 1 for vexMode, 0 for normal
vexMode=(21,21) # 1 for vex instruction, 0 for normal
vexMode=(20,21) # 2 for evex instruction, 1 for vexMode, 0 for normal
evexL = (22,23) # 0 for 128, 1 for 256, 2 for 512 (also used for rounding control)
evexLp=(22,22) # EVEX.L'
@@ -947,10 +946,10 @@ evexDisp8N: offs is evexD8Type=1 & evexTType=0xd & evexL=1 [ offs = 5; evexDisp8
evexDisp8N: offs is evexD8Type=1 & evexTType=0xd & evexL=2 [ offs = 6; evexDisp8=offs; ] { export *[const]:1 offs; }
simm8_16: disp8N is evexMode=2 & evexDisp8N & simm8 [ disp8N = simm8 << evexDisp8; ] { export *[const]:2 disp8N; }
simm8_32: disp8N is evexMode=2 & evexDisp8N & simm8 [ disp8N = simm8 << evexDisp8; ] { export *[const]:4 disp8N; }
simm8_16: disp8N is vexMode=2 & evexDisp8N & simm8 [ disp8N = simm8 << evexDisp8; ] { export *[const]:2 disp8N; }
simm8_32: disp8N is vexMode=2 & evexDisp8N & simm8 [ disp8N = simm8 << evexDisp8; ] { export *[const]:4 disp8N; }
@ifdef IA64
simm8_64: disp8N is evexMode=2 & evexDisp8N & simm8 [ disp8N = simm8 << evexDisp8; ] { export *[const]:8 disp8N; }
simm8_64: disp8N is vexMode=2 & evexDisp8N & simm8 [ disp8N = simm8 << evexDisp8; ] { export *[const]:8 disp8N; }
@endif
usimm8_16: imm8 is imm8 & imm8_7=0 { export *[const]:2 imm8; }
@@ -1971,49 +1970,49 @@ macro fucompe(val1, val2) {
@define VEX_W0 "rexWprefix=0"
@define VEX_W1 "rexWprefix=1"
@define EVEX_NONE "evexMode=2"
@define EVEX_NDS "evexMode=2"
@define EVEX_NDD "evexMode=2"
@define EVEX_DDS "evexMode=2"
@define EVEX_NONE "vexMode=2"
@define EVEX_NDS "vexMode=2"
@define EVEX_NDD "vexMode=2"
@define EVEX_DDS "vexMode=2"
@ifdef IA64
# 64-bit 3-byte VEX
:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=0; instruction
:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=0; instruction
[ instrPhase=1; vexMode=1; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; ] {}
:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=1; instruction
:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=1; instruction
[ instrPhase=1; vexMode=1; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; prefix_66=1; ] {}
:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=2; instruction
:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=2; instruction
[ instrPhase=1; vexMode=1; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; prefix_f3=1; ] {}
:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=3; instruction
:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=3; instruction
[ instrPhase=1; vexMode=1; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; prefix_f2=1; ] {}
# 64-bit 2-byte VEX
:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=0; instruction
:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=0; instruction
[ instrPhase=1; vexMode=1; rexRprefix=~vex_r; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; ] {}
:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=1; instruction
:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=1; instruction
[ instrPhase=1; vexMode=1; rexRprefix=~vex_r; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; prefix_66=1; ] {}
:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=2; instruction
:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=2; instruction
[ instrPhase=1; vexMode=1; rexRprefix=~vex_r; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; prefix_f3=1; ] {}
:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=3; instruction
:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=3; instruction
[ instrPhase=1; vexMode=1; rexRprefix=~vex_r; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; prefix_f2=1; ] {}
# 4-byte EVEX prefix
:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r & vex_x & vex_b & evex_rp & evex_res=0 & evex_mmm;
:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r & vex_x & vex_b & evex_rp & evex_res=0 & evex_mmm;
vex_w & vex_vvvv & evex_res2=1 & vex_pp=0; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction
[ instrPhase=1; evexMode=2; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexMMMMM=evex_mmm;
[ instrPhase=1; vexMode=2; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexMMMMM=evex_mmm;
evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; ] {}
:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r & vex_x & vex_b & evex_rp & evex_res=0 & evex_mmm;
:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r & vex_x & vex_b & evex_rp & evex_res=0 & evex_mmm;
vex_w & vex_vvvv & evex_res2=1 & vex_pp=1; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction
[ instrPhase=1; evexMode=2; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexMMMMM=evex_mmm;
[ instrPhase=1; vexMode=2; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexMMMMM=evex_mmm;
evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; prefix_66=1; ] {}
:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r & vex_x & vex_b & evex_rp & evex_res=0 & evex_mmm;
:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r & vex_x & vex_b & evex_rp & evex_res=0 & evex_mmm;
vex_w & vex_vvvv & evex_res2=1 & vex_pp=2; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction
[ instrPhase=1; evexMode=2; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexMMMMM=evex_mmm;
[ instrPhase=1; vexMode=2; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexMMMMM=evex_mmm;
evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; prefix_f3=1; ] {}
:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r & vex_x & vex_b & evex_rp & evex_res=0 & evex_mmm;
:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r & vex_x & vex_b & evex_rp & evex_res=0 & evex_mmm;
vex_w & vex_vvvv & evex_res2=1 & vex_pp=3; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction
[ instrPhase=1; evexMode=2; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexMMMMM=evex_mmm;
[ instrPhase=1; vexMode=2; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexMMMMM=evex_mmm;
evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; prefix_f2=1; ] {}
@endif
@@ -2037,18 +2036,18 @@ macro fucompe(val1, val2) {
:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r=1 & vex_x=1 & vex_vvvv & vex_l & vex_pp=3; instruction
[ instrPhase=1; vexMode=1; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; prefix_f2=1; ] {}
:^instruction is $(LONGMODE_OFF) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r=1 & vex_x=1 & vex_b & evex_rp & evex_res=0 & evex_mmm;
:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r=1 & vex_x=1 & vex_b & evex_rp & evex_res=0 & evex_mmm;
vex_w & vex_vvvv & evex_res2=1 & vex_pp=0; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction
[ instrPhase=1; evexMode=2; vexVVVV=~vex_vvvv; rexBprefix=~vex_b; rexWprefix=vex_w; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; vexMMMMM=evex_mmm; ] {}
:^instruction is $(LONGMODE_OFF) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r=1 & vex_x=1 & vex_b & evex_rp & evex_res=0 & evex_mmm;
[ instrPhase=1; vexMode=2; vexVVVV=~vex_vvvv; rexBprefix=~vex_b; rexWprefix=vex_w; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; vexMMMMM=evex_mmm; ] {}
:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r=1 & vex_x=1 & vex_b & evex_rp & evex_res=0 & evex_mmm;
vex_w & vex_vvvv & evex_res2=1 & vex_pp=1; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction
[ instrPhase=1; evexMode=2; vexVVVV=~vex_vvvv; rexBprefix=~vex_b; rexWprefix=vex_w; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; vexMMMMM=evex_mmm; prefix_66=1; ] {}
:^instruction is $(LONGMODE_OFF) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r=1 & vex_x=1 & vex_b & evex_rp & evex_res=0 & evex_mmm;
[ instrPhase=1; vexMode=2; vexVVVV=~vex_vvvv; rexBprefix=~vex_b; rexWprefix=vex_w; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; vexMMMMM=evex_mmm; prefix_66=1; ] {}
:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r=1 & vex_x=1 & vex_b & evex_rp & evex_res=0 & evex_mmm;
vex_w & vex_vvvv & evex_res2=1 & vex_pp=2; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction
[ instrPhase=1; evexMode=2; vexVVVV=~vex_vvvv; rexBprefix=~vex_b; rexWprefix=vex_w; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; vexMMMMM=evex_mmm; prefix_f3=1; ] {}
:^instruction is $(LONGMODE_OFF) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r=1 & vex_x=1 & vex_b & evex_rp & evex_res=0 & evex_mmm;
[ instrPhase=1; vexMode=2; vexVVVV=~vex_vvvv; rexBprefix=~vex_b; rexWprefix=vex_w; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; vexMMMMM=evex_mmm; prefix_f3=1; ] {}
:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r=1 & vex_x=1 & vex_b & evex_rp & evex_res=0 & evex_mmm;
vex_w & vex_vvvv & evex_res2=1 & vex_pp=3; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction
[ instrPhase=1; evexMode=2; vexVVVV=~vex_vvvv; rexBprefix=~vex_b; rexWprefix=vex_w; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; vexMMMMM=evex_mmm; prefix_f2=1; ] {}
[ instrPhase=1; vexMode=2; vexVVVV=~vex_vvvv; rexBprefix=~vex_b; rexWprefix=vex_w; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; vexMMMMM=evex_mmm; prefix_f2=1; ] {}
# Many of the multimedia instructions have a "mandatory" prefix, either 0x66, 0xf2 or 0xf3
# where the prefix really becomes part of the encoding. We collect the three possible prefixes of this