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Update to RISCV processor module
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@@ -1,16 +1,49 @@
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<patternlist>
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<patternpairs totalbits="16" postbits="16">
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<patternpairs totalbits="32" postbits="0">
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<prepatterns>
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<!-- ATTN these patterns are above the insructions in sinc -->
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<!-- 76543210 54321098 32109876 10987654 -->
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<data>10000010 10000000</data> <!-- ret -->
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<data>01101111 ....0000 ........ ........</data> <!-- j imm -->
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<data>......01 101.....</data> <!-- c.j imm -->
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</prepatterns>
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<postpatterns>
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<!-- 76543210 54321098 32109876 10987654 -->
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<data>0.....01 01110001</data> <!-- c.addi16sp sp,-imm -->
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<data>0.....01 00010001</data> <!-- c.addi sp,-imm -->
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<funcstart/>
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</postpatterns>
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</patternpairs>
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<patternpairs totalbits="48" postbits="0">
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<prepatterns>
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<!-- 76543210 54321098 32109876 10987654 -->
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<data>10000010 10000000</data> <!-- ret -->
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<data>......01 101.....</data> <!-- c.j imm -->
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</prepatterns>
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<postpatterns>
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<!-- 76543210 54321098 32109876 10987654 -->
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<data>00010011 00000001 ....0001 1.......</data> <!-- addi sp,sp,-imm -->
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<data>.0010111 ........ ........ ........</data> <!-- auipc rd,imm-->
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<funcstart/>
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</postpatterns>
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</patternpairs>
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<patternpairs totalbits="48" postbits="0">
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<prepatterns>
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<!-- 76543210 54321098 32109876 10987654 -->
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<data>01101111 ....0000 ........ ........</data> <!-- j imm -->
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</prepatterns>
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<postpatterns>
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<!-- 76543210 54321098 32109876 10987654 -->
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<data>0.....01 01110001</data> <!-- c.addi16sp sp,-imm -->
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<data>0.....01 00010001</data> <!-- c.addi sp,-imm -->
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<funcstart/>
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</postpatterns>
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</patternpairs>
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<patternpairs totalbits="64" postbits="0">
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<prepatterns>
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<!-- 76543210 54321098 32109876 10987654 -->
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<data>01101111 ....0000 ........ ........</data> <!-- j imm -->
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</prepatterns>
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<postpatterns>
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<!-- 76543210 54321098 32109876 10987654 -->
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<data>00010011 00000001 ....0001 1.......</data> <!-- addi sp,sp,-imm -->
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<data>.0010111 ........ ........ ........</data> <!-- auipc rd,imm-->
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<funcstart/>
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