RISC-V processor

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[riscv] Added context register for extensions

[riscv] missed a define in refactor

[riscv] got 100% on RV32IMC

[riscv] Add throw away script to generate SLEIGH

[riscv]

Fixes from SleighDevTools

- R4-type were using a bad bit pattern that broke the rs3 operand
- mul had a copy/paste typo that ignored the rs2 operand
- bad define guard for compressesed instruction

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mumbel

2019-08-21 18:36:45 -05:00

parent 01c43efb2c

commit d7e51ee515

60 changed files with 9735 additions and 0 deletions

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Ghidra/Processors/RISCV/scripts/binutil.py Normal file

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