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GP-0: Fixed x86 AVX512 OpMask operand spacing

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ghidorahrex
2025-01-24 17:24:36 +00:00
committed by Ryan Kurtz
parent d7722f878b
commit dddc9afa9c
2 changed files with 1225 additions and 1225 deletions
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2222
Ghidra/Processors/x86/data/languages/avx512.sinc
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228
Ghidra/Processors/x86/data/languages/avx512_manual.sinc
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@@ -464,7 +464,7 @@
# VCVTPS2PH 5-37 PAGE 1861 LINE 96116
define pcodeop vcvtps2ph_avx512vl ;
:VCVTPS2PH XmmReg2 XmmOpMask, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x1D; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2; imm8
:VCVTPS2PH XmmReg2^XmmOpMask, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x1D; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2; imm8
{
XmmResult = vcvtps2ph_avx512vl( XmmReg1, imm8:1 );
XmmMask = XmmReg2;
@@ -476,7 +476,7 @@ define pcodeop vcvtps2ph_avx512vl ;
ZmmReg2 = zext(XmmResult[0,64]);
}
:VCVTPS2PH m64 XmmOpMask, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x1D; XmmReg1 ... & m64; imm8
:VCVTPS2PH m64^XmmOpMask, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x1D; XmmReg1 ... & m64; imm8
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
XmmResult = vcvtps2ph_avx512vl( XmmReg1, imm8:1 );
@@ -490,7 +490,7 @@ define pcodeop vcvtps2ph_avx512vl ;
}
# VCVTPS2PH 5-37 PAGE 1861 LINE 96119
:VCVTPS2PH XmmReg2 XmmOpMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x1D; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2; imm8
:VCVTPS2PH XmmReg2^XmmOpMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x1D; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2; imm8
{
XmmResult = vcvtps2ph_avx512vl( YmmReg1, imm8:1 );
XmmMask = XmmReg2;
@@ -507,7 +507,7 @@ define pcodeop vcvtps2ph_avx512vl ;
}
# VCVTPS2PH 5-37 PAGE 1861 LINE 96119
:VCVTPS2PH m128 XmmOpMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x1D; YmmReg1 ... & m128; imm8
:VCVTPS2PH m128^XmmOpMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x1D; YmmReg1 ... & m128; imm8
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
XmmResult = vcvtps2ph_avx512vl( YmmReg1, imm8:1 );
@@ -526,7 +526,7 @@ define pcodeop vcvtps2ph_avx512vl ;
# VCVTPS2PH 5-37 PAGE 1861 LINE 96122
define pcodeop vcvtps2ph_avx512f ;
:VCVTPS2PH YmmReg2 YmmOpMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask; byte=0x1D; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2; imm8
:VCVTPS2PH YmmReg2^YmmOpMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask; byte=0x1D; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2; imm8
{
YmmResult = vcvtps2ph_avx512f( ZmmReg1, imm8:1 );
YmmMask = YmmReg2;
@@ -550,7 +550,7 @@ define pcodeop vcvtps2ph_avx512f ;
ZmmReg2 = zext(YmmResult);
}
:VCVTPS2PH m256 YmmOpMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask; byte=0x1D; ZmmReg1 ... & m256; imm8
:VCVTPS2PH m256^YmmOpMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask; byte=0x1D; ZmmReg1 ... & m256; imm8
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
YmmResult = vcvtps2ph_avx512f( ZmmReg1, imm8:1 );
@@ -577,7 +577,7 @@ define pcodeop vcvtps2ph_avx512f ;
# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115319
define pcodeop vpmovdb_avx512vl ;
:VPMOVDB XmmReg2 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVDB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovdb_avx512vl( XmmReg1 );
XmmMask = XmmReg2;
@@ -585,7 +585,7 @@ define pcodeop vpmovdb_avx512vl ;
ZmmReg2 = zext(XmmResult[0,32]);
}
:VPMOVDB m32 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; XmmReg1 ... & m32
:VPMOVDB m32^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; XmmReg1 ... & m32
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
XmmResult = vpmovdb_avx512vl( XmmReg1 );
@@ -596,7 +596,7 @@ define pcodeop vpmovdb_avx512vl ;
# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115322
define pcodeop vpmovsdb_avx512vl ;
:VPMOVSDB XmmReg2 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSDB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovsdb_avx512vl( XmmReg1 );
XmmMask = XmmReg2;
@@ -604,7 +604,7 @@ define pcodeop vpmovsdb_avx512vl ;
ZmmReg2 = zext(XmmResult[0,32]);
}
:VPMOVSDB m32 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; XmmReg1 ... & m32
:VPMOVSDB m32^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; XmmReg1 ... & m32
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
XmmResult = vpmovsdb_avx512vl( XmmReg1 );
@@ -614,7 +614,7 @@ define pcodeop vpmovsdb_avx512vl ;
}
# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115326
define pcodeop vpmovusdb_avx512vl ;
:VPMOVUSDB XmmReg2 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSDB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovusdb_avx512vl( XmmReg1 );
XmmMask = XmmReg2;
@@ -622,7 +622,7 @@ define pcodeop vpmovusdb_avx512vl ;
ZmmReg2 = zext(XmmResult[0,32]);
}
:VPMOVUSDB m32 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; XmmReg1 ... & m32
:VPMOVUSDB m32^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; XmmReg1 ... & m32
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
XmmResult = vpmovusdb_avx512vl( XmmReg1 );
@@ -632,7 +632,7 @@ define pcodeop vpmovusdb_avx512vl ;
}
# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115330
:VPMOVDB XmmReg2 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVDB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovdb_avx512vl( YmmReg1 );
XmmMask = XmmReg2;
@@ -640,7 +640,7 @@ define pcodeop vpmovusdb_avx512vl ;
ZmmReg2 = zext(XmmResult[0,64]);
}
:VPMOVDB m64 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; YmmReg1 ... & m64
:VPMOVDB m64^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; YmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
XmmResult = vpmovdb_avx512vl( YmmReg1 );
@@ -650,7 +650,7 @@ define pcodeop vpmovusdb_avx512vl ;
}
# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115333
:VPMOVSDB XmmReg2 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSDB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovsdb_avx512vl( YmmReg1 );
XmmMask = XmmReg2;
@@ -658,7 +658,7 @@ define pcodeop vpmovusdb_avx512vl ;
ZmmReg2 = zext(XmmResult[0,64]);
}
:VPMOVSDB m64 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; YmmReg1 ... & m64
:VPMOVSDB m64^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; YmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
XmmResult = vpmovsdb_avx512vl( YmmReg1 );
@@ -668,7 +668,7 @@ define pcodeop vpmovusdb_avx512vl ;
}
# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115337
:VPMOVUSDB XmmReg2 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSDB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovusdb_avx512vl( YmmReg1 );
XmmMask = XmmReg2;
@@ -676,7 +676,7 @@ define pcodeop vpmovusdb_avx512vl ;
ZmmReg2 = zext(XmmResult[0,64]);
}
:VPMOVUSDB m64 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; YmmReg1 ... & m64
:VPMOVUSDB m64^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; YmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
XmmResult = vpmovusdb_avx512vl( YmmReg1 );
@@ -687,7 +687,7 @@ define pcodeop vpmovusdb_avx512vl ;
# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115341
define pcodeop vpmovdb_avx512f ;
:VPMOVDB XmmReg2 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
:VPMOVDB XmmReg2^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovdb_avx512f( ZmmReg1 );
XmmMask = XmmReg2;
@@ -695,7 +695,7 @@ define pcodeop vpmovdb_avx512f ;
ZmmReg2 = zext(XmmResult);
}
:VPMOVDB m128 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; ZmmReg1 ... & m128
:VPMOVDB m128^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; ZmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
XmmResult = vpmovdb_avx512f( ZmmReg1 );
@@ -706,7 +706,7 @@ define pcodeop vpmovdb_avx512f ;
# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115344
define pcodeop vpmovsdb_avx512f ;
:VPMOVSDB XmmReg2 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSDB XmmReg2^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovsdb_avx512f( ZmmReg1 );
XmmMask = XmmReg2;
@@ -714,7 +714,7 @@ define pcodeop vpmovsdb_avx512f ;
ZmmReg2 = zext(XmmResult);
}
:VPMOVSDB m128 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; ZmmReg1 ... & m128
:VPMOVSDB m128^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; ZmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
XmmResult = vpmovsdb_avx512f( ZmmReg1 );
@@ -725,7 +725,7 @@ define pcodeop vpmovsdb_avx512f ;
# VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115348
define pcodeop vpmovusdb_avx512f ;
:VPMOVUSDB XmmReg2 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSDB XmmReg2^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovusdb_avx512f( ZmmReg1 );
XmmMask = XmmReg2;
@@ -733,7 +733,7 @@ define pcodeop vpmovusdb_avx512f ;
ZmmReg2 = zext(XmmResult);
}
:VPMOVUSDB m128 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; ZmmReg1 ... & m128
:VPMOVUSDB m128^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; ZmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
XmmResult = vpmovusdb_avx512f( ZmmReg1 );
@@ -744,7 +744,7 @@ define pcodeop vpmovusdb_avx512f ;
# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115532
define pcodeop vpmovdw_avx512vl ;
:VPMOVDW XmmReg2 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x33; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVDW XmmReg2^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x33; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovdw_avx512vl( XmmReg1 );
XmmMask = XmmReg2;
@@ -752,7 +752,7 @@ define pcodeop vpmovdw_avx512vl ;
ZmmReg2 = zext(XmmResult[0,64]);
}
:VPMOVDW m64 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x33; XmmReg1 ... & m64
:VPMOVDW m64^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x33; XmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
XmmResult = vpmovdw_avx512vl( XmmReg1 );
@@ -763,7 +763,7 @@ define pcodeop vpmovdw_avx512vl ;
# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115535
define pcodeop vpmovsdw_avx512vl ;
:VPMOVSDW XmmReg2 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x23; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSDW XmmReg2^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x23; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovsdw_avx512vl( XmmReg1 );
XmmMask = XmmReg2;
@@ -771,7 +771,7 @@ define pcodeop vpmovsdw_avx512vl ;
ZmmReg2 = zext(XmmResult[0,64]);
}
:VPMOVSDW m64 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x23; XmmReg1 ... & m64
:VPMOVSDW m64^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x23; XmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
XmmResult = vpmovsdw_avx512vl( XmmReg1 );
@@ -782,7 +782,7 @@ define pcodeop vpmovsdw_avx512vl ;
# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115539
define pcodeop vpmovusdw_avx512vl ;
:VPMOVUSDW XmmReg2 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x13; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSDW XmmReg2^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x13; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovusdw_avx512vl( XmmReg1 );
XmmMask = XmmReg2;
@@ -790,7 +790,7 @@ define pcodeop vpmovusdw_avx512vl ;
ZmmReg2 = zext(XmmResult[0,64]);
}
:VPMOVUSDW m64 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x13; XmmReg1 ... & m64
:VPMOVUSDW m64^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x13; XmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
XmmResult = vpmovusdw_avx512vl( XmmReg1 );
@@ -800,7 +800,7 @@ define pcodeop vpmovusdw_avx512vl ;
}
# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115543
:VPMOVDW XmmReg2 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x33; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVDW XmmReg2^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x33; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovdw_avx512vl( YmmReg1 );
XmmMask = XmmReg2;
@@ -808,7 +808,7 @@ define pcodeop vpmovusdw_avx512vl ;
ZmmReg2 = zext(XmmResult[0,64]);
}
:VPMOVDW m128 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x33; YmmReg1 ... & m128
:VPMOVDW m128^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x33; YmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
XmmResult = vpmovdw_avx512vl( YmmReg1 );
@@ -818,7 +818,7 @@ define pcodeop vpmovusdw_avx512vl ;
}
# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115546
:VPMOVSDW XmmReg2 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x23; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSDW XmmReg2^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x23; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovsdw_avx512vl( YmmReg1 );
XmmMask = XmmReg2;
@@ -826,7 +826,7 @@ define pcodeop vpmovusdw_avx512vl ;
ZmmReg2 = zext(XmmResult);
}
:VPMOVSDW m128 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x23; YmmReg1 ... & m128
:VPMOVSDW m128^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x23; YmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
XmmResult = vpmovsdw_avx512vl( YmmReg1 );
@@ -836,7 +836,7 @@ define pcodeop vpmovusdw_avx512vl ;
}
# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115550
:VPMOVUSDW XmmReg2 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x13; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSDW XmmReg2^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x13; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovusdw_avx512vl( YmmReg1 );
XmmMask = XmmReg2;
@@ -844,7 +844,7 @@ define pcodeop vpmovusdw_avx512vl ;
ZmmReg2 = zext(XmmResult);
}
:VPMOVUSDW m128 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x13; YmmReg1 ... & m128
:VPMOVUSDW m128^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x13; YmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
XmmResult = vpmovusdw_avx512vl( YmmReg1 );
@@ -855,7 +855,7 @@ define pcodeop vpmovusdw_avx512vl ;
# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115554
define pcodeop vpmovdw_avx512f ;
:VPMOVDW YmmReg2 YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x33; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
:VPMOVDW YmmReg2^YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x33; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
{
YmmResult = vpmovdw_avx512f( ZmmReg1 );
YmmMask = YmmReg2;
@@ -863,7 +863,7 @@ define pcodeop vpmovdw_avx512f ;
ZmmReg2 = zext(YmmResult);
}
:VPMOVDW m256 YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x33; ZmmReg1 ... & m256
:VPMOVDW m256^YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x33; ZmmReg1 ... & m256
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
YmmResult = vpmovdw_avx512f( ZmmReg1 );
@@ -874,7 +874,7 @@ define pcodeop vpmovdw_avx512f ;
# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115557
define pcodeop vpmovsdw_avx512f ;
:VPMOVSDW YmmReg2 YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x23; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
:VPMOVSDW YmmReg2^YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x23; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
{
YmmResult = vpmovsdw_avx512f( ZmmReg1 );
YmmMask = YmmReg2;
@@ -882,7 +882,7 @@ define pcodeop vpmovsdw_avx512f ;
ZmmReg2 = zext(YmmResult);
}
:VPMOVSDW m256 YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x23; ZmmReg1 ... & m256
:VPMOVSDW m256^YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x23; ZmmReg1 ... & m256
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
YmmResult = vpmovsdw_avx512f( ZmmReg1 );
@@ -893,7 +893,7 @@ define pcodeop vpmovsdw_avx512f ;
# VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115561
define pcodeop vpmovusdw_avx512f ;
:VPMOVUSDW YmmReg2 YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x13; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
:VPMOVUSDW YmmReg2^YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x13; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
{
YmmResult = vpmovusdw_avx512f( ZmmReg1 );
YmmMask = YmmReg2;
@@ -901,7 +901,7 @@ define pcodeop vpmovusdw_avx512f ;
ZmmReg2 = zext(YmmResult);
}
:VPMOVUSDW m256 YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x13; ZmmReg1 ... & m256
:VPMOVUSDW m256^YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x13; ZmmReg1 ... & m256
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
YmmResult = vpmovusdw_avx512f( ZmmReg1 );
@@ -912,7 +912,7 @@ define pcodeop vpmovusdw_avx512f ;
# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114671
define pcodeop vpmovqb_avx512vl ;
:VPMOVQB XmmReg2 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVQB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovqb_avx512vl( XmmReg1 );
XmmMask = XmmReg2;
@@ -920,7 +920,7 @@ define pcodeop vpmovqb_avx512vl ;
ZmmReg2 = zext(XmmResult[0,16]);
}
:VPMOVQB m16 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; XmmReg1 ... & m16
:VPMOVQB m16^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; XmmReg1 ... & m16
[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)
{
XmmResult = vpmovqb_avx512vl( XmmReg1 );
@@ -931,7 +931,7 @@ define pcodeop vpmovqb_avx512vl ;
# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114674
define pcodeop vpmovsqb_avx512vl ;
:VPMOVSQB XmmReg2 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSQB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovsqb_avx512vl( XmmReg1 );
XmmMask = XmmReg2;
@@ -939,7 +939,7 @@ define pcodeop vpmovsqb_avx512vl ;
ZmmReg2 = zext(XmmResult[0,16]);
}
:VPMOVSQB m16 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; XmmReg1 ... & m16
:VPMOVSQB m16^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; XmmReg1 ... & m16
[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)
{
XmmResult = vpmovsqb_avx512vl( XmmReg1 );
@@ -950,7 +950,7 @@ define pcodeop vpmovsqb_avx512vl ;
# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114678
define pcodeop vpmovusqb_avx512vl ;
:VPMOVUSQB XmmReg2 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSQB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovusqb_avx512vl( XmmReg1 );
XmmMask = XmmReg2;
@@ -958,7 +958,7 @@ define pcodeop vpmovusqb_avx512vl ;
ZmmReg2 = zext(XmmResult[0,16]);
}
:VPMOVUSQB m16 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; XmmReg1 ... & m16
:VPMOVUSQB m16^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; XmmReg1 ... & m16
[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)
{
XmmResult = vpmovusqb_avx512vl( XmmReg1 );
@@ -968,7 +968,7 @@ define pcodeop vpmovusqb_avx512vl ;
}
# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114682
:VPMOVQB XmmReg2 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVQB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovqb_avx512vl( YmmReg1 );
XmmMask = XmmReg2;
@@ -976,7 +976,7 @@ define pcodeop vpmovusqb_avx512vl ;
ZmmReg2 = zext(XmmResult[0,32]);
}
:VPMOVQB m32 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; YmmReg1 ... & m32
:VPMOVQB m32^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; YmmReg1 ... & m32
[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)
{
XmmResult = vpmovqb_avx512vl( YmmReg1 );
@@ -986,7 +986,7 @@ define pcodeop vpmovusqb_avx512vl ;
}
# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114685
:VPMOVSQB XmmReg2 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSQB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovsqb_avx512vl( YmmReg1 );
XmmMask = XmmReg2;
@@ -994,7 +994,7 @@ define pcodeop vpmovusqb_avx512vl ;
ZmmReg2 = zext(XmmResult[0,32]);
}
:VPMOVSQB m32 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; YmmReg1 ... & m32
:VPMOVSQB m32^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; YmmReg1 ... & m32
[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)
{
XmmResult = vpmovsqb_avx512vl( YmmReg1 );
@@ -1004,7 +1004,7 @@ define pcodeop vpmovusqb_avx512vl ;
}
# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114689
:VPMOVUSQB XmmReg2 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSQB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovusqb_avx512vl( YmmReg1 );
XmmMask = XmmReg2;
@@ -1012,7 +1012,7 @@ define pcodeop vpmovusqb_avx512vl ;
ZmmReg2 = zext(XmmResult[0,32]);
}
:VPMOVUSQB m32 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; YmmReg1 ... & m32
:VPMOVUSQB m32^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; YmmReg1 ... & m32
[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)
{
XmmResult = vpmovusqb_avx512vl( YmmReg1 );
@@ -1023,7 +1023,7 @@ define pcodeop vpmovusqb_avx512vl ;
# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114693
define pcodeop vpmovqb_avx512f ;
:VPMOVQB XmmReg2 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
:VPMOVQB XmmReg2^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovqb_avx512f( ZmmReg1 );
XmmMask = XmmReg2;
@@ -1031,7 +1031,7 @@ define pcodeop vpmovqb_avx512f ;
ZmmReg2 = zext(XmmResult[0,64]);
}
:VPMOVQB m64 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; ZmmReg1 ... & m64
:VPMOVQB m64^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; ZmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)
{
XmmResult = vpmovqb_avx512f( ZmmReg1 );
@@ -1042,7 +1042,7 @@ define pcodeop vpmovqb_avx512f ;
# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114696
define pcodeop vpmovsqb_avx512f ;
:VPMOVSQB XmmReg2 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSQB XmmReg2^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovsqb_avx512f( ZmmReg1 );
XmmMask = XmmReg2;
@@ -1050,7 +1050,7 @@ define pcodeop vpmovsqb_avx512f ;
ZmmReg2 = zext(XmmResult[0,64]);
}
:VPMOVSQB m64 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; ZmmReg1 ... & m64
:VPMOVSQB m64^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; ZmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)
{
XmmResult = vpmovsqb_avx512f( ZmmReg1 );
@@ -1061,7 +1061,7 @@ define pcodeop vpmovsqb_avx512f ;
# VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114700
define pcodeop vpmovusqb_avx512f ;
:VPMOVUSQB XmmReg2 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSQB XmmReg2^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovusqb_avx512f( ZmmReg1 );
XmmMask = XmmReg2;
@@ -1069,7 +1069,7 @@ define pcodeop vpmovusqb_avx512f ;
ZmmReg2 = zext(XmmResult[0,64]);
}
:VPMOVUSQB m64 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; ZmmReg1 ... & m64
:VPMOVUSQB m64^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; ZmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM)
{
XmmResult = vpmovusqb_avx512f( ZmmReg1 );
@@ -1080,7 +1080,7 @@ define pcodeop vpmovusqb_avx512f ;
# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114887
define pcodeop vpmovqw_avx512vl ;
:VPMOVQW XmmReg2 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVQW XmmReg2^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovqw_avx512vl( XmmReg1 );
XmmMask = XmmReg2;
@@ -1088,7 +1088,7 @@ define pcodeop vpmovqw_avx512vl ;
ZmmReg2 = zext(XmmResult[0,32]);
}
:VPMOVQW m32 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; XmmReg1 ... & m32
:VPMOVQW m32^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; XmmReg1 ... & m32
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
XmmResult = vpmovqw_avx512vl( XmmReg1 );
@@ -1099,7 +1099,7 @@ define pcodeop vpmovqw_avx512vl ;
# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114890
define pcodeop vpmovsqw_avx512vl ;
:VPMOVSQW XmmReg2 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSQW XmmReg2^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovsqw_avx512vl( XmmReg1 );
XmmMask = XmmReg2;
@@ -1107,7 +1107,7 @@ define pcodeop vpmovsqw_avx512vl ;
ZmmReg2 = zext(XmmResult[0,32]);
}
:VPMOVSQW m32 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; XmmReg1 ... & m32
:VPMOVSQW m32^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; XmmReg1 ... & m32
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
XmmResult = vpmovsqw_avx512vl( XmmReg1 );
@@ -1118,7 +1118,7 @@ define pcodeop vpmovsqw_avx512vl ;
# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114894
define pcodeop vpmovusqw_avx512vl ;
:VPMOVUSQW XmmReg2 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSQW XmmReg2^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovusqw_avx512vl( XmmReg1 );
XmmMask = XmmReg2;
@@ -1126,7 +1126,7 @@ define pcodeop vpmovusqw_avx512vl ;
ZmmReg2 = zext(XmmResult[0,32]);
}
:VPMOVUSQW m32 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; XmmReg1 ... & m32
:VPMOVUSQW m32^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; XmmReg1 ... & m32
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
XmmResult = vpmovusqw_avx512vl( XmmReg1 );
@@ -1136,7 +1136,7 @@ define pcodeop vpmovusqw_avx512vl ;
}
# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114898
:VPMOVQW XmmReg2 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVQW XmmReg2^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovqw_avx512vl( YmmReg1 );
XmmMask = XmmReg2;
@@ -1144,7 +1144,7 @@ define pcodeop vpmovusqw_avx512vl ;
ZmmReg2 = zext(XmmResult[0,64]);
}
:VPMOVQW m64 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; YmmReg1 ... & m64
:VPMOVQW m64^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; YmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
XmmResult = vpmovqw_avx512vl( YmmReg1 );
@@ -1154,7 +1154,7 @@ define pcodeop vpmovusqw_avx512vl ;
}
# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114901
:VPMOVSQW XmmReg2 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSQW XmmReg2^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovsqw_avx512vl( YmmReg1 );
XmmMask = XmmReg2;
@@ -1162,7 +1162,7 @@ define pcodeop vpmovusqw_avx512vl ;
ZmmReg2 = zext(XmmResult[0,64]);
}
:VPMOVSQW m64 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; YmmReg1 ... & m64
:VPMOVSQW m64^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; YmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
XmmResult = vpmovsqw_avx512vl( YmmReg1 );
@@ -1172,7 +1172,7 @@ define pcodeop vpmovusqw_avx512vl ;
}
# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114905
:VPMOVUSQW XmmReg2 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSQW XmmReg2^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovusqw_avx512vl( YmmReg1 );
XmmMask = XmmReg2;
@@ -1180,7 +1180,7 @@ define pcodeop vpmovusqw_avx512vl ;
ZmmReg2 = zext(XmmResult[0,64]);
}
:VPMOVUSQW m64 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; YmmReg1 ... & m64
:VPMOVUSQW m64^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; YmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
XmmResult = vpmovusqw_avx512vl( YmmReg1 );
@@ -1191,7 +1191,7 @@ define pcodeop vpmovusqw_avx512vl ;
# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114909
define pcodeop vpmovqw_avx512f ;
:VPMOVQW XmmReg2 XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
:VPMOVQW XmmReg2^XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovqw_avx512f( ZmmReg1 );
XmmMask = XmmReg2;
@@ -1199,7 +1199,7 @@ define pcodeop vpmovqw_avx512f ;
ZmmReg2 = zext(XmmResult);
}
:VPMOVQW m128 XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; ZmmReg1 ... & m128
:VPMOVQW m128^XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; ZmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
XmmResult = vpmovqw_avx512f( ZmmReg1 );
@@ -1210,7 +1210,7 @@ define pcodeop vpmovqw_avx512f ;
# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114912
define pcodeop vpmovsqw_avx512f ;
:VPMOVSQW XmmReg2 XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSQW XmmReg2^XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovsqw_avx512f( ZmmReg1 );
XmmMask = XmmReg2;
@@ -1218,7 +1218,7 @@ define pcodeop vpmovsqw_avx512f ;
ZmmReg2 = zext(XmmResult);
}
:VPMOVSQW m128 XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; ZmmReg1 ... & m128
:VPMOVSQW m128^XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; ZmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
XmmResult = vpmovsqw_avx512f( ZmmReg1 );
@@ -1229,7 +1229,7 @@ define pcodeop vpmovsqw_avx512f ;
# VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114916
define pcodeop vpmovusqw_avx512f ;
:VPMOVUSQW XmmReg2 XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSQW XmmReg2^XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovusqw_avx512f( ZmmReg1 );
XmmMask = XmmReg2;
@@ -1237,7 +1237,7 @@ define pcodeop vpmovusqw_avx512f ;
ZmmReg2 = zext(XmmResult);
}
:VPMOVUSQW m128 XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; ZmmReg1 ... & m128
:VPMOVUSQW m128^XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; ZmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM)
{
XmmResult = vpmovusqw_avx512f( ZmmReg1 );
@@ -1248,7 +1248,7 @@ define pcodeop vpmovusqw_avx512f ;
# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115104
define pcodeop vpmovqd_avx512vl ;
:VPMOVQD XmmReg2 XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x35; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVQD XmmReg2^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x35; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovqd_avx512vl( XmmReg1 );
XmmMask = XmmReg2;
@@ -1256,7 +1256,7 @@ define pcodeop vpmovqd_avx512vl ;
ZmmReg2 = zext(XmmResult);
}
:VPMOVQD m128 XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x35; XmmReg1 ... & m128
:VPMOVQD m128^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x35; XmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
XmmResult = vpmovqd_avx512vl( XmmReg1 );
@@ -1267,7 +1267,7 @@ define pcodeop vpmovqd_avx512vl ;
# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115108
define pcodeop vpmovsqd_avx512vl ;
:VPMOVSQD XmmReg2 XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x25; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSQD XmmReg2^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x25; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovsqd_avx512vl( XmmReg1 );
XmmMask = XmmReg2;
@@ -1275,7 +1275,7 @@ define pcodeop vpmovsqd_avx512vl ;
ZmmReg2 = zext(XmmResult[0,64]);
}
:VPMOVSQD m64 XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x25; XmmReg1 ... & m64
:VPMOVSQD m64^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x25; XmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
XmmResult = vpmovsqd_avx512vl( XmmReg1 );
@@ -1286,7 +1286,7 @@ define pcodeop vpmovsqd_avx512vl ;
# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115113
define pcodeop vpmovusqd_avx512vl ;
:VPMOVUSQD XmmReg2 XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x15; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSQD XmmReg2^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x15; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovusqd_avx512vl( XmmReg1 );
XmmMask = XmmReg2;
@@ -1294,7 +1294,7 @@ define pcodeop vpmovusqd_avx512vl ;
ZmmReg2 = zext(XmmResult[0,64]);
}
:VPMOVUSQD m64 XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x15; XmmReg1 ... & m64
:VPMOVUSQD m64^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x15; XmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
m64 = vpmovusqd_avx512vl( XmmReg1 );
@@ -1305,7 +1305,7 @@ define pcodeop vpmovusqd_avx512vl ;
# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115118
:VPMOVQD XmmReg2 XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x35; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVQD XmmReg2^XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x35; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovqd_avx512vl( YmmReg1 );
XmmMask = XmmReg2;
@@ -1313,7 +1313,7 @@ define pcodeop vpmovusqd_avx512vl ;
ZmmReg2 = zext(XmmResult);
}
:VPMOVQD m128 XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x35; YmmReg1 ... & m128
:VPMOVQD m128^XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x35; YmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
XmmResult = vpmovqd_avx512vl( YmmReg1 );
@@ -1323,7 +1323,7 @@ define pcodeop vpmovusqd_avx512vl ;
}
# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115122
:VPMOVSQD XmmReg2 XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x25; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSQD XmmReg2^XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x25; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovsqd_avx512vl( YmmReg1 );
XmmMask = XmmReg2;
@@ -1331,7 +1331,7 @@ define pcodeop vpmovusqd_avx512vl ;
ZmmReg2 = zext(XmmResult);
}
:VPMOVSQD m128 XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x25; YmmReg1 ... & m128
:VPMOVSQD m128^XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x25; YmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
XmmResult = vpmovsqd_avx512vl( YmmReg1 );
@@ -1341,7 +1341,7 @@ define pcodeop vpmovusqd_avx512vl ;
}
# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115127
:VPMOVUSQD XmmReg2 XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x15; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSQD XmmReg2^XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x15; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovusqd_avx512vl( YmmReg1 );
XmmMask = XmmReg2;
@@ -1349,7 +1349,7 @@ define pcodeop vpmovusqd_avx512vl ;
ZmmReg2 = zext(XmmResult);
}
:VPMOVUSQD m128 XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x15; YmmReg1 ... & m128
:VPMOVUSQD m128^XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x15; YmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
XmmResult = vpmovusqd_avx512vl( YmmReg1 );
@@ -1360,7 +1360,7 @@ define pcodeop vpmovusqd_avx512vl ;
# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115131
define pcodeop vpmovqd_avx512f ;
:VPMOVQD YmmReg2 YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x35; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
:VPMOVQD YmmReg2^YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x35; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
{
YmmResult = vpmovqd_avx512f( ZmmReg1 );
YmmMask = YmmReg2;
@@ -1368,7 +1368,7 @@ define pcodeop vpmovqd_avx512f ;
ZmmReg2 = zext(YmmResult);
}
:VPMOVQD m256 YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x35; ZmmReg1 ... & m256
:VPMOVQD m256^YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x35; ZmmReg1 ... & m256
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
YmmResult = vpmovqd_avx512f( ZmmReg1 );
@@ -1379,7 +1379,7 @@ define pcodeop vpmovqd_avx512f ;
# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115134
define pcodeop vpmovsqd_avx512f ;
:VPMOVSQD YmmReg2 YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x25; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
:VPMOVSQD YmmReg2^YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x25; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
{
YmmResult = vpmovsqd_avx512f( ZmmReg1 );
YmmMask = YmmReg2;
@@ -1387,7 +1387,7 @@ define pcodeop vpmovsqd_avx512f ;
ZmmReg2 = zext(YmmResult);
}
:VPMOVSQD m256 YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x25; ZmmReg1 ... & m256
:VPMOVSQD m256^YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x25; ZmmReg1 ... & m256
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
YmmResult = vpmovsqd_avx512f( ZmmReg1 );
@@ -1398,7 +1398,7 @@ define pcodeop vpmovsqd_avx512f ;
# VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115138
define pcodeop vpmovusqd_avx512f ;
:VPMOVUSQD YmmReg2 YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x15; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
:VPMOVUSQD YmmReg2^YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x15; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
{
YmmResult = vpmovusqd_avx512f( ZmmReg1 );
YmmMask = YmmReg2;
@@ -1406,7 +1406,7 @@ define pcodeop vpmovusqd_avx512f ;
ZmmReg2 = zext(YmmResult);
}
:VPMOVUSQD m256 YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x15; ZmmReg1 ... & m256
:VPMOVUSQD m256^YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x15; ZmmReg1 ... & m256
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
YmmResult = vpmovusqd_avx512f( ZmmReg1 );
@@ -1417,7 +1417,7 @@ define pcodeop vpmovusqd_avx512f ;
# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115748
define pcodeop vpmovwb_avx512vl ;
:VPMOVWB XmmReg2 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x30; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVWB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x30; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovwb_avx512vl( XmmReg1 );
XmmMask = XmmReg2;
@@ -1425,7 +1425,7 @@ define pcodeop vpmovwb_avx512vl ;
ZmmReg2 = zext(XmmResult[0,64]);
}
:VPMOVWB m64 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x30; XmmReg1 ... & m64
:VPMOVWB m64^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x30; XmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
XmmResult = vpmovwb_avx512vl( XmmReg1 );
@@ -1436,7 +1436,7 @@ define pcodeop vpmovwb_avx512vl ;
# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115751
define pcodeop vpmovswb_avx512vl ;
:VPMOVSWB XmmReg2 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x20; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSWB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x20; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovswb_avx512vl( XmmReg1 );
XmmMask = XmmReg2;
@@ -1444,7 +1444,7 @@ define pcodeop vpmovswb_avx512vl ;
ZmmReg2 = zext(XmmResult[0,64]);
}
:VPMOVSWB m64 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x20; XmmReg1 ... & m64
:VPMOVSWB m64^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x20; XmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
XmmResult = vpmovswb_avx512vl( XmmReg1 );
@@ -1455,7 +1455,7 @@ define pcodeop vpmovswb_avx512vl ;
# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115754
define pcodeop vpmovuswb_avx512vl ;
:VPMOVUSWB XmmReg2 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x10; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSWB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x10; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovuswb_avx512vl( XmmReg1 );
XmmMask = XmmReg2;
@@ -1463,7 +1463,7 @@ define pcodeop vpmovuswb_avx512vl ;
ZmmReg2 = zext(XmmResult[0,64]);
}
:VPMOVUSWB m64 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x10; XmmReg1 ... & m64
:VPMOVUSWB m64^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x10; XmmReg1 ... & m64
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
XmmResult = vpmovuswb_avx512vl( XmmReg1 );
@@ -1473,7 +1473,7 @@ define pcodeop vpmovuswb_avx512vl ;
}
# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115757
:VPMOVWB XmmReg2 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x30; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVWB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x30; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovwb_avx512vl( YmmReg1 );
XmmMask = XmmReg2;
@@ -1482,7 +1482,7 @@ define pcodeop vpmovuswb_avx512vl ;
}
:VPMOVWB m128 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x30; YmmReg1 ... & m128
:VPMOVWB m128^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x30; YmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
XmmResult = vpmovwb_avx512vl( YmmReg1 );
@@ -1492,7 +1492,7 @@ define pcodeop vpmovuswb_avx512vl ;
}
# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115760
:VPMOVSWB XmmReg2 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x20; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVSWB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x20; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovswb_avx512vl( YmmReg1 );
XmmMask = XmmReg2;
@@ -1500,7 +1500,7 @@ define pcodeop vpmovuswb_avx512vl ;
ZmmReg2 = zext(XmmResult);
}
:VPMOVSWB m128 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x20; YmmReg1 ... & m128
:VPMOVSWB m128^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x20; YmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
XmmResult = vpmovswb_avx512vl( YmmReg1 );
@@ -1510,7 +1510,7 @@ define pcodeop vpmovuswb_avx512vl ;
}
# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115763
:VPMOVUSWB XmmReg2 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x10; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
:VPMOVUSWB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x10; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2
{
XmmResult = vpmovuswb_avx512vl( YmmReg1 );
XmmMask = XmmReg2;
@@ -1518,7 +1518,7 @@ define pcodeop vpmovuswb_avx512vl ;
ZmmReg2 = zext(XmmResult);
}
:VPMOVUSWB m128 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x10; YmmReg1 ... & m128
:VPMOVUSWB m128^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x10; YmmReg1 ... & m128
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
XmmResult = vpmovuswb_avx512vl( YmmReg1 );
@@ -1529,7 +1529,7 @@ define pcodeop vpmovuswb_avx512vl ;
# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115766
define pcodeop vpmovwb_avx512bw ;
:VPMOVWB YmmReg2 YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x30; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
:VPMOVWB YmmReg2^YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x30; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
{
YmmResult = vpmovwb_avx512bw( ZmmReg1 );
YmmMask = YmmReg2;
@@ -1537,7 +1537,7 @@ define pcodeop vpmovwb_avx512bw ;
ZmmReg2 = zext(YmmResult);
}
:VPMOVWB m256 YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x30; ZmmReg1 ... & m256
:VPMOVWB m256^YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x30; ZmmReg1 ... & m256
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
YmmResult = vpmovwb_avx512bw( ZmmReg1 );
@@ -1548,7 +1548,7 @@ define pcodeop vpmovwb_avx512bw ;
# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115769
define pcodeop vpmovswb_avx512bw ;
:VPMOVSWB YmmReg2 YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x20; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
:VPMOVSWB YmmReg2^YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x20; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
{
YmmResult = vpmovswb_avx512bw( ZmmReg1 );
YmmMask = YmmReg2;
@@ -1556,7 +1556,7 @@ define pcodeop vpmovswb_avx512bw ;
ZmmReg2 = zext(YmmResult);
}
:VPMOVSWB m256 YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x20; ZmmReg1 ... & m256
:VPMOVSWB m256^YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x20; ZmmReg1 ... & m256
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
YmmResult = vpmovswb_avx512bw( ZmmReg1 );
@@ -1567,7 +1567,7 @@ define pcodeop vpmovswb_avx512bw ;
# VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115772
define pcodeop vpmovuswb_avx512bw ;
:VPMOVUSWB YmmReg2 YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x10; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
:VPMOVUSWB YmmReg2^YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x10; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2
{
YmmResult = vpmovuswb_avx512bw( ZmmReg1 );
YmmMask = YmmReg2;
@@ -1575,7 +1575,7 @@ define pcodeop vpmovuswb_avx512bw ;
ZmmReg2 = zext(YmmResult);
}
:VPMOVUSWB m256 YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x10; ZmmReg1 ... & m256
:VPMOVUSWB m256^YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x10; ZmmReg1 ... & m256
[ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM)
{
YmmResult = vpmovuswb_avx512bw( ZmmReg1 );