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riscv: handle divideby0

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Sleigh-InSPECtor
2024-05-15 16:17:17 +09:30
committed by ghidorahrex
parent 05aae4a59e
commit edb05a43b9
2 changed files with 14 additions and 0 deletions
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10
Ghidra/Processors/RISCV/data/languages/riscv.rv32m.sinc
View File

@@ -1,8 +1,15 @@
# RV32M Standard Extension
macro checkDivByZero(reg, rd, adjustment) {
if (reg != 0) goto <NOTZERO>;
rd = adjustment;
goto inst_next;
<NOTZERO>
}
# div d,s,t 02004033 fe00707f SIMPLE (0, 0)
:div rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x4 & funct7=0x1
{
checkDivByZero(rs2, rd, ~0);
rd = rs1 s/ rs2;
}
@@ -10,6 +17,7 @@
# divu d,s,t 02005033 fe00707f SIMPLE (0, 0)
:divu rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x5 & funct7=0x1
{
checkDivByZero(rs2, rd, ~0);
rd = rs1 / rs2;
}
@@ -54,6 +62,7 @@
# rem d,s,t 02006033 fe00707f SIMPLE (0, 0)
:rem rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x6 & funct7=0x1
{
checkDivByZero(rs2, rd, rs1);
rd = rs1 s% rs2;
}
@@ -61,5 +70,6 @@
# remu d,s,t 02007033 fe00707f SIMPLE (0, 0)
:remu rd,rs1,rs2 is rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x7 & funct7=0x1
{
checkDivByZero(rs2, rd, rs1);
rd = rs1 % rs2;
}

4
Ghidra/Processors/RISCV/data/languages/riscv.rv64m.sinc
View File

@@ -5,6 +5,7 @@
{
local tmpr1:4 = rs1:4;
local tmpr2:4 = rs2:4;
checkDivByZero(tmpr2, rd, ~0);
rd = sext(tmpr1 / tmpr2);
}
@@ -14,6 +15,7 @@
{
local tmpr1:4 = rs1:4;
local tmpr2:4 = rs2:4;
checkDivByZero(tmpr2, rd, ~0);
rd = sext(tmpr1 s/ tmpr2);
}
@@ -31,6 +33,7 @@
{
local tmpr1:4 = rs1:4;
local tmpr2:4 = rs2:4;
checkDivByZero(tmpr2, rd, sext(tmpr1));
rd = sext(tmpr1 % tmpr2);
}
@@ -40,5 +43,6 @@
{
local tmpr1:4 = rs1:4;
local tmpr2:4 = rs2:4;
checkDivByZero(tmpr2, rd, sext(tmpr1));
rd = sext(tmpr1 s% tmpr2);
}