mirror/ghidra
1
0
Fork 0
mirror of https://github.com/NationalSecurityAgency/ghidra.git synced 2026-09-28 17:11:11 -09:00
Code Issues Packages Projects Releases Wiki Activity

Merge remote-tracking branch

Browse Source 
'origin/GP-3432_ghidorahrex_PR-4887_Ninja3047_ppc_vle_eieio' into patch
(Closes #4887)
This commit is contained in:
Ryan Kurtz
2023-05-18 10:57:28 -04:00
parent 79c9e5cee6 9c694ebfd1
commit f8ebb729ef
5 changed files with 11 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
Ghidra/Processors/PowerPC/data/languages/ppc_a2.sinc
View File

@@ -85,14 +85,6 @@ define pcodeop wclrallOp;
define pcodeop wclrOp; define pcodeop wclrOp;
# :wclr L,A,B is $(NOTVLE) & OP=31 & XOP_1_10=934 & L & A & B { wclrOp(); } # :wclr L,A,B is $(NOTVLE) & OP=31 & XOP_1_10=934 & L & A & B { wclrOp(); }
@ifdef IS_ISA
# binutils: 476.d 474: 7c 00 06 ac mbar
# binutils: 476.d 47c: 7c 20 06 ac mbar 1
# "mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, PPCNONE, {MO}
define pcodeop mbarOp;
:mbar MO is OP=31 & XOP_1_10=854 & MO { mbarOp(); }
@endif
# binutils: a2.d: 514: 7d 4a 3a 87 mfdcr\. r10,234 # binutils: a2.d: 514: 7d 4a 3a 87 mfdcr\. r10,234
:mfdcr. D, DCRN is $(NOTVLE) & OP=31 & D & DCRN & XOP_1_10=323 & BIT_0=1 :mfdcr. D, DCRN is $(NOTVLE) & OP=31 & D & DCRN & XOP_1_10=323 & BIT_0=1
{ {

10
Ghidra/Processors/PowerPC/data/languages/ppc_embedded.sinc
View File

@@ -49,14 +49,12 @@
dataCacheBlockClearToZero(ea); dataCacheBlockClearToZero(ea);
} }
@ifndef IS_ISA define pcodeop memoryBarrier;
# this is equilent to "mbar 0" #mbar 0 7c 00 06 ac
#eieio 0x7c 00 06 ac :mbar MO is OP=31 & MO & XOP_1_10=854
:eieio is $(NOTVLE) & OP=31 & BITS_21_25=0 & BITS_16_20=0 & BITS_11_15=0 & XOP_1_10=854 & BIT_0=0
{ {
enforceInOrderExecutionIO(); memoryBarrier(MO:1);
} }
@endif
#icbi r0,r0 0x7c 00 07 ac #icbi r0,r0 0x7c 00 07 ac
:icbi RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=982 & BIT_0=0 & RA_OR_ZERO :icbi RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=982 & BIT_0=0 & RA_OR_ZERO

7
Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc
View File

@@ -1087,6 +1087,13 @@
externalControlOut(ea, S); externalControlOut(ea, S);
} }
#===========================================================
# EIEIO
#===========================================================
# binutils-descr: "eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}
# binutils: mytest.d: 20: 7c 00 06 ac eieio
:eieio is OP=31 & XOP_1_10=854 & BITS_11_25=0 & BIT_0=0 { enforceInOrderExecutionIO(); }
#=========================================================== #===========================================================
# EQVx # EQVx
#=========================================================== #===========================================================

8
Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc
View File

@@ -1625,14 +1625,6 @@ define pcodeop lbzcixOp;
RT = *:1 A; RT = *:1 A;
} }
# binutils-descr: "eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}
define pcodeop eieioOp;
# ISA-cmt: eieio - Enforce In-order Execution of I/O
# ISA-info: eieio - Form "X" Page 698 Category "S"
# binutils: mytest.d: 20: 7c 00 06 ac eieio
:eieio is $(NOTVLE) & OP=31 & XOP_1_10=854 & BITS_11_25=0 & BIT_0=0 { eieioOp(); }
# binutils-descr: "ldcix", X(31,885), X_MASK, POWER6, PPCNONE, {RT, RA0, RB} # binutils-descr: "ldcix", X(31,885), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}
# ISA-cmt: ldcix - Load Doubleword Caching Inhibited Indexed # ISA-cmt: ldcix - Load Doubleword Caching Inhibited Indexed
# ISA-info: ldcix - Form "X" Page 749 Category "S" # ISA-info: ldcix - Form "X" Page 749 Category "S"

9
Ghidra/Processors/PowerPC/data/languages/quicciii.sinc
View File

@@ -8,7 +8,6 @@ define pcodeop debuggerNotifyHalt;
define pcodeop instructionCacheBlockClearLock; define pcodeop instructionCacheBlockClearLock;
define pcodeop queryInstructionCacheBlockLock; define pcodeop queryInstructionCacheBlockLock;
define pcodeop prefetchInstructionCacheBlockLockSetX; define pcodeop prefetchInstructionCacheBlockLockSetX;
define pcodeop memoryBarrier;
define pcodeop moveFromAPIDIndirect; define pcodeop moveFromAPIDIndirect;
define pcodeop moveFromPerformanceMonitorRegister; define pcodeop moveFromPerformanceMonitorRegister;
define pcodeop moveToPerformanceMonitorRegister; define pcodeop moveToPerformanceMonitorRegister;
@@ -70,14 +69,6 @@ define pcodeop invalidateTLB;
# D = (zext(CC_X_OP) * RA_OR_ZERO) + (zext(!CC_X_OP) * B); # D = (zext(CC_X_OP) * RA_OR_ZERO) + (zext(!CC_X_OP) * B);
} }
@ifndef IS_ISA
#mbar 0 #FIXME
:mbar MO is OP=31 & MO & XOP_1_10=854
{
memoryBarrier(MO:1);
}
@endif
#mfapidi r0,r1 #FIXME #mfapidi r0,r1 #FIXME
:mfapidi D,A is $(NOTVLE) & OP=31 & D & A & XOP_1_10=275 :mfapidi D,A is $(NOTVLE) & OP=31 & D & A & XOP_1_10=275
{ {