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321c3455a342daee4d435b06eb7f3d32cbaea541
ghidra/Ghidra/Processors/RISCV/data/languages
History
emteere 321c3455a3 GP-2878 Adjusted RISCV function start pattern totalbits and postbits and instruction flow / decode changes, don't decode 0x0000 as unimpl
2022-12-01 19:33:53 -05:00
..
riscv32-fp.cspec
RISC-V processor
2019-12-10 14:04:05 -06:00
riscv32.cspec
GP-2878 Adjusted RISCV function start pattern totalbits and postbits and instruction flow / decode changes, don't decode 0x0000 as unimpl
2022-12-01 19:33:53 -05:00
riscv32.dwarf
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv64-fp.cspec
Bad long size (and alignment)
2020-12-27 22:29:04 -06:00
riscv64.cspec
GP-2878 Adjusted RISCV function start pattern totalbits and postbits and instruction flow / decode changes, don't decode 0x0000 as unimpl
2022-12-01 19:33:53 -05:00
riscv64.dwarf
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv.csr.sinc
GP-358_emteere Minor RISV code review changes
2020-11-03 16:41:29 -05:00
riscv.custom.sinc
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv.ilp32d.slaspec
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv.instr.sinc
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv.ldefs
GP-1409 implemented code review suggestion
2021-11-05 09:36:43 -04:00
riscv.lp64d.slaspec
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv.opinion
Opinion fix
2020-11-03 16:41:27 -05:00
riscv.priv.sinc
GP-358_emteere Minor RISV code review changes
2020-11-03 16:41:29 -05:00
riscv.reg.sinc
GP-2878 Adjusted RISCV function start pattern totalbits and postbits and instruction flow / decode changes, don't decode 0x0000 as unimpl
2022-12-01 19:33:53 -05:00
riscv.rv32a.sinc
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv.rv32b.sinc
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv.rv32d.sinc
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv.rv32f.sinc
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv.rv32i.sinc
GP-2878 Adjusted RISCV function start pattern totalbits and postbits and instruction flow / decode changes, don't decode 0x0000 as unimpl
2022-12-01 19:33:53 -05:00
riscv.rv32k.sinc
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv.rv32m.sinc
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv.rv32p.sinc
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv.rv32q.sinc
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv.rv64a.sinc
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv.rv64b.sinc
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv.rv64d.sinc
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv.rv64f.sinc
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv.rv64i.sinc
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv.rv64k.sinc
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv.rv64m.sinc
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv.rv64p.sinc
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv.rv64q.sinc
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv.rvc.sinc
GP-2878 Adjusted RISCV function start pattern totalbits and postbits and instruction flow / decode changes, don't decode 0x0000 as unimpl
2022-12-01 19:33:53 -05:00
riscv.rvv.sinc
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
riscv.table.sinc
GP-2878 Adjusted RISCV function start pattern totalbits and postbits and instruction flow / decode changes, don't decode 0x0000 as unimpl
2022-12-01 19:33:53 -05:00
riscv.zi.sinc
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
RV32G.pspec
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
RV32GC.pspec
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
RV32I.pspec
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
RV32IC.pspec
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
RV32IMC.pspec
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
RV64G.pspec
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
RV64GC.pspec
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
RV64I.pspec
Update to RISCV processor module
2020-11-03 16:41:26 -05:00
RV64IC.pspec
Update to RISCV processor module
2020-11-03 16:41:26 -05:00