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hexagon: refresh comments to reflect current support

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Records the decode coverage this branch adds (V66 ZReg matrix extension
and V81 valign4, both decode-only stubs) and narrows the shift-amount
KNOWN ISSUE to what is actually fixed: register-form shifts now model
the 7-bit signed shift amount, other forms may still assume positive.
This commit is contained in:
Shawn Hoffman
2026-08-28 21:55:29 -07:00
committed by ghidra1
parent d29b9c718f
commit 0345ff83cf
3 changed files with 8 additions and 4 deletions
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2
Ghidra/Processors/Hexagon/data/languages/hexagon.sinc
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@@ -1,4 +1,4 @@
# Qualcomm Hexagon (V73) General Instruction Set
# Qualcomm Hexagon (V60-V81) General Instruction Set
#
# Custom pcode-op

8
Ghidra/Processors/Hexagon/data/languages/hexagon.slaspec
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@@ -1,12 +1,14 @@
# Qualcomm Hexagon (V79) and HVX (V79)
## KNOWN ISSUES
# 1. Shift amounts may be positive or negative, however in some cases no special handling
# is provided for negative shift amounts.
# 1. Shift amounts may be positive or negative. The register-form shifts model the
# 7-bit signed shift amount explicitly; other forms may still assume a positive amount.
# 2. There are many complex instructions with unimplemented pcode or simple custom pcodeops
#
## NOTES
# 1. Implementation includes V73 system registers, instruction set may be incomplete
# 1. Implementation includes V73 system registers, instruction set may be incomplete.
# Decode additionally covers the V66 ZReg matrix extension and V81 valign4 as
# decode-only stubs (unimpl pcode).
# 2. HVX register pairs may be access with a vector-swap mode (lsb of 5-bit field is 1)
# introduced with Hexagon v67.
# 3. HVX vector register size is 128-bytes (see defines below), paired size is 256-bytes,

2
Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.sinc
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@@ -2,6 +2,8 @@
# NOTES:
# - HVX implementation has been updated through V79
# - Decode additionally covers the V66 ZReg matrix family (vrmpyz / vr8mpyz / vr16mpyz
# and the z-register loads) plus V81 valign4, as decode-only stubs (unimpl pcode).
# - HVX hardware supports either 64-byte or 128-byte vector lengths. See hexagon.slaspec for
# default length of 128-bytes.