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Merge remote-tracking branch 'origin/patch'

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This commit is contained in:
Ryan Kurtz
2026-06-10 11:06:15 -04:00
parent 98b65295e5 99780aceed
commit 42af38e97d
8 changed files with 950 additions and 575 deletions
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2
Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
View File

@@ -2775,7 +2775,7 @@ mrsipsr: "i" is thc0000=1 & Rd0811 {
b:1 = isCurrentModePrivileged();
if (!b) goto <notPriv>;
ipsr:4 = getCurrentExceptionNumber();
Rd0811 = Rd0811 | (ipsr & 0x1f);
Rd0811 = Rd0811 | (ipsr & 0x1ff);
<notPriv>
}
mrsipsr: is thc0000=0 { }

165
Ghidra/Processors/x86/data/languages/avx.sinc
View File

@@ -95,63 +95,97 @@ define pcodeop vaddsubps_avx ;
}
# ANDPD 3-64 PAGE 634 LINE 34821
define pcodeop vandpd_avx ;
:VANDPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vandpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
ZmmReg1 = zext(tmp);
local m:16 = XmmReg2_m128;
XmmReg1[0,64] = vexVVVV_XmmReg[0,64] & m[0,64];
XmmReg1[64,64] = vexVVVV_XmmReg[64,64] & m[64,64];
ZmmReg1 = zext(XmmReg1);
}
# ANDPD 3-64 PAGE 634 LINE 34824
:VANDPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
{
local tmp:32 = vandpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );
ZmmReg1 = zext(tmp);
local m:32 = YmmReg2_m256;
YmmReg1[0,64] = vexVVVV_YmmReg[0,64] & m[0,64];
YmmReg1[64,64] = vexVVVV_YmmReg[64,64] & m[64,64];
YmmReg1[128,64] = vexVVVV_YmmReg[128,64] & m[128,64];
YmmReg1[192,64] = vexVVVV_YmmReg[192,64] & m[192,64];
ZmmReg1 = zext(YmmReg1);
}
# ANDPS 3-67 PAGE 637 LINE 34947
define pcodeop vandps_avx ;
:VANDPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vandps_avx( vexVVVV_XmmReg, XmmReg2_m128 );
ZmmReg1 = zext(tmp);
local tmp:16 = XmmReg2_m128;
XmmReg1[0,32] = vexVVVV_XmmReg[0,32] & tmp[0,32];
XmmReg1[32,32] = vexVVVV_XmmReg[32,32] & tmp[32,32];
XmmReg1[64,32] = vexVVVV_XmmReg[64,32] & tmp[64,32];
XmmReg1[96,32] = vexVVVV_XmmReg[96,32] & tmp[96,32];
ZmmReg1 = zext(XmmReg1);
}
# ANDPS 3-67 PAGE 637 LINE 34950
:VANDPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
{
local tmp:32 = vandps_avx( vexVVVV_YmmReg, YmmReg2_m256 );
ZmmReg1 = zext(tmp);
local tmp:32 = YmmReg2_m256;
YmmReg1[0,32] = vexVVVV_YmmReg[0,32] & tmp[0,32];
YmmReg1[32,32] = vexVVVV_YmmReg[32,32] & tmp[32,32];
YmmReg1[64,32] = vexVVVV_YmmReg[64,32] & tmp[64,32];
YmmReg1[96,32] = vexVVVV_YmmReg[96,32] & tmp[96,32];
YmmReg1[128,32] = vexVVVV_YmmReg[128,32] & tmp[128,32];
YmmReg1[160,32] = vexVVVV_YmmReg[160,32] & tmp[160,32];
YmmReg1[192,32] = vexVVVV_YmmReg[192,32] & tmp[192,32];
YmmReg1[224,32] = vexVVVV_YmmReg[224,32] & tmp[224,32];
ZmmReg1 = zext(YmmReg1);
}
# ANDNPD 3-70 PAGE 640 LINE 35081
define pcodeop vandnpd_avx ;
:VANDNPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vandnpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
ZmmReg1 = zext(tmp);
local m:16 = XmmReg2_m128;
XmmReg1[0,64] = ~vexVVVV_XmmReg[0,64] & m[0,64];
XmmReg1[64,64] = ~vexVVVV_XmmReg[64,64] & m[64,64];
ZmmReg1 = zext(XmmReg1);
}
# ANDNPD 3-70 PAGE 640 LINE 35084
:VANDNPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x55; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
{
local tmp:32 = vandnpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );
ZmmReg1 = zext(tmp);
local m:32 = YmmReg2_m256;
YmmReg1[0,64] = ~vexVVVV_YmmReg[0,64] & m[0,64];
YmmReg1[64,64] = ~vexVVVV_YmmReg[64,64] & m[64,64];
YmmReg1[128,64] = ~vexVVVV_YmmReg[128,64] & m[128,64];
YmmReg1[192,64] = ~vexVVVV_YmmReg[192,64] & m[192,64];
ZmmReg1 = zext(YmmReg1);
}
# ANDNPS 3-73 PAGE 643 LINE 35207
define pcodeop vandnps_avx ;
:VANDNPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vandnps_avx( vexVVVV_XmmReg, XmmReg2_m128 );
ZmmReg1 = zext(tmp);
local tmp:16 = XmmReg2_m128;
XmmReg1[0,32] = ~vexVVVV_XmmReg[0,32] & tmp[0,32];
XmmReg1[32,32] = ~vexVVVV_XmmReg[32,32] & tmp[32,32];
XmmReg1[64,32] = ~vexVVVV_XmmReg[64,32] & tmp[64,32];
XmmReg1[96,32] = ~vexVVVV_XmmReg[96,32] & tmp[96,32];
ZmmReg1 = zext(XmmReg1);
}
# ANDNPS 3-73 PAGE 643 LINE 35210
:VANDNPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x55; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
{
local tmp:32 = vandnps_avx( vexVVVV_YmmReg, YmmReg2_m256 );
ZmmReg1 = zext(tmp);
local tmp:32 = YmmReg2_m256;
YmmReg1[0,32] = ~vexVVVV_YmmReg[0,32] & tmp[0,32];
YmmReg1[32,32] = ~vexVVVV_YmmReg[32,32] & tmp[32,32];
YmmReg1[64,32] = ~vexVVVV_YmmReg[64,32] & tmp[64,32];
YmmReg1[96,32] = ~vexVVVV_YmmReg[96,32] & tmp[96,32];
YmmReg1[128,32] = ~vexVVVV_YmmReg[128,32] & tmp[128,32];
YmmReg1[160,32] = ~vexVVVV_YmmReg[160,32] & tmp[160,32];
YmmReg1[192,32] = ~vexVVVV_YmmReg[192,32] & tmp[192,32];
YmmReg1[224,32] = ~vexVVVV_YmmReg[224,32] & tmp[224,32];
ZmmReg1 = zext(YmmReg1);
}
# BLENDPD 3-78 PAGE 648 LINE 35433
@@ -1475,30 +1509,30 @@ define pcodeop vmpsadbw_avx ;
define pcodeop vorpd_avx ;
:VORPD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vorpd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
ZmmReg1 = zext(tmp);
XmmReg1 = vexVVVV_XmmReg | XmmReg2_m128;
ZmmReg1 = zext(XmmReg1);
}
# ORPD 4-168 PAGE 1288 LINE 66722
:VORPD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
{
local tmp:32 = vorpd_avx( vexVVVV_YmmReg, YmmReg2_m256 );
ZmmReg1 = zext(tmp);
YmmReg1 = vexVVVV_YmmReg | YmmReg2_m256;
ZmmReg1 = zext(YmmReg1);
}
# ORPS 4-171 PAGE 1291 LINE 66846
define pcodeop vorps_avx ;
:VORPS XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vorps_avx( vexVVVV_XmmReg, XmmReg2_m128 );
ZmmReg1 = zext(tmp);
XmmReg1 = vexVVVV_XmmReg | XmmReg2_m128;
ZmmReg1 = zext(XmmReg1);
}
# ORPS 4-171 PAGE 1291 LINE 66848
:VORPS YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & vexVVVV_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
{
local tmp:32 = vorps_avx( vexVVVV_YmmReg, YmmReg2_m256 );
ZmmReg1 = zext(tmp);
YmmReg1 = vexVVVV_YmmReg | YmmReg2_m256;
ZmmReg1 = zext(YmmReg1);
}
# PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67302
@@ -1561,24 +1595,53 @@ define pcodeop vpackuswb_avx ;
define pcodeop vpaddb_avx ;
:VPADDB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vpaddb_avx( vexVVVV_XmmReg, XmmReg2_m128 );
ZmmReg1 = zext(tmp);
local result:16 = 0;
result[0,8] = vexVVVV_XmmReg[0,8] + XmmReg2_m128[0,8];
result[8,8] = vexVVVV_XmmReg[8,8] + XmmReg2_m128[8,8];
result[16,8] = vexVVVV_XmmReg[16,8] + XmmReg2_m128[16,8];
result[24,8] = vexVVVV_XmmReg[24,8] + XmmReg2_m128[24,8];
result[32,8] = vexVVVV_XmmReg[32,8] + XmmReg2_m128[32,8];
result[40,8] = vexVVVV_XmmReg[40,8] + XmmReg2_m128[40,8];
result[48,8] = vexVVVV_XmmReg[48,8] + XmmReg2_m128[48,8];
result[56,8] = vexVVVV_XmmReg[56,8] + XmmReg2_m128[56,8];
result[64,8] = vexVVVV_XmmReg[64,8] + XmmReg2_m128[64,8];
result[72,8] = vexVVVV_XmmReg[72,8] + XmmReg2_m128[72,8];
result[80,8] = vexVVVV_XmmReg[80,8] + XmmReg2_m128[80,8];
result[88,8] = vexVVVV_XmmReg[88,8] + XmmReg2_m128[88,8];
result[96,8] = vexVVVV_XmmReg[96,8] + XmmReg2_m128[96,8];
result[104,8] = vexVVVV_XmmReg[104,8] + XmmReg2_m128[104,8];
result[112,8] = vexVVVV_XmmReg[112,8] + XmmReg2_m128[112,8];
result[120,8] = vexVVVV_XmmReg[120,8] + XmmReg2_m128[120,8];
ZmmReg1 = zext(result);
}
# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68660
define pcodeop vpaddw_avx ;
:VPADDW XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vpaddw_avx( vexVVVV_XmmReg, XmmReg2_m128 );
ZmmReg1 = zext(tmp);
local result:16 = 0;
result[0,16] = vexVVVV_XmmReg[0,16] + XmmReg2_m128[0,16];
result[16,16] = vexVVVV_XmmReg[16,16] + XmmReg2_m128[16,16];
result[32,16] = vexVVVV_XmmReg[32,16] + XmmReg2_m128[32,16];
result[48,16] = vexVVVV_XmmReg[48,16] + XmmReg2_m128[48,16];
result[64,16] = vexVVVV_XmmReg[64,16] + XmmReg2_m128[64,16];
result[80,16] = vexVVVV_XmmReg[80,16] + XmmReg2_m128[80,16];
result[96,16] = vexVVVV_XmmReg[96,16] + XmmReg2_m128[96,16];
result[112,16] = vexVVVV_XmmReg[112,16] + XmmReg2_m128[112,16];
ZmmReg1 = zext(result);
}
# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68662
define pcodeop vpaddd_avx ;
:VPADDD XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
{
local tmp:16 = vpaddd_avx( vexVVVV_XmmReg, XmmReg2_m128 );
ZmmReg1 = zext(tmp);
local result:16 = 0;
result[0,32] = vexVVVV_XmmReg[0,32] + XmmReg2_m128[0,32];
result[32,32] = vexVVVV_XmmReg[32,32] + XmmReg2_m128[32,32];
result[64,32] = vexVVVV_XmmReg[64,32] + XmmReg2_m128[64,32];
result[96,32] = vexVVVV_XmmReg[96,32] + XmmReg2_m128[96,32];
ZmmReg1 = zext(result);
}
# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68664
@@ -1885,24 +1948,6 @@ define pcodeop vpinsrb_avx ;
ZmmReg1 = zext(tmp);
}
# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73324
define pcodeop vpinsrd_avx ;
:VPINSRD XmmReg1, vexVVVV_XmmReg, rm32, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x22; (XmmReg1 & ZmmReg1) ... & rm32; imm8
{
local tmp:16 = vpinsrd_avx( vexVVVV_XmmReg, rm32, imm8:1 );
ZmmReg1 = zext(tmp);
}
# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73327
define pcodeop vpinsrq_avx ;
@ifdef IA64
:VPINSRQ XmmReg1, vexVVVV_XmmReg, rm64, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x22; (XmmReg1 & ZmmReg1) ... & rm64; imm8
{
local tmp:16 = vpinsrq_avx( vexVVVV_XmmReg, rm64, imm8:1 );
ZmmReg1 = zext(tmp);
}
@endif
# PINSRW 4-296 PAGE 1416 LINE 73446
define pcodeop vpinsrw_avx ;
:VPINSRW XmmReg1, vexVVVV_XmmReg, Reg32_m16, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xC4; (XmmReg1 & ZmmReg1) ... & Reg32_m16; imm8
@@ -2688,19 +2733,21 @@ define pcodeop vsqrtps_avx ;
}
# SQRTSD 4-638 PAGE 1758 LINE 91272
define pcodeop vsqrtsd_avx ;
:VSQRTSD XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64
{
local tmp:16 = vsqrtsd_avx( vexVVVV_XmmReg, XmmReg2_m64 );
ZmmReg1 = zext(tmp);
local m:16 = XmmReg2_m64;
XmmReg1[0,64] = sqrt(vexVVVV_XmmReg[0,64]);
XmmReg1[64,64]= m[64,64];
ZmmReg1 = zext(XmmReg1);
}
# SQRTSS 4-640 PAGE 1760 LINE 91367
define pcodeop vsqrtss_avx ;
:VSQRTSS XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32
{
local tmp:16 = vsqrtss_avx( vexVVVV_XmmReg, XmmReg2_m32 );
ZmmReg1 = zext(tmp);
local m:16 = XmmReg2_m32;
XmmReg1[0,32] = sqrt(vexVVVV_XmmReg[0,32]);
XmmReg1[32,96]= m[32,96];
ZmmReg1 = zext(XmmReg1);
}
# STMXCSR 4-647 PAGE 1767 LINE 91697

84
Ghidra/Processors/x86/data/languages/avx2.sinc
View File

@@ -75,35 +75,95 @@ define pcodeop vpackuswb_avx2 ;
}
# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68666
define pcodeop vpaddb_avx2 ;
:VPADDB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xFC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
{
local tmp:32 = vpaddb_avx2( vexVVVV_YmmReg, YmmReg2_m256 );
ZmmReg1 = zext(tmp);
local result:32 = 0;
result[0,8] = vexVVVV_YmmReg[0,8] + YmmReg2_m256[0,8];
result[8,8] = vexVVVV_YmmReg[8,8] + YmmReg2_m256[8,8];
result[16,8] = vexVVVV_YmmReg[16,8] + YmmReg2_m256[16,8];
result[24,8] = vexVVVV_YmmReg[24,8] + YmmReg2_m256[24,8];
result[32,8] = vexVVVV_YmmReg[32,8] + YmmReg2_m256[32,8];
result[40,8] = vexVVVV_YmmReg[40,8] + YmmReg2_m256[40,8];
result[48,8] = vexVVVV_YmmReg[48,8] + YmmReg2_m256[48,8];
result[56,8] = vexVVVV_YmmReg[56,8] + YmmReg2_m256[56,8];
result[64,8] = vexVVVV_YmmReg[64,8] + YmmReg2_m256[64,8];
result[72,8] = vexVVVV_YmmReg[72,8] + YmmReg2_m256[72,8];
result[80,8] = vexVVVV_YmmReg[80,8] + YmmReg2_m256[80,8];
result[88,8] = vexVVVV_YmmReg[88,8] + YmmReg2_m256[88,8];
result[96,8] = vexVVVV_YmmReg[96,8] + YmmReg2_m256[96,8];
result[104,8] = vexVVVV_YmmReg[104,8] + YmmReg2_m256[104,8];
result[112,8] = vexVVVV_YmmReg[112,8] + YmmReg2_m256[112,8];
result[120,8] = vexVVVV_YmmReg[120,8] + YmmReg2_m256[120,8];
result[128,8] = vexVVVV_YmmReg[128,8] + YmmReg2_m256[128,8];
result[136,8] = vexVVVV_YmmReg[136,8] + YmmReg2_m256[136,8];
result[144,8] = vexVVVV_YmmReg[144,8] + YmmReg2_m256[144,8];
result[152,8] = vexVVVV_YmmReg[152,8] + YmmReg2_m256[152,8];
result[160,8] = vexVVVV_YmmReg[160,8] + YmmReg2_m256[160,8];
result[168,8] = vexVVVV_YmmReg[168,8] + YmmReg2_m256[168,8];
result[176,8] = vexVVVV_YmmReg[176,8] + YmmReg2_m256[176,8];
result[184,8] = vexVVVV_YmmReg[184,8] + YmmReg2_m256[184,8];
result[192,8] = vexVVVV_YmmReg[192,8] + YmmReg2_m256[192,8];
result[200,8] = vexVVVV_YmmReg[200,8] + YmmReg2_m256[200,8];
result[208,8] = vexVVVV_YmmReg[208,8] + YmmReg2_m256[208,8];
result[216,8] = vexVVVV_YmmReg[216,8] + YmmReg2_m256[216,8];
result[224,8] = vexVVVV_YmmReg[224,8] + YmmReg2_m256[224,8];
result[232,8] = vexVVVV_YmmReg[232,8] + YmmReg2_m256[232,8];
result[240,8] = vexVVVV_YmmReg[240,8] + YmmReg2_m256[240,8];
result[248,8] = vexVVVV_YmmReg[248,8] + YmmReg2_m256[248,8];
ZmmReg1 = zext(result);
}
# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68668
define pcodeop vpaddw_avx2 ;
:VPADDW YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xFD; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
{
local tmp:32 = vpaddw_avx2( vexVVVV_YmmReg, YmmReg2_m256 );
ZmmReg1 = zext(tmp);
local result:32 = 0;
result[0,16] = vexVVVV_YmmReg[0,16] + YmmReg2_m256[0,16];
result[16,16] = vexVVVV_YmmReg[16,16] + YmmReg2_m256[16,16];
result[32,16] = vexVVVV_YmmReg[32,16] + YmmReg2_m256[32,16];
result[48,16] = vexVVVV_YmmReg[48,16] + YmmReg2_m256[48,16];
result[64,16] = vexVVVV_YmmReg[64,16] + YmmReg2_m256[64,16];
result[80,16] = vexVVVV_YmmReg[80,16] + YmmReg2_m256[80,16];
result[96,16] = vexVVVV_YmmReg[96,16] + YmmReg2_m256[96,16];
result[112,16] = vexVVVV_YmmReg[112,16] + YmmReg2_m256[112,16];
result[128,16] = vexVVVV_YmmReg[128,16] + YmmReg2_m256[128,16];
result[144,16] = vexVVVV_YmmReg[144,16] + YmmReg2_m256[144,16];
result[160,16] = vexVVVV_YmmReg[160,16] + YmmReg2_m256[160,16];
result[176,16] = vexVVVV_YmmReg[176,16] + YmmReg2_m256[176,16];
result[192,16] = vexVVVV_YmmReg[192,16] + YmmReg2_m256[192,16];
result[208,16] = vexVVVV_YmmReg[208,16] + YmmReg2_m256[208,16];
result[224,16] = vexVVVV_YmmReg[224,16] + YmmReg2_m256[224,16];
result[240,16] = vexVVVV_YmmReg[240,16] + YmmReg2_m256[240,16];
ZmmReg1 = zext(result);
}
# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68670
define pcodeop vpaddd_avx2 ;
:VPADDD YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xFE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
{
local tmp:32 = vpaddd_avx2( vexVVVV_YmmReg, YmmReg2_m256 );
ZmmReg1 = zext(tmp);
local result:32 = 0;
result[0,32] = vexVVVV_YmmReg[0,32] + YmmReg2_m256[0,32];
result[32,32] = vexVVVV_YmmReg[32,32] + YmmReg2_m256[32,32];
result[64,32] = vexVVVV_YmmReg[64,32] + YmmReg2_m256[64,32];
result[96,32] = vexVVVV_YmmReg[96,32] + YmmReg2_m256[96,32];
result[128,32] = vexVVVV_YmmReg[128,32] + YmmReg2_m256[128,32];
result[160,32] = vexVVVV_YmmReg[160,32] + YmmReg2_m256[160,32];
result[192,32] = vexVVVV_YmmReg[192,32] + YmmReg2_m256[192,32];
result[224,32] = vexVVVV_YmmReg[224,32] + YmmReg2_m256[224,32];
ZmmReg1 = zext(result);
}
# PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68672
define pcodeop vpaddq_avx2 ;
:VPADDQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD4; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
{
local tmp:32 = vpaddq_avx2( vexVVVV_YmmReg, YmmReg2_m256 );
ZmmReg1 = zext(tmp);
local result:32 = 0;
result[0,64] = vexVVVV_YmmReg[0,64] + YmmReg2_m256[0,64];
result[64,64] = vexVVVV_YmmReg[64,64] + YmmReg2_m256[64,64];
result[128,64] = vexVVVV_YmmReg[128,64] + YmmReg2_m256[128,64];
result[192,64] = vexVVVV_YmmReg[192,64] + YmmReg2_m256[192,64];
ZmmReg1 = zext(result);
}
# PADDSB/PADDSW 4-211 PAGE 1331 LINE 69045

20
Ghidra/Processors/x86/data/languages/avx2_manual.sinc
View File

@@ -1,13 +1,15 @@
# VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109785
define pcodeop vinserti128 ;
:VINSERTI128 YmmReg1, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x38; YmmReg1 ... & XmmReg2_m128; imm8 & imm8_0 {
local tmp:16 = XmmReg2_m128;
local cond0:16 = zext((imm8_0:1 & 0x1) == 0);
local cond1:16 = zext((imm8_0:1 & 0x1) == 1);
# ignoring all but the least significant bit
YmmReg1[0,128] = (cond0 * tmp) + (cond1 * vexVVVV_YmmReg[0,128]);
YmmReg1[128,128] = (cond0 * vexVVVV_YmmReg[128,128]) + (cond1 * tmp);
:VINSERTI128 YmmReg1, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x38; YmmReg1 ... & XmmReg2_m128; imm8 & imm8_0{
local scr1l:16 = vexVVVV_YmmReg[0,128];
local scr1h:16 = vexVVVV_YmmReg[128,128];
local src2:16 = XmmReg2_m128;
local vcond:1 = (imm8_0:1 & 0x1) == 0;
local part1:16 = 0;
conditionalAssign(part1, vcond, src2, scr1l);
local part2:16 = 0;
conditionalAssign(part2, vcond, scr1h, src2);
YmmReg1[0,128] = part1;
YmmReg1[128,128] = part2;
}
# VGATHERDPD/VGATHERQPD 5-251 PAGE 2075 LINE 106903

120
Ghidra/Processors/x86/data/languages/avx512.sinc
View File

@@ -2140,11 +2140,10 @@ define pcodeop vmulss_avx512f ;
}
# ORPD 4-168 PAGE 1288 LINE 66724
define pcodeop vorpd_avx512vl ;
:VORPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
{
XmmResult = vorpd_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
XmmResult = evexV5_XmmReg | XmmReg2_m128_m64bcst;
XmmMask = XmmReg1;
build XmmOpMask64;
ZmmReg1 = zext(XmmResult);
@@ -2154,29 +2153,27 @@ define pcodeop vorpd_avx512vl ;
:VORPD YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
{
YmmResult = vorpd_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
YmmResult = evexV5_YmmReg | YmmReg2_m256_m64bcst;
YmmMask = YmmReg1;
build YmmOpMask64;
ZmmReg1 = zext(YmmResult);
}
# ORPD 4-168 PAGE 1288 LINE 66730
define pcodeop vorpd_avx512dq ;
:VORPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x56; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
{
ZmmResult = vorpd_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
ZmmResult = evexV5_ZmmReg | ZmmReg2_m512_m64bcst;
ZmmMask = ZmmReg1;
build ZmmOpMask64;
ZmmReg1 = ZmmResult;
}
# ORPS 4-171 PAGE 1291 LINE 66850
define pcodeop vorps_avx512vl ;
:VORPS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
{
XmmResult = vorps_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
XmmResult = evexV5_XmmReg | XmmReg2_m128_m32bcst;
XmmMask = XmmReg1;
build XmmOpMask32;
ZmmReg1 = zext(XmmResult);
@@ -2186,18 +2183,17 @@ define pcodeop vorps_avx512vl ;
:VORPS YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
{
YmmResult = vorps_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
YmmResult = evexV5_YmmReg | YmmReg2_m256_m32bcst;
YmmMask = YmmReg1;
build YmmOpMask32;
ZmmReg1 = zext(YmmResult);
}
# ORPS 4-171 PAGE 1291 LINE 66856
define pcodeop vorps_avx512dq ;
:VORPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x56; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
{
ZmmResult = vorps_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
ZmmResult = evexV5_ZmmReg | ZmmReg2_m512_m32bcst;
ZmmMask = ZmmReg1;
build ZmmOpMask32;
ZmmReg1 = ZmmResult;
@@ -2717,20 +2713,20 @@ define pcodeop vpaddusw_avx512bw ;
# PALIGNR 4-219 PAGE 1339 LINE 69495
define pcodeop vpalignr_avx512vl ;
:VPALIGNR XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_XmmReg; byte=0x0F; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128
:VPALIGNR XmmReg1^XmmOpMask8, evexV5_XmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_XmmReg; byte=0x0F; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128; imm8
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
{
XmmResult = vpalignr_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
XmmResult = vpalignr_avx512vl( evexV5_XmmReg, XmmReg2_m128, imm8:1 );
XmmMask = XmmReg1;
build XmmOpMask8;
ZmmReg1 = zext(XmmResult);
}
# PALIGNR 4-219 PAGE 1339 LINE 69499
:VPALIGNR YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_YmmReg; byte=0x0F; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256
:VPALIGNR YmmReg1^YmmOpMask8, evexV5_YmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_YmmReg; byte=0x0F; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256; imm8
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
{
YmmResult = vpalignr_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
YmmResult = vpalignr_avx512vl( evexV5_YmmReg, YmmReg2_m256, imm8:1 );
YmmMask = YmmReg1;
build YmmOpMask8;
ZmmReg1 = zext(YmmResult);
@@ -2738,15 +2734,16 @@ define pcodeop vpalignr_avx512vl ;
# PALIGNR 4-219 PAGE 1339 LINE 69505
define pcodeop vpalignr_avx512bw ;
:VPALIGNR ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x0F; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512
:VPALIGNR ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x0F; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512; imm8
[ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM)
{
ZmmResult = vpalignr_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 );
ZmmResult = vpalignr_avx512bw( evexV5_ZmmReg, ZmmReg2_m512, imm8:1 );
ZmmMask = ZmmReg1;
build ZmmOpMask8;
ZmmReg1 = ZmmResult;
}
# PAND 4-223 PAGE 1343 LINE 69684
define pcodeop vpandd_avx512vl ;
:VPANDD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xDB; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
@@ -5816,70 +5813,6 @@ define pcodeop vpunpcklqdq_avx512f ;
ZmmReg1 = ZmmResult;
}
# PXOR 4-518 PAGE 1638 LINE 85503
define pcodeop vpxord_avx512vl ;
:VPXORD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
{
XmmResult = vpxord_avx512vl( evexV5_XmmReg, XmmReg2_m128_m32bcst );
XmmMask = XmmReg1;
build XmmOpMask32;
ZmmReg1 = zext(XmmResult);
}
# PXOR 4-518 PAGE 1638 LINE 85505
:VPXORD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xEF; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
{
YmmResult = vpxord_avx512vl( evexV5_YmmReg, YmmReg2_m256_m32bcst );
YmmMask = YmmReg1;
build YmmOpMask32;
ZmmReg1 = zext(YmmResult);
}
# PXOR 4-518 PAGE 1638 LINE 85507
define pcodeop vpxord_avx512f ;
:VPXORD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xEF; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
{
ZmmResult = vpxord_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst );
ZmmMask = ZmmReg1;
build ZmmOpMask32;
ZmmReg1 = ZmmResult;
}
# PXOR 4-518 PAGE 1638 LINE 85514
define pcodeop vpxorq_avx512vl ;
:VPXORQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
{
XmmResult = vpxorq_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst );
XmmMask = XmmReg1;
build XmmOpMask64;
ZmmReg1 = zext(XmmResult);
}
# PXOR 4-518 PAGE 1638 LINE 85521
:VPXORQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xEF; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
{
YmmResult = vpxorq_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst );
YmmMask = YmmReg1;
build YmmOpMask64;
ZmmReg1 = zext(YmmResult);
}
# PXOR 4-518 PAGE 1638 LINE 85523
define pcodeop vpxorq_avx512f ;
:VPXORQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xEF; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
{
ZmmResult = vpxorq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst );
ZmmMask = ZmmReg1;
build ZmmOpMask64;
ZmmReg1 = ZmmResult;
}
# SHUFPD 4-617 PAGE 1737 LINE 90231
define pcodeop vshufpd_avx512vl ;
:VSHUFPD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xC6; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8
@@ -6009,25 +5942,27 @@ define pcodeop vsqrtps_avx512f ;
}
# SQRTSD 4-638 PAGE 1758 LINE 91276
define pcodeop vsqrtsd_avx512f ;
:VSQRTSD XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64
:VSQRTSD XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m64
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
{
XmmResult = vsqrtsd_avx512f( evexV5_XmmReg, XmmReg2_m64 );
XmmResult[0,64] = sqrt(XmmReg2_m64[0,64]);
XmmMask = XmmReg1;
build XmmOpMask64;
ZmmReg1 = zext(XmmResult);
conditionalAssign(XmmResult[0,64], XmmOpMask[0,1], XmmResult[0,64], XmmMask[0,64]);
XmmReg1[0,64] = XmmResult[0,64];
XmmReg1[64,64]= evexV5_XmmReg[64,64];
ZmmReg1 = zext(XmmReg1);
}
# SQRTSS 4-640 PAGE 1760 LINE 91371
define pcodeop vsqrtss_avx512f ;
:VSQRTSS XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32
:VSQRTSS XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m32
[ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S)
{
XmmResult = vsqrtss_avx512f( evexV5_XmmReg, XmmReg2_m32 );
XmmResult[0,32] = sqrt(XmmReg2_m32[0,32]);
XmmMask = XmmReg1;
build XmmOpMask32;
ZmmReg1 = zext(XmmResult);
conditionalAssign(XmmResult[0,32], XmmOpMask[0,1], XmmResult[0,32], XmmMask[0,32]);
XmmReg1[0,32] = XmmResult[0,32];
XmmReg1[32,96]=evexV5_XmmReg[32,96];
ZmmReg1 = zext(XmmReg1);
}
# SUBPD 4-656 PAGE 1776 LINE 92120
@@ -17646,11 +17581,10 @@ define pcodeop vsqrtph_avx512fp16 ;
define pcodeop vsqrtsh_avx512fp16 ;
:VSQRTSH XmmReg1^XmmOpMask, evexV5_XmmReg, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_LLIG) & $(VEX_PRE_F3) & $(VEX_MAP5) & $(VEX_W0) & XmmOpMask & evexV5_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16
{
XmmResult = vsqrtsh_avx512fp16( evexV5_XmmReg, XmmReg2_m16 );
XmmResult[0,16] = sqrt(XmmReg2_m16[0,16]);
XmmMask = XmmReg1;
build XmmOpMask;
conditionalAssign(XmmResult[0,16], XmmOpMask[0,1], XmmResult[0,16], XmmMask[0,16]);
XmmResult[16,112] = XmmReg1[16,112]; # DEST[127:16] remains unchanged
XmmResult[16,112] = evexV5_XmmReg[16,112]; # DEST[127:16] = src1[127:16]
ZmmReg1 = zext(XmmResult);
}

63
Ghidra/Processors/x86/data/languages/avx512_manual.sinc
View File

@@ -1582,4 +1582,65 @@ define pcodeop vpmovuswb_avx512bw ;
YmmMask = m256;
build YmmOpMask8;
m256 = zext(YmmResult);
}
}
# PXOR 4-518 PAGE 1638 LINE 85503
:VPXORD XmmReg1^XmmOpMask32, evexV5_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
{
XmmResult = evexV5_XmmReg ^ XmmReg2_m128_m32bcst;
XmmMask = XmmReg1;
build XmmOpMask32;
ZmmReg1 = zext(XmmResult);
}
# PXOR 4-518 PAGE 1638 LINE 85505
:VPXORD YmmReg1^YmmOpMask32, evexV5_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_YmmReg; byte=0xEF; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
{
YmmResult = evexV5_YmmReg ^ YmmReg2_m256_m32bcst;
YmmMask = YmmReg1;
build YmmOpMask32;
ZmmReg1 = zext(YmmResult);
}
# PXOR 4-518 PAGE 1638 LINE 85507
:VPXORD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xEF; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
{
ZmmResult = evexV5_ZmmReg ^ ZmmReg2_m512_m32bcst;
ZmmMask = ZmmReg1;
build ZmmOpMask32;
ZmmReg1 = ZmmResult;
}
# PXOR 4-518 PAGE 1638 LINE 85514
:VPXORQ XmmReg1^XmmOpMask64, evexV5_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
{
XmmResult = evexV5_XmmReg ^ XmmReg2_m128_m64bcst;
XmmMask = XmmReg1;
build XmmOpMask64;
ZmmReg1 = zext(XmmResult);
}
# PXOR 4-518 PAGE 1638 LINE 85521
:VPXORQ YmmReg1^YmmOpMask64, evexV5_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_YmmReg; byte=0xEF; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
{
YmmResult = evexV5_YmmReg ^ YmmReg2_m256_m64bcst;
YmmMask = YmmReg1;
build YmmOpMask64;
ZmmReg1 = zext(YmmResult);
}
# PXOR 4-518 PAGE 1638 LINE 85523
:VPXORQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xEF; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst
[ evexD8Type = 0; evexTType = 0; ] # (TupleType FV)
{
ZmmResult = evexV5_ZmmReg ^ ZmmReg2_m512_m64bcst;
ZmmMask = ZmmReg1;
build ZmmOpMask64;
ZmmReg1 = ZmmResult;
}

30
Ghidra/Processors/x86/data/languages/avx_manual.sinc
View File

@@ -192,6 +192,36 @@
ZmmReg1 = zext(XmmReg1);
}
# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73324
#define pcodeop vpinsrd_avx ;
:VPINSRD XmmReg1, vexVVVV_XmmReg, rm32, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x22; (XmmReg1 & ZmmReg1) ... & rm32; imm8
{
local tmp:4 = rm32;
local cond0:1 = (imm8:1 & 0x3) == 0;
local cond1:1 = (imm8:1 & 0x3) == 1;
local cond2:1 = (imm8:1 & 0x3) == 2;
local cond3:1 = (imm8:1 & 0x3) == 3;
conditionalAssign(XmmReg1[ 0,32], cond0, tmp, vexVVVV_XmmReg[ 0,32]);
conditionalAssign(XmmReg1[32,32], cond0, tmp, vexVVVV_XmmReg[32,32]);
conditionalAssign(XmmReg1[64,32], cond0, tmp, vexVVVV_XmmReg[64,32]);
conditionalAssign(XmmReg1[96,32], cond0, tmp, vexVVVV_XmmReg[96,32]);
ZmmReg1 = zext(XmmReg1);
}
# PINSRB/PINSRD/PINSRQ 4-293 PAGE 1413 LINE 73327
#define pcodeop vpinsrq_avx ;
@ifdef IA64
:VPINSRQ XmmReg1, vexVVVV_XmmReg, rm64, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x22; (XmmReg1 & ZmmReg1) ... & rm64; imm8
{
local tmp:8 = rm64;
local cond0:8 = zext((imm8:1 & 0x1) == 0);
local cond1:8 = zext((imm8:1 & 0x1) == 1);
# ignoring all but the least significant bit
XmmReg1[0,64] = (cond0 * tmp) + (cond1 * vexVVVV_XmmReg[0,64]);
XmmReg1[64,64] = (cond0 * vexVVVV_XmmReg[64,64]) + (cond1 * tmp);
ZmmReg1 = zext(XmmReg1);
}
@endif
# PMOVMSKB 4-338 PAGE 1458 LINE 75651
:VPMOVMSKB Reg32, XmmReg2 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xD7; Reg32 & (mod=0x3 & XmmReg2) & check_Reg32_dest

1041
Ghidra/Processors/x86/data/languages/fma.sinc
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