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c.fsw broken under double-precision

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if FP is 64, should still handle single precision
This commit is contained in:
mumbel
2020-10-31 20:47:40 -05:00
committed by ghidra1
parent a487f77918
commit 5fe0f16e10
2 changed files with 16 additions and 16 deletions
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30
Ghidra/Processors/RISCV/certification.manifest
View File

@@ -1,12 +1,15 @@
##VERSION: 2.0
Module.manifest||GHIDRA||||END|
build.gradle||GHIDRA||||END|
data/languages/riscv32.cspec||GHIDRA||||END|
data/languages/riscv32.dwarf||GHIDRA||||END|
data/languages/riscv32-fp.cspec||GHIDRA||||END|
data/languages/riscv64.cspec||GHIDRA||||END|
data/languages/riscv64.dwarf||GHIDRA||||END|
data/languages/riscv64-fp.cspec||GHIDRA||||END|
data/languages/RV32G.pspec||GHIDRA||||END|
data/languages/RV32GC.pspec||GHIDRA||||END|
data/languages/RV32I.pspec||GHIDRA||||END|
data/languages/RV32IC.pspec||GHIDRA||||END|
data/languages/RV32IMC.pspec||GHIDRA||||END|
data/languages/RV64G.pspec||GHIDRA||||END|
data/languages/RV64GC.pspec||GHIDRA||||END|
data/languages/RV64I.pspec||GHIDRA||||END|
data/languages/RV64IC.pspec||GHIDRA||||END|
data/languages/riscv.csr.sinc||GHIDRA||||END|
data/languages/riscv.custom.sinc||GHIDRA||||END|
data/languages/riscv.ilp32d.slaspec||GHIDRA||||END|
@@ -38,15 +41,12 @@ data/languages/riscv.rvc.sinc||GHIDRA||||END|
data/languages/riscv.rvv.sinc||GHIDRA||||END|
data/languages/riscv.table.sinc||GHIDRA||||END|
data/languages/riscv.zi.sinc||GHIDRA||||END|
data/languages/RV32GC.pspec||GHIDRA||||END|
data/languages/RV32G.pspec||GHIDRA||||END|
data/languages/RV32IC.pspec||GHIDRA||||END|
data/languages/RV32IMC.pspec||GHIDRA||||END|
data/languages/RV32I.pspec||GHIDRA||||END|
data/languages/RV64GC.pspec||GHIDRA||||END|
data/languages/RV64G.pspec||GHIDRA||||END|
data/languages/RV64IC.pspec||GHIDRA||||END|
data/languages/RV64I.pspec||GHIDRA||||END|
data/languages/riscv32-fp.cspec||GHIDRA||||END|
data/languages/riscv32.cspec||GHIDRA||||END|
data/languages/riscv32.dwarf||GHIDRA||||END|
data/languages/riscv64-fp.cspec||GHIDRA||||END|
data/languages/riscv64.cspec||GHIDRA||||END|
data/languages/riscv64.dwarf||GHIDRA||||END|
data/patterns/patterncontraints.xml||GHIDRA||||END|
data/patterns/riscv_gc_patterns.xml||GHIDRA||||END|
scripts/binutil.py||GHIDRA||||END|

2
Ghidra/Processors/RISCV/data/languages/riscv.rvc.sinc
View File

@@ -136,7 +136,7 @@
@endif
@if ADDRSIZE == "32"
@if FPSIZE == "32"
@if FPSIZE == "32" || FPSIZE == "64"
# c.fsw CD,Ck(Cs) 0000e000 0000e003 DWORD|DREF (32, 4)
:c.fsw cfr0204s,clwimm(cr0709s) is cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x7 & clwimm
{